NAME

	mii – MII/MDIO/SMI PHY debug driver

SYNOPSIS

	bind '#Φ' /mnt/mii /mnt/mii/bus/phy/ctl /mnt/mii/bus/phy/mii /mnt/mii/bus/phy/mmd

DESCRIPTION

Ethernet hardware is usually split into media–access (MAC) and PHY parts with a media–independent–interface (MII) in between. The MII has a electrical high–speed connection, for the ethernet frames, and a low–speed 2–wire serial connection for PHY management. There can be multiple PHYs on a single management bus. Ethernet drivers can expose this PHY management bus giving direct access to the PHYs. On its top–level directory, the driver serves a bus directory, one per controller. It is usually named by the the ethernet device that registered it (like etherN ), but it can be anything. Inside each bus directory, there appear phy directories, named by their 5–bit bus address (phy number) in decimal: 0–31. Each phy directory contains the following files: ctl, mii, mmd. The ctl file provides a textual representation of the phy status. The following text commands can be written to it: reset Reset the phy status Update the phy status fields autoneg Restart auto–negotiation on the phy The mii file allows direct access to the clause 22 registers. The read/write offset is directly mapped to the 5–bit register number: 0–31. Reads and writes needs to be exactly 2 bytes, containing the 16–bit value, with the least significant byte first. The mmd file provides access to the clause 45 registers. The lest significant 16 bits of the offset are mapped to the register number (0–65535) and the top bits [16–20] map to the device address. So accessing the ID1/ID2 register 1.1 and 1.2 map to offsets 0x10001 and 0x10002 respectively.

EXAMPLE

	Read the ID1/ID2 registers: bind '#Φ' /mnt/mii io –f /mnt/mii/ether0/1/mii –Wr 1 io –f /mnt/mii/ether0/1/mii –Wr 2

SEE ALSO

	io(1) ether(3)

SOURCE

	/sys/src/9/port/devmii.c /sys/src/9/port/ethermii.c