[ADMIN:CORE:INTERRUPT_VECTOR:MEMORY:PACKAGE:FUSE:PROGRAMMING:LOCKBIT:IO_MODULE:ICE_SETTINGS]AT86RF4018MHZ180RELEASED$1E$91$81V2[lpm rd,z+][sleep][]32$00$1B$1A$1D$1C$1F$1E3$000Hardware pin, Watchdog or Button Reset$002Transmission Done, Bit Timer Flag 2 Interrupt$004Transmit Buffer Empty, Bit Itmer Flag 0 InterruptAVRSimMemory8bit.SimMemory8bit2048128128$600NA$00$3F$20$5F$3F$5F0x010x020x040x080x100x200x400x80$3E$5E0x010x020x04$3D$5D0x010x020x040x080x100x200x400x80$35$550x010x020x040x080x100x200x400x80$34$540x010x020x040x080x100x20$33$530x010x020x040x080x100x200x40$32$520x010x020x040x080x100x20$31$510x010x020x040x080x100x20$30$500x010x020x040x080x100x20$22$420x010x020x040x080x10$21$410x010x020x040x080x100x200x400x80$20$400x010x020x040x080x100x200x400x80$1E$3E0x010x020x040x080x100x200x40$1D$3D0x010x020x040x080x100x200x400x80$1C$3C0x010x020x040x08$17$370x010x020x040x080x100x200x400x80$16$360x010x020x040x080x100x400x80$14$340x010x020x040x080x100x20$12$320x040x100x200x40$10$300x010x020x040x080x10[TSSOP]20[ANTB][LOOPFIL][L1][L2][RESETB][N/C][IO0:SDI][IO1:SDO][IO2:SCK][XTAL:CLK][XTALB][IO3][IO4][IO5][DGND][AGND][DVDD][AVDD][CFIL][ANT][LOW]0x0000[LB1 = 1 : LB2 = 1] No memory lock features enabled. [LB1 = 0 : LB2 = 1] Further programming of Flash and EEPROM is enabled. [LB1 = 0 : LB2 = 0] Same as previous, but verify is also disabled320x060x06Mode 1: No memory lock features enabled0x060x04Mode 2: Further programming disabled0x060x00Mode 3: Further programming and verification disabledLB1LockbitLB2Lockbit[RF_CONTROL:EEPROM:WATCHDOG:TIMER_COUNTER_0:PORT:CPU][LOCKDET1:LOCKDET2:TX_CNTL:PWR_ATTEN:VCOTUNE]io_cpu.bmpLOCKDET1Lock Detector Configuration Register 1$10$30io_flag.bmpYUPOKUnlock Conuter ControlRW0ENKOEnable Key On BitRW0BODBlack Out DisableRW0CS1Cycle Slip Counter bit 1RW0CS0Cycle Slip Counter bit 0RW0LOCKDET1Lock Detector Configuration register 2$17$37io_flag.bmpYEUDEnable Unlock DetectRW0LATLock Always TrueRW0ULC2Unlock Count bit 2RW0ULC1Unlock Count bit 1RW0ULC0Unlock Count bit 0RW0LC2Lock Count bit 2RW0LC1Lock Count bit 1RW0LC0Lock Count bit 0RW0TX_CNTLTransmit Control Register$12$32io_flag.bmpYFSKFSK ModeRW0TXETransmitter EnableRW0TXKTransmitter KeyRW0LOCPLL LockRW0PWR_ATTENPower Attenuation Control RegisterThis register is used to select the power attenuation level of the device.$14$34io_flag.bmpYPCC2Power Control Coarse bit 2RW0PCC1Power Control Coarse bit 1RW0PCC0Power Control Coarse bit 0RW0PCF2Power Control Fine bit 2RW0PCF1Power Control Fine bit 1RW0PCF0Power Control Fine bit 0RW0VCOTUNEVCO Tuning Register$16$36io_flag.bmpYVCOVDET1VCO Voltage Detector bit 1RW0VCOVDET0VCO Voltage Detector bit 0RW0VCOTUNE4VCO Tuning Register bit 4RW0VCOTUNE3VCO Tuning Register bit 3RW0VCOTUNE2VCO Tuning Register bit 2RW0VCOTUNE1VCO Tuning Register bit 1RW0VCOTUNE0VCO Tuning Register bit 0RW0[DEEAR:DEEDR:DEECR]io_cpu.bmpEEPROM_02.xmlDEEAREERPOM Address Register$1E$3Eio_cpu.bmpNPA6EEPROM Page Address bit 6RW0PA5EEPROM Page Address bit 5RW0PA4EEPROM Page Address bit 4RW0PA3EEPROM Page Address bit 3RW0BA2EEPROM Byte Address bit 2RW0BA1EEPROM Byte Address bit 1RW0BA0EEPROM Byte Address bit 0RW0DEEDREEPROM Data Register$1D$3Dio_cpu.bmpNED7EEPROM Data Register bit 7RW0ED6EEPROM Data Register bit 6RW0ED5EEPROM Data Register bit 5RW0ED4EEPROM Data Register bit 4RW0ED3EEPROM Data Register bit 3RW0ED2EEPROM Data Register bit 2RW0ED1EEPROM Data Register bit 1RW0ED0EEPROM Data Register bit 0RW0DEECREEPROM Control Register$1C$3Cio_flag.bmpYBSYEERPOM Busy BitR0EEUEEPROM Unlock BitRW0EELEEPROM Load BitRW0EEREEPROM Read BitRW0[WDTCR]io_watch.bmpWDTCRWatchdog Timer Control Register$22$42io_flag.bmpYWDTOEWDDERWThis bit must be set (one) when the WDE bit is cleared. Otherwise, the watchdog will not be disabled. Once set, hardware will clear this bit to zero after four clock cycles. Refer to the description of the WDE bit for a watchdog disable procedure.RW0WDEWatch Dog EnableWhen the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdogRW0WDP2Watch Dog Timer Prescaler bit 2RW0WDP1Watch Dog Timer Prescaler bit 1RW0WDP0Watch Dog Timer Prescaler bit 0RW0[BTCNT:BTCR]io_timer.bmp29569BTCNTTimer Count register$20$40io_timer.bmpNC7Timer Count Register bit 7RW0C6Timer Count Register bit 7RW0C5Timer Count Register bit 7RW0C4Timer Count Register bit 7RW0C3Timer Count Register bit 7RW0C2Timer Count Register bit 7RW0C1Timer Count Register bit 7RW0C0Timer Count Register bit 7RW0BTCRBit Timer Counter Control Register$21$41io_timer.bmpYC9Timer Count Register bit 9RW0C8Timer Count Register bit 8RW0M1Bit Timer Mode bit 1RW0M0Bit Timer Mode bit 0RW0IEInterrupt EnableRW0F2Flag 2RW0DATAData BitRW0F0Flag 0RW0[IO_ENAB:IO_DATOUT:IO_DATIN]io_port.bmpAVRSimIOPort.SimIOPortIO_ENABI/O Enable Register$30$50io_port.bmpNIOE5I/O Enable bit 5RW0IOE4I/O Enable bit 4RW0IOE3I/O Enable bit 3RW0IOE2I/O Enable bit 2RW0IOE1I/O Enable bit 1RW0IOE0I/O Enable bit 0RW0IO_DATOUTI/O Data Out Register$31$51io_port.bmpNIOO5I/O Data Out Register bit 5RW0IOO4I/O Data Out Register bit 4RW0IOO3I/O Data Out Register bit 3RW0IOO2I/O Data Out Register bit 2RW0IOO1I/O Data Out Register bit 1RW0IOO0I/O Data Out Register bit 0RW0IO_DATINI/O Data In register$32$52io_port.bmpNIOI5I/O Data In Register bit 5RIOI4I/O Data In Register bit 4RIOI3I/O Data In Register bit 3RIOI2I/O Data In Register bit 2RIOI1I/O Data In Register bit 1RIOI0I/O Data In Register bit 0R[SREG:SPH:SPL:AVR_CONFIG:B_DET:BL_CONFIG]
[SPH:SPL]
io_cpu.bmpSREGStatus Register$3F$5Fio_sreg.bmpYIGlobal Interrupt EnableThe global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable bit is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts.RW0TBit Copy StorageThe bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction.RW0HHalf Carry FlagThe half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed information.RW0SSign BitThe S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruc-tion Set Description for detailed information.RW0VTwo's Complement Overflow FlagThe two’s complement overflow flag V supports two’s complement arithmetics. See the Instruction Set Description for detailed information.RW0NNegative FlagThe negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.RW0ZZero FlagThe zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.RW0CCarry FlagThe carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software.RW0SPHStack Pointer HighThe general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the AT90S4414/8515 supports up to 64 kB external SRAM, all 16-bits are used. The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or return from interrupt R$3E$5Eio_sph.bmpNSP10Stack pointer bit 10RW0SP9Stack pointer bit 9RW0SP8Stack pointer bit 8RW0SPLStack Pointer LowThe general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the AT90S4414/8515 supports up to 64 kB external SRAM, all 16-bits are used. The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or return from interrupt $3D$5Dio_sph.bmpNSP7Stack pointer bit 7RW0SP6Stack pointer bit 6RW0SP5Stack pointer bit 5RW0SP4Stack pointer bit 4RW0SP3Stack pointer bit 3RW0SP2Stack pointer bit 2RW0SP1Stack pointer bit 1RW0SP0Stack pointer bit 0RW0AVR_CONFIGAVR Configuration Register$33$53io_flag.bmpNACS1AVR System Clock Select bit 1RW0ACS0AVR System Clock Select bit 0RW0TMTest ModeRW0BDBattery DeadRW0BLIBattery Low IndicatorRW0SLEEPSleep BitRW0BBMButton Boot ModeRW0B_DETButton Detect Register$34$54io_sph.bmpNBD5Button Detect bit 5RW0BD4Button Detect bit 4RW0BD3Button Detect bit 3RW0BD2Button Detect bit 2RW0BD1Button Detect bit 1RW0BD0Button Detect bit 0RW0BL_CONFIGBattery Low Configuration Register$35$55io_sph.bmpNBLBattery LowRW0BLVBattery Low ValidRW0BL5Battery Low Detection Level bit 5RW0BL4Battery Low Detection Level bit 4RW0BL3Battery Low Detection Level bit 3RW0BL2Battery Low Detection Level bit 2RW0BL1Battery Low Detection Level bit 1RW0BL0Battery Low Detection Level bit 0RW0[SIMULATOR:STK500:STK500_2:AVRISPmkII]AVRSimCoreV2.SimCoreV2AVRSimMemory8bit.SimMemory8bitAVRSimInterrupt.SimInterrupt00x000x000x000x000xD00000x000x000x0002001002532030x53114510x0232100x400x000x200x000x000x02460xC00x000xA00x000xFF2562564444