[ADMIN:CORE:PROGVOLT:POWER:LOCKBIT:MEMORY:INTERRUPT_VECTOR:PACKAGE:PROGRAMMING:FUSE:IO_MODULE:ICE_SETTINGS]AT90PWM38MHz153RELEASED$1E$93$81V2EAVRSimCoreV2.SimCoreV2[][][]32$00$1B$1A$1D$1C$1F$1E2.76.04.55.54MHz25CTBD mATBD mATBD uA[LB1 = 1 : LB2 = 1] No memory lock features enabled. [LB1 = 0 : LB2 = 1] Further programming of Flash and EEPROM is enabled. [LB1 = 0 : LB2 = 0] Same as previous, but verify is also disabled6110x030x03Mode 1: No memory lock features enabled0x030x02Mode 2: Further programming disabled0x030x00Mode 3: Further programming and verification disabled0x0C0x0CApplication Protection Mode 1: No lock on SPM and LPM in Application Section0x0C0x08Application Protection Mode 2: SPM prohibited in Application Section0x0C0x00Application Protection Mode 3: LPM and SPM prohibited in Application Section0x0C0x04Application Protection Mode 4: LPM prohibited in Application Section0x300x30Boot Loader Protection Mode 1: No lock on SPM and LPM in Boot Loader Section0x300x20Boot Loader Protection Mode 2: SPM prohibited in Boot Loader Section0x300x00Boot Loader Protection Mode 3: LPM and SPM prohibited in Boot Loader Section0x300x10Boot Loader Protection Mode 4: LPM prohibited in Boot Loader SectionLB1Lock bitLB2Lock bitBLB01Boot Lock bitBLB02Boot Lock bitBLB11Boot lock bitBLB12Boot lock bitAVRSimMemory8bit.SimMemory8bit8192512512$01000NA$0000$003F$0060$00FF$0020$00FFNA0xFF0x010x020x040x08NA0xFE0x010x020x040x080x100x200x400x80NA0xFD0x010x020x040x080x100x200x400x80NA0xFC0x010x020x040x080x100x200x400x80NA0xFB0x010x020x040x080x100x200x400x80NA0xFA0x010x020x040x080x100x200x400x80NA0xF90x010x020x040x080x100x200x400x80NA0xF80x010x020x040x080x100x200x400x80NA0xF70x010x020x040x08NA0xF60x010x020x040x080x100x200x400x80NA0xF50x010x020x040x08NA0xF40x010x020x040x080x100x200x400x80NA0xF30x010x020x040x08NA0xF20x010x020x040x080x100x200x400x80NA0xF10x010x020x040x080x100x200x400x80NA0xF00x010x020x040x080x100x200x400x80NA0xEF0x010x020x040x08NA0xEE0x010x020x040x080x100x200x400x80NA0xED0x010x020x040x080x100x200x400x80NA0xEC0x010x020x040x080x100x200x400x80NA0xEB0x010x020x040x080x100x200x400x80NA0xEA0x020x040x080x100x200x400x80NA0xE90x010x020x040x080x100x200x400x80NA0xE80x010x020x040x080x100x200x400x80NA0xE70x010x020x040x08NA0xE60x010x020x040x080x100x200x400x80NA0xE50x010x020x040x08NA0xE40x010x020x040x080x100x200x400x80NA0xE30x010x020x040x08NA0xE20x010x020x040x080x100x200x400x80NA0xE00x010x040x100x20NA0xDF0x010x020x040x08NA0xDE0x010x020x040x080x100x200x400x80NA0xDD0x010x020x040x080x100x200x400x80NA0xDC0x010x020x040x080x100x200x400x80NA0xDB0x010x020x040x080x100x200x400x80NA0xDA0x020x040x080x100x200x400x80NA0xD90x010x020x040x080x100x200x400x80NA0xD80x010x020x040x080x100x200x400x80NA0xD70x010x020x040x08NA0xD60x010x020x040x080x100x200x400x80NA0xD50x010x020x040x08NA0xD40x010x020x040x080x100x200x400x80NA0xD30x010x020x040x08NA0xD20x010x020x040x080x100x200x400x80NA0xD00x010x040x100x20NA0xCE0x010x020x040x080x100x200x400x80NA0xCD0x010x020x040x080x100x200x400x80NA0xCC0x010x020x040x080x100x200x400x80NA0xCA0x010x020x040x08NA0xC90x010x020x080x10NA0xC80x010x020x040x080x100x200x400x80NA0xC60x010x020x040x080x100x200x400x80NA0xC50x010x020x040x08NA0xC40x010x020x040x080x100x200x400x80NA0xC20x010x020x040x080x100x200x40NA0xC10x010x020x040x080x100x200x400x80NA0xC00x010x020x040x080x100x200x400x80NA$AF0x010x020x040x100x200x400x80NA$AE0x010x020x040x080x100x200x400x80NA$AD0x010x020x040x100x200x400x80NA$AC0x010x020x040x080x100x200x400x80NA$AB0x010x020x040x080x100x200x400x80NA$AA0x010x020x040x100x200x400x80NA$A50x010x080x100x20NA$A40x010x020x040x080x100x20NA$A30x010x080x100x20NA$A20x010x020x040x080x100x20NA$A10x010x080x100x20NA$A00x010x020x040x080x100x20NA$8B0x010x020x040x080x100x200x400x80NA$8A0x010x020x040x080x100x200x400x80NA$890x010x020x040x080x100x200x400x80NA$880x010x020x040x080x100x200x400x80NA$870x010x020x040x080x100x200x400x80NA$860x010x020x040x080x100x200x400x80NA$850x010x020x040x080x100x200x400x80NA$840x010x020x040x080x100x200x400x80NA$820x400x80NA$810x010x020x040x080x100x400x80NA$800x010x020x100x200x400x80NA$7F0x010x020x040x080x100x20NA$7E0x010x020x040x080x100x200x400x80NA$7C0x010x020x040x080x200x400x80NA$7B0x010x020x040x080x100x80NA$7A0x010x020x040x080x100x200x400x80NA$790x010x020x040x080x100x200x400x80NA$780x010x020x040x080x100x200x400x80NA$77NA$76NA$6F0x010x020x040x20NA$6E0x010x020x04NA$690x010x020x040x080x100x200x400x80NA$660x010x020x040x080x100x200x40NA$64NA$610x010x020x040x080x80NA$600x010x020x040x080x100x200x400x80$3F$5F0x010x020x040x080x100x200x400x80$3E$5E0x010x020x040x080x100x200x400x80$3D$5D0x010x020x040x080x100x200x400x80$37$570x010x020x040x080x100x400x80$35$550x010x020x100x80$34$540x010x020x040x08$33$530x010x020x040x08$30$50$2E$4E0x010x020x040x080x100x200x400x80$2D$4D0x010x400x80$2C$4C0x010x020x040x080x100x200x400x80$29$490x010x020x04$28$480x010x020x040x080x100x200x400x80$27$470x010x020x040x080x100x200x400x80$26$460x010x020x040x080x100x200x400x80$25$450x010x020x040x080x400x80$24$440x010x020x100x200x400x80$23$430x010x400x800x01$22$420x010x020x040x08$21$410x010x020x040x080x100x200x400x80$20$400x010x020x040x080x100x200x400x80$1F$3F0x010x020x040x080x100x20$1E$3E0x010x020x040x080x100x200x400x80$1D$3D0x010x020x040x08$1C$3C0x010x020x040x08$1B$3B0x010x020x040x080x100x200x400x80$1A$3A0x010x020x040x080x100x200x400x80$19$390x010x020x040x080x100x200x400x80$16$360x010x020x040x20$15$350x010x020x04$0E$2E0x010x020x04$0D$2D0x010x020x04$0C$2C0x010x020x04$0B$2B0x010x020x040x080x100x200x400x80$0A$2A0x010x020x040x080x100x200x400x80$09$290x010x020x040x080x100x200x400x80$08$280x010x020x040x080x100x200x400x80$07$270x010x020x040x080x100x200x400x80$06$260x010x020x040x080x100x200x400x80$05$250x010x020x040x080x100x200x400x80$04$240x010x020x040x080x100x200x400x80$03$230x010x020x040x080x100x200x400x80$C00$FFF$0$BFF321284$0$F80$F802568$0$F00$F0051216$0$E00$E00102432$0$C00$C0032AVRSimInterrupt.SimInterrupt$0000External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset and JTAG AVR Reset$0001PSC2 Capture Event$0002PSC2 End Cycle$0003PSC1 Capture Event$0004PSC1 End Cycle$0005PSC0 Capture Event$0006PSC0 End Cycle$0007Analog Comparator 0$0008Analog Comparator 1$0009Analog Comparator 2$000AExternal Interrupt Request 0$000BTimer/Counter1 Capture Event$000CTimer/Counter1 Compare Match A$000DTimer/Counter Compare Match B$000E$000FTimer/Counter1 Overflow$0010Timer/Counter0 Compare Match A$0011Timer/Counter0 Overflow$0012ADC Conversion Complete$0013External Interrupt Request 1$0014SPI Serial Transfer Complete$0015USART, Rx Complete$0016USART Data Register Empty$0017USART, Tx Complete$0018External Interrupt Request 2$0019Watchdog Timeout Interrupt$001AEEPROM Ready$001BTimer Counter 0 Compare Match B$001CExternal Interrupt Request 3$001D$001E$001FStore Program Memory Read[QFN:SOIC]32[PD2:PSCIN2:OC1A:MISO_A][PD3:TXD:DALI:OC0A:SS:MOSI_A][PC1:PSCIN1:OC1B][VCC][GND][PC2:T0:PSCOUT22][PC3:T1:PSCOUT23][PB0:MISO:PSCOUT20][PB1:MOSI:PSCOUT21][PE1:OC0B:XTAL1][PE2:ADC0:XTAL2][PD4:ADC1:RXD:DALI:ICP1:SCK_A][PD5:ADC2:ACOMP2][PD6:ADC3:ACMPM:INT0][PD7:ACMP0][PB2:ADC5:INT1][PC4:ADC8:AMP1-][PC5:ADC9:AMP1+][AVCC][AGND][AREF][PC6:ADC10:ACMP1][PB3:AMP0-][PB4:AMP0+][PC7:D2A][PB5:ADC6:INT2][PB6:ADC7:PSCOUT11:ICP1B][PB7:ADC4:PSCOUT01:SCK)[PD0:PSCOUT00:XCK:SSA][PC0:INT3:PSCOUT10][PE0:RESET:OCD][PD1:PSCIN0:CLK0]32[PD0:PSCOUT00:XCK:SSA][PC0:INT3:PSCOUT10][PE0:RESET:OCD][PD1:PSCIN0:CLK0][PD2:PSCIN2:OC1A:MISO_A][PD3:TXD:DALI:OC0A:SS:MOSI_A][PC1:PSCIN1:OC1B][VCC][GND][PC2:T0:PSCOUT22][PC3:T1:PSCOUT23][PB0:MISO:PSCOUT20][PB1:MOSI:PSCOUT21][PE1:OC0B:XTAL1][PE2:ADC0:XTAL2][PD4:ADC1:RXD:DALI:ICP1:SCK_A][PD5:ADC2:ACOMP2][PD6:ADC3:ACMPM:INT0][PD7:ACMP0][PB2:ADC5:INT1][PC4:ADC8:AMP1-][PC5:ADC9:AMP1+][AVCC][AGND][AREF][PC6:ADC10:ACMP1][PB3:AMP0-][PB4:AMP0+][PC7:D2A][PB5:ADC6:INT2][PB6:ADC7:PSCOUT11:ICP1B][PB7:ADC4:PSCOUT01:SCK)0xff,0xdf,0xff0xff,0xdf,0xff1,0x20,0x20,WARNING! These fuse settings will disable the ISP interface!1,0x80,0x00,WARNING! Disabling external reset will make the ISP interface inaccessible!1,0x40,0x00,WARNING! Enabling DEBUGWIRE will make the ISP interface inaccessible!2,0x90,0x00,WARNING! These fuse settings will make the Parallel interface inaccessible!1,0x20,0x20,WARNING! These fuse settings will disable the ISP interface!1,0x80,0x00,WARNING! Disabling external reset will make the ISP interface inaccessible!1,0x40,0x00,WARNING! Enabling DEBUGWIRE will make the ISP interface inaccessible!2,0x90,0x00,WARNING! These fuse settings will make the Parallel interface inaccessible!0x00,8.0 MHz644[LOW:HIGH:EXTENDED]8CLKDIV8Divide clock by 80CKOUTOscillator output option1SUT1Select start-up time0SUT0Select start-up time0CKSEL3Select Clock Source0CKSEL2Select Clock Source0CKSEL1Select Clock Source0CKSEL0Select Clock Source1440x800x00Divide clock by 8 internally; [CKDIV8=0]0x400x00Clock output on PORTD1; [CKOUT=0]0x3F0x00Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms; [CKSEL=0000 SUT=00]0x3F0x10Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms; [CKSEL=0000 SUT=01]0x3F0x20Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms; [CKSEL=0000 SUT=10]0x3F0x02Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms; [CKSEL=0010 SUT=00]0x3F0x12Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms; [CKSEL=0010 SUT=01]0x3F0x22Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms; [CKSEL=0010 SUT=10]; default value0x3F0x08Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms; [CKSEL=1000 SUT=00] 0x3F0x18Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms; [CKSEL=1000 SUT=01] 0x3F0x28Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms; [CKSEL=1000 SUT=10] 0x3F0x38Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms; [CKSEL=1000 SUT=11] 0x3F0x09Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms; [CKSEL=1001 SUT=00] 0x3F0x19Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms; [CKSEL=1001 SUT=01] 0x3F0x29Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms; [CKSEL=1001 SUT=10] 0x3F0x39Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms; [CKSEL=1001 SUT=11] 0x3F0x0AExt. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms; [CKSEL=1010 SUT=00] 0x3F0x1AExt. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms; [CKSEL=1010 SUT=01] 0x3F0x2AExt. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms; [CKSEL=1010 SUT=10] 0x3F0x3AExt. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms; [CKSEL=1010 SUT=11] 0x3F0x0BExt. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms; [CKSEL=1011 SUT=00] 0x3F0x1BExt. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms; [CKSEL=1011 SUT=01] 0x3F0x2BExt. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms; [CKSEL=1011 SUT=10] 0x3F0x3BExt. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms; [CKSEL=1011 SUT=11] 0x3F0x0CExt. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms; [CKSEL=1100 SUT=00] 0x3F0x1CExt. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms; [CKSEL=1100 SUT=01] 0x3F0x2CExt. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms; [CKSEL=1100 SUT=10] 0x3F0x3CExt. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms; [CKSEL=1100 SUT=11] 0x3F0x0DExt. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms; [CKSEL=1101 SUT=00] 0x3F0x1DExt. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms; [CKSEL=1101 SUT=01] 0x3F0x2DExt. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms; [CKSEL=1101 SUT=10] 0x3F0x3DExt. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms; [CKSEL=1101 SUT=11] 0x3F0x0EExt. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms; [CKSEL=1110 SUT=00] 0x3F0x1EExt. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms; [CKSEL=1110 SUT=01] 0x3F0x2EExt. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms; [CKSEL=1110 SUT=10] 0x3F0x3EExt. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms; [CKSEL=1110 SUT=11] 0x3F0x0FExt. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms; [CKSEL=1111 SUT=00] 0x3F0x1FExt. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms; [CKSEL=1111 SUT=01] 0x3F0x2FExt. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms; [CKSEL=1111 SUT=10] 0x3F0x3FExt. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms; [CKSEL=1111 SUT=11] 0x3F0x03PLL clock; Frequency 16 MHz; Start-up time PWRDWN/RESET: 1K CK/14 CK + 0 ms; [CKSEL=0011 SUT=00]0x3F0x13PLL clock; Frequency 16 MHz; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4.1 ms; [CKSEL=0011 SUT=01]0x3F0x23PLL clock; Frequency 16 MHz; Start-up time PWRDWN/RESET: 1K CK/14 CK + 65 ms; [CKSEL=0011 SUT=10]0x3F0x33PLL clock; Frequency 16 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms; [CKSEL=0011 SUT=11]8RSTDISBLExternal Reset Disable1DWENdwbugWIRE Enable1SPIENEnable Serial programming and Data Downloading0WDTONWatchdog timer always on1EESAVEEEPROM memory is preserved through chip erase1BOOTSZ1Select Boot Size0BOOTSZ0Select Boot Size0BOOTRSTSelect Reset Vector1130x800x00Reset Disabled (Enable PC6 as i/o pin); [RSTDISBL=0]0x400x00Debug Wire enable; [DWEN=0]0x200x00Serial program downloading (SPI) enabled; [SPIEN=0]0x100x00Watch-dog Timer always on; [WDTON=0]0x080x00Preserve EEPROM memory through the Chip Erase cycle; [EESAVE=0]0x070x07Brown-out detection disabled; [BODLEVEL=111]0x070x06Brown-out detection level at VCC=4.5 V; [BODLEVEL=110]0x070x05Brown-out detection level at VCC=2.7 V; [BODLEVEL=101]0x070x04Brown-out detection level at VCC=4.3 V; [BODLEVEL=100]0x070x03Brown-out detection level at VCC=4.4 V; [BODLEVEL=011]0x070x02Brown-out detection level at VCC=4.2 V; [BODLEVEL=010]0x070x01Brown-out detection level at VCC=2.8 V; [BODLEVEL=001]0x070x00Brown-out detection level at VCC=2.6 V; [BODLEVEL=000] 4BODLEVEL2Brown out detector trigger level1BODLEVEL1Brown-out Detector trigger level1BODLEVEL0Brown-out Detector trigger level1TA0SEL(Reserved to factory tests)190x100x00PSCOUT Reset Value; [PSCRV=1]0x800x00PSC2 Reset Behavior; [PSC2RB=0]0x400x00PSC1 Reset Behavior; [PSC1RB=0]0x200x00PSC0 Reset Behavior; [PSC0RB=0]0x060x06Boot Flash section size=128 words Boot start address=$0F80; [BOOTSZ=11]0x060x04Boot Flash section size=256 words Boot start address=$0F00; [BOOTSZ=10]0x060x02Boot Flash section size=512 words Boot start address=$0E00; [BOOTSZ=01]0x060x00Boot Flash section size=1024 words Boot start address=$0C00; [BOOTSZ=00] ; default value0x010x00Boot Reset vector Enabled (default address=$0000); [BOOTRST=0][PORTB:PORTC:PORTD:BOOT_LOAD:PSC0:PSC1:PSC2:EUSART:ANALOG_COMPARATOR:DA_CONVERTER:CPU:PORTE:TIMER_COUNTER_0:TIMER_COUNTER_1:AD_CONVERTER:USART:SPI:WATCHDOG:EXTERNAL_INTERRUPT:EEPROM][PORTB:DDRB:PINB]io_port.bmpAVRSimIOPort.SimIOPortPORTBPort B Data Register$05$25io_port.bmpNPORTB7Port B Data Register bit 7RW0PORTB6Port B Data Register bit 6RW0PORTB5Port B Data Register bit 5RW0PORTB4Port B Data Register bit 4RW0PORTB3Port B Data Register bit 3RW0PORTB2Port B Data Register bit 2RW0PORTB1Port B Data Register bit 1RW0PORTB0Port B Data Register bit 0RW0DDRBPort B Data Direction Register$04$24io_flag.bmpNDDB7Port B Data Direction Register bit 7RW0DDB6Port B Data Direction Register bit 6RW0DDB5Port B Data Direction Register bit 5RW0DDB4Port B Data Direction Register bit 4RW0DDB3Port B Data Direction Register bit 3RW0DDB2Port B Data Direction Register bit 2RW0DDB1Port B Data Direction Register bit 1RW0DDB0Port B Data Direction Register bit 0RW0PINBPort B Input PinsThe Port B Input Pins address - PINB - is not a register, and this address enables access to the physical value on each Port B pin. When reading PORTB, the Port B Data Latch is read, and when reading PINB, the logical values present on the pins are read.$03$23io_port.bmpNPINB7Port B Input Pins bit 7R0PINB6Port B Input Pins bit 6R0PINB5Port B Input Pins bit 5R0PINB4Port B Input Pins bit 4R0PINB3Port B Input Pins bit 3R0PINB2Port B Input Pins bit 2R0PINB1Port B Input Pins bit 1R0PINB0Port B Input Pins bit 0R0[PORTC:DDRC:PINC]io_port.bmpAVRSimIOPort.SimIOPortPORTCPort C Data Register$08$28io_port.bmpNPORTC7Port C Data Register bit 7RW0PORTC6Port C Data Register bit 6RW0PORTC5Port C Data Register bit 5RW0PORTC4Port C Data Register bit 4RW0PORTC3Port C Data Register bit 3RW0PORTC2Port C Data Register bit 2RW0PORTC1Port C Data Register bit 1RW0PORTC0Port C Data Register bit 0RW0DDRCPort C Data Direction Register$07$27io_flag.bmpNDDC7Port C Data Direction Register bit 7RW0DDC6Port C Data Direction Register bit 6RW0DDC5Port C Data Direction Register bit 5RW0DDC4Port C Data Direction Register bit 4RW0DDC3Port C Data Direction Register bit 3RW0DDC2Port C Data Direction Register bit 2RW0DDC1Port C Data Direction Register bit 1RW0DDC0Port C Data Direction Register bit 0RW0PINCPort C Input PinsThe Port C Input Pins address - PINC - is not a register, and this address enables access to the physical value on each Port C pin. When reading PORTC, the Port C Data Latch is read, and when reading PINC, the logical values present on the pins are read.$06$26io_port.bmpNPINC7Port C Input Pins bit 7R0PINC6Port C Input Pins bit 6R0PINC5Port C Input Pins bit 5R0PINC4Port C Input Pins bit 4R0PINC3Port C Input Pins bit 3R0PINC2Port C Input Pins bit 2R0PINC1Port C Input Pins bit 1R0PINC0Port C Input Pins bit 0R0[PORTD:DDRD:PIND]io_port.bmpAVRSimIOPort.SimIOPortPORTDPort D Data Register$0B$2Bio_port.bmpNPORTD7Port D Data Register bit 7RW0PORTD6Port D Data Register bit 6RW0PORTD5Port D Data Register bit 5RW0PORTD4Port D Data Register bit 4RW0PORTD3Port D Data Register bit 3RW0PORTD2Port D Data Register bit 2RW0PORTD1Port D Data Register bit 1RW0PORTD0Port D Data Register bit 0RW0DDRDPort D Data Direction Register$0A$2Aio_flag.bmpNDDD7Port D Data Direction Register bit 7RW0DDD6Port D Data Direction Register bit 6RW0DDD5Port D Data Direction Register bit 5RW0DDD4Port D Data Direction Register bit 4RW0DDD3Port D Data Direction Register bit 3RW0DDD2Port D Data Direction Register bit 2RW0DDD1Port D Data Direction Register bit 1RW0DDD0Port D Data Direction Register bit 0RW0PINDPort D Input PinsThe Port D Input Pins address - PIND - is not a register, and this address enables access to the physical value on each Port D pin. When reading PORTD, the Port D Data Latch is read, and when reading PIND, the logical values present on the pins are read.$09$29io_port.bmpNPIND7Port D Input Pins bit 7R0PIND6Port D Input Pins bit 6R0PIND5Port D Input Pins bit 5R0PIND4Port D Input Pins bit 4R0PIND3Port D Input Pins bit 3R0PIND2Port D Input Pins bit 2R0PIND1Port D Input Pins bit 1R0PIND0Port D Input Pins bit 0R0[SPMCSR]io_cpu.bmpAVRSimIOSPM.SimIOSPMThe Boot Loader Support provides a real Read While Write self-programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program. The Boot Loader program can use any available data interface and associated proto-col to read code and write (program) that code into the Flash memory, or read the code from the program memory. The program code within the Boot Loader section has the capability to write into the entire Flash, including the Boot Loader Memory. The Boot Loader can thus even modify itself, and it can also erase itself from the code if the feature is not needed anymore. The size of the Boot Loader Memory is configurable with fuses and the Boot Loader has two separate sets of Boot Lock Bits which can be set independently. This gives the user a unique flexibility to select different levels of protection. Boot Loader Features: Read While Write self-programming. Flexibl Boot Memory size. High security (separate Boot Lock bits for a flexible protection). Separate fuse to select reset vector Optimized page (1) size. Code efficient algorithm Efficient read-modify-write supporSPMCSRSPMCRStore Program Memory Control RegisterThe Store Program Memory Control Register contains the control bits needed to control the Boot Loader operations.$37$57io_flag.bmpYSPMIESPM Interrupt EnableWhen the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN bit in the SPMCR register is cleared.RW0RWWSBASBRead While Write Section BusyWhen a self-programming (page erase or page write) operation to the RWW section is initiated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a self-programming operation is completed. Alternatively the RWWSB bit will auto-matically be cleared if a page load operation is initiated.R0RWWSREASRERead While Write section read enableWhen programming (page erase or page write) to the RWW section, the RWW section is blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW section, the user software must wait until the programming is completed (SPMEN will be cleared). Then, if the RWWSRE bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles re-enables the RWW section. The RWW section cannot be re-enabled while Flash is busy with a page erase or a page write (SPMEN is set). If the RWWSRE bit is written while the Flash is being loaded, the Flash load operation will abort and the data loaded will be loRW0BLBSETBoot Lock Bit SetIf this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles sets Boot Lock bits, according to the data in R0. The data in R1 and the address in the Z pointer are ignored. The BLBSET bit will automatically be cleared upon completion of the lock bit set, or if no SPM instruction is executed within four clock cycles. An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCR register, will read either the Lock-bits or the Fuse bits (depending on Z0 in the Z pointer) into the destination register. See “Reading the Fuse and Lock Bits from Software” on page 235 for detailsRW0PGWRTPage WriteIf this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPM instruction is exe-cuted within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.RW0PGERSPage EraseIf this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page erase. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a page erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.RW0SPMENStore Program Memory EnableThis bit enables the SPM instruction for the next four clock cycles. If written to one together with either RWWSRE, BLB-SET, PGWRT or PGERS, the following SPM instruction will have a special meaning, see description above. If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z pointer. The LSB of the Z pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During page erase and page write, the SPMEN bit remain high until the operation is completed. Writing any other combination than “10001”, "01001", "00101", "00011" or "00001" in the lower five bits will have no effecRW0[PICR0H:PICR0L:PFRC0B:PFRC0A:PCTL0:PCNF0:OCR0RBH:OCR0RBL:OCR0SBH:OCR0SBL:OCR0RAH:OCR0RAL:OCR0SAH:OCR0SAL:PSOC0:PIM0:PIFR0]io_com.bmpPower Stage ControllerPICR0HPSC 0 Input Capture Register HighNA0xDFregister.bmpNPICR0_11R0PICR0_10R0PICR0_9R0PICR0_8R0PICR0LPSC 0 Input Capture Register LowNA0xDEregister.bmpNPICR0_7R0PICR0_6R0PICR0_5R0PICR0_4R0PICR0_3R0PICR0_2R0PICR0_1R0PICR0_0R0PFRC0BPSC 0 Input B ControlNA0xDDregister.bmpYPCAE0BPSC 0 Capture Enable Input Part BRW0PISEL0BPSC 0 Input Select for Part BRW0PELEV0BPSC 0 Edge Level Selector on Input Part BRW0PFLTE0BPSC 0 Filter Enable on Input Part BRW0PRFM0B3PSC 0 Retrigger and Fault Mode for Part BRW0PRFM0B2PSC 0 Retrigger and Fault Mode for Part BRW0PRFM0B1PSC 0 Retrigger and Fault Mode for Part BRW0PRFM0B0PSC 0 Retrigger and Fault Mode for Part BRW0PFRC0APSC 0 Input A ControlNA0xDCregister.bmpYPCAE0APSC 0 Capture Enable Input Part ARW0PISEL0APSC 0 Input Select for Part ARW0PELEV0APSC 0 Edge Level Selector on Input Part ARW0PFLTE0APSC 0 Filter Enable on Input Part ARW0PRFM0A3PSC 0 Retrigger and Fault Mode for Part ARW0PRFM0A2PSC 0 Retrigger and Fault Mode for Part ARW0PRFM0A1PSC 0 Retrigger and Fault Mode for Part ARW0PRFM0A0PSC 0 Retrigger and Fault Mode for Part ARW0PCTL0PSC 0 Control RegisterNA0xDBregister.bmpYPPRE01PSC 0 Prescaler Select 1RW0PPRE00PSC 0 Prescaler Select 0RW0PBFM0PSC 0 Balance Flank Width ModulationRW0PAOC0BPSC 0 Asynchronous Output Control BRW0PAOC0APSC 0 Asynchronous Output Control ARW0PARUN0PSC0 Auto RunRW0PCCYC0PSC0 Complete CycleRW0PRUN0PSC 0 RunRW0PCNF0PSC 0 Configuration RegisterNA0xDAregister.bmpYPFIFTY0PSC 0 FiftyRW0PALOCK0PSC 0 AutolockRW0PLOCK0PSC 0 LockRW0PMODE01PSC 0 ModeRW0PMODE00PSC 0 ModeRW0POP0PSC 0 Output PolarityRW0PCLKSEL0PSC 0 Input Clock SelectRW0OCR0RBHOutput Compare RB Register HighNA0xD9register.bmpNOCR0RB_05RW0OCR0RB_04RW0OCR0RB_03RW0OCR0RB_02RW0OCR0RB_01RW0OCR0RB_00RW0OCR0RB_9RW0OCR0RB_8RW0OCR0RBLOutput Compare RB Register LowNA0xD8register.bmpNOCR0RB_7RW0OCR0RB_6RW0OCR0RB_5RW0OCR0RB_4RW0OCR0RB_3RW0OCR0RB_2RW0OCR0RB_1RW0OCR0RB_0RW0OCR0SBHOutput Compare SB Register HighNA0xD7register.bmpNOCR0SB_01RW0OCR0SB_00RW0OCR0SB_9RW0OCR0SB_8RW0OCR0SBLOutput Compare SB Register LowNA0xD6register.bmpNOCR0SB_7RW0OCR0SB_6RW0OCR0SB_5RW0OCR0SB_4RW0OCR0SB_3RW0OCR0SB_2RW0OCR0SB_1RW0OCR0SB_0RW0OCR0RAHOutput Compare RA Register HighNA0xD5register.bmpNOCR0RA_01RW0OCR0RA_00RW0OCR0RA_9RW0OCR0RA_8RW0OCR0RALOutput Compare RA Register LowNA0xD4register.bmpNOCR0RA_7RW0OCR0RA_6RW0OCR0RA_5RW0OCR0RA_4RW0OCR0RA_3RW0OCR0RA_2RW0OCR0RA_1RW0OCR0RA_0RW0OCR0SAHOutput Compare SA Register HighNA0xD3register.bmpNOCR0SA_01RW0OCR0SA_00RW0OCR0SA_9RW0OCR0SA_8RW0OCR0SALOutput Compare SA Register LowNA0xD2register.bmpNOCR0SA_7RW0OCR0SA_6RW0OCR0SA_5RW0OCR0SA_4RW0OCR0SA_3RW0OCR0SA_2RW0OCR0SA_1RW0OCR0SA_0RW0PSOC0PSC0 Synchro and Output ConfigurationNA0xD0register.bmpYPSYNC01Synchronization Out for ADC SelectionRW0PSYNC00Synchronization Out for ADC SelectionRW0POEN0BPSCOUT01 Output EnableRW0POEN0APSCOUT00 Output EnableRW0PIM0PSC0 Interrupt Mask RegisterNA$A1register.bmpYPSEIE0PSC 0 Synchro Error Interrupt EnableRW0PEVE0BExternal Event B Interrupt EnableRW0PEVE0AExternal Event A Interrupt EnableRW0PEOPE0End of Cycle Interrupt EnableRW0PIFR0PSC0 Interrupt Flag RegisterNA$A0register.bmpYPSEI0PSC 0 Synchro Error InterruptRW0PEV0BExternal Event B InterruptRW0PEV0AExternal Event A InterruptRW0PRN01Ramp NumberR0PRN00Ramp NumberR0PEOP0End of PSC0 InterruptRW0[PICR1H:PICR1L:PFRC1B:PFRC1A:PCTL1:PCNF1:OCR1RBH:OCR1RBL:OCR1SBH:OCR1SBL:OCR1RAH:OCR1RAL:OCR1SAH:OCR1SAL:PSOC1:PIM1:PIFR1]io_com.bmpPower Stage ControllerPICR1HPSC 1 Input Capture Register HighNA0xEFregister.bmpNPICR1_11R0PICR1_10R0PICR1_9R0PICR1_8R0PICR1LPSC 1 Input Capture Register LowNA0xEEregister.bmpNPICR1_7R0PICR1_6R0PICR1_5R0PICR1_4R0PICR1_3R0PICR1_2R0PICR1_1R0PICR1_0R0PFRC1BPSC 1 Input B ControlNA0xEDregister.bmpYPCAE1BPSC 1 Capture Enable Input Part BRW0PISEL1BPSC 1 Input Select for Part BRW0PELEV1BPSC 1 Edge Level Selector on Input Part BRW0PFLTE1BPSC 1 Filter Enable on Input Part BRW0PRFM1B3PSC 1 Retrigger and Fault Mode for Part BRW0PRFM1B2PSC 1 Retrigger and Fault Mode for Part BRW0PRFM1B1PSC 1 Retrigger and Fault Mode for Part BRW0PRFM1B0PSC 1 Retrigger and Fault Mode for Part BRW0PFRC1APSC 1 Input B ControlNA0xECregister.bmpYPCAE1APSC 1 Capture Enable Input Part ARW0PISEL1APSC 1 Input Select for Part ARW0PELEV1APSC 1 Edge Level Selector on Input Part ARW0PFLTE1APSC 1 Filter Enable on Input Part ARW0PRFM1A3PSC 1 Retrigger and Fault Mode for Part ARW0PRFM1A2PSC 1 Retrigger and Fault Mode for Part ARW0PRFM1A1PSC 1 Retrigger and Fault Mode for Part ARW0PRFM1A0PSC 1 Retrigger and Fault Mode for Part ARW0PCTL1PSC 1 Control RegisterNA0xEBregister.bmpYPPRE11PSC 1 Prescaler Select 1RW0PPRE10PSC 1 Prescaler Select 0RW0PBFM1Balance Flank Width ModulationRW0PAOC1BPSC 1 Asynchronous Output Control BRW0PAOC1APSC 1 Asynchronous Output Control ARW0PARUN1PSC1 Auto RunRW0PCCYC1PSC1 Complete CycleRW0PRUN1PSC 1 RunRW0PCNF1PSC 1 Configuration RegisterNA0xEAregister.bmpYPFIFTY1PSC 1 FiftyRW0PALOCK1PSC 1 AutolockRW0PLOCK1PSC 1 LockRW0PMODE11PSC 1 ModeRW0PMODE10PSC 1 ModeRW0POP1PSC 1 Output PolarityRW0PCLKSEL1PSC 1 Input Clock SelectRW0OCR1RBHOutput Compare RB Register HighNA0xE9register.bmpNOCR1RB_15RW0OCR1RB_14RW0OCR1RB_13RW0OCR1RB_12RW0OCR1RB_11RW0OCR1RB_10RW0OCR1RB_9RW0OCR1RB_8RW0OCR1RBLOutput Compare RB Register LowNA0xE8register.bmpNOCR1RB_7RW0OCR1RB_6RW0OCR1RB_5RW0OCR1RB_4RW0OCR1RB_3RW0OCR1RB_2RW0OCR1RB_1RW0OCR1RB_0RW0OCR1SBHOutput Compare SB Register HighNA0xE7register.bmpNOCR1SB_11RW0OCR1SB_10RW0OCR1SB_9RW0OCR1SB_8RW0OCR1SBLOutput Compare SB Register LowNA0xE6register.bmpNOCR1SB_7RW0OCR1SB_6RW0OCR1SB_5RW0OCR1SB_4RW0OCR1SB_3RW0OCR1SB_2RW0OCR1SB_1RW0OCR1SB_0RW0OCR1RAHOutput Compare RA Register HighNA0xE5register.bmpNOCR1RA_11RW0OCR1RA_10RW0OCR1RA_9RW0OCR1RA_8RW0OCR1RALOutput Compare RA Register LowNA0xE4register.bmpNOCR1RA_7RW0OCR1RA_6RW0OCR1RA_5RW0OCR1RA_4RW0OCR1RA_3RW0OCR1RA_2RW0OCR1RA_1RW0OCR1RA_0RW0OCR1SAHOutput Compare SA Register HighNA0xE3register.bmpNOCR1SA_11RW0OCR1SA_10RW0OCR1SA_9RW0OCR1SA_8RW0OCR1SALOutput Compare SA Register LowNA0xE2register.bmpNOCR1SA_7RW0OCR1SA_6RW0OCR1SA_5RW0OCR1SA_4RW0OCR1SA_3RW0OCR1SA_2RW0OCR1SA_1RW0OCR1SA_0RW0PSOC1PSC1 Synchro and Output ConfigurationNA0xE0register.bmpYPSYNC1_1Synchronization Out for ADC SelectionRW0PSYNC1_0Synchronization Out for ADC SelectionRW0POEN1BPSCOUT11 Output EnableRW0POEN1APSCOUT10 Output EnableRW0PIM1PSC1 Interrupt Mask RegisterNA$A3register.bmpYPSEIE1PSC 1 Synchro Error Interrupt EnableRW0PEVE1BExternal Event B Interrupt EnableRW0PEVE1AExternal Event A Interrupt EnableRW0PEOPE1End of Cycle Interrupt EnableRW0PIFR1PSC1 Interrupt Flag RegisterNA$A2register.bmpYPSEI1PSC 1 Synchro Error InterruptRW0PEV1BExternal Event B InterruptRW0PEV1AExternal Event A InterruptRW0PRN11Ramp NumberR0PRN10Ramp NumberR0PEOP1End of PSC1 InterruptRW0[PICR2H:PICR2L:PFRC2B:PFRC2A:PCTL2:PCNF2:OCR2RBH:OCR2RBL:OCR2SBH:OCR2SBL:OCR2RAH:OCR2RAL:OCR2SAH:OCR2SAL:POM2:PSOC2:PIM2:PIFR2]io_com.bmpPower Stage ControllerPICR2HPSC 2 Input Capture Register HighNA0xFFregister.bmpNPICR2_11R0PICR2_10R0PICR2_9R0PICR2_8R0PICR2LPSC 2 Input Capture Register LowNA0xFEregister.bmpNPICR2_7R0PICR2_6R0PICR2_5R0PICR2_4R0PICR2_3R0PICR2_2R0PICR2_1R0PICR2_0R0PFRC2BPSC 2 Input B ControlNA0xFDregister.bmpYPCAE2BPSC 2 Capture Enable Input Part BRW0PISEL2BPSC 2 Input Select for Part BRW0PELEV2BPSC 2 Edge Level Selector on Input Part BRW0PFLTE2BPSC 2 Filter Enable on Input Part BRW0PRFM2B3PSC 2 Retrigger and Fault Mode for Part BRW0PRFM2B2PSC 2 Retrigger and Fault Mode for Part BRW0PRFM2B1PSC 2 Retrigger and Fault Mode for Part BRW0PRFM2B0PSC 2 Retrigger and Fault Mode for Part BRW0PFRC2APSC 2 Input B ControlNA0xFCregister.bmpYPCAE2APSC 2 Capture Enable Input Part ARW0PISEL2APSC 2 Input Select for Part ARW0PELEV2APSC 2 Edge Level Selector on Input Part ARW0PFLTE2APSC 2 Filter Enable on Input Part ARW0PRFM2A3PSC 2 Retrigger and Fault Mode for Part ARW0PRFM2A2PSC 2 Retrigger and Fault Mode for Part ARW0PRFM2A1PSC 2 Retrigger and Fault Mode for Part ARW0PRFM2A0PSC 2 Retrigger and Fault Mode for Part ARW0PCTL2PSC 2 Control RegisterNA0xFBregister.bmpYPPRE21PSC 2 Prescaler Select 1RW0PPRE20PSC 2 Prescaler Select 0RW0PBFM2Balance Flank Width ModulationRW0PAOC2BPSC 2 Asynchronous Output Control BRW0PAOC2APSC 2 Asynchronous Output Control ARW0PARUN2PSC2 Auto RunRW0PCCYC2PSC2 Complete CycleRW0PRUN2PSC 2 RunRW0PCNF2PSC 2 Configuration RegisterNA0xFAregister.bmpYPFIFTY2PSC 2 FiftyRW0PALOCK2PSC 2 AutolockRW0PLOCK2PSC 2 LockRW0PMODE21PSC 2 ModeRW0PMODE20PSC 2 ModeRW0POP2PSC 2 Output PolarityRW0PCLKSEL2PSC 2 Input Clock SelectRW0POME2PSC 2 Output Matrix EnableRW0OCR2RBHOutput Compare RB Register HighNA0xF9register.bmpNOCR2RB_15RW0OCR2RB_14RW0OCR2RB_13RW0OCR2RB_12RW0OCR2RB_11RW0OCR2RB_10RW0OCR2RB_9RW0OCR2RB_8RW0OCR2RBLOutput Compare RB Register LowNA0xF8register.bmpNOCR2RB_7RW0OCR2RB_6RW0OCR2RB_5RW0OCR2RB_4RW0OCR2RB_3RW0OCR2RB_2RW0OCR2RB_1RW0OCR2RB_0RW0OCR2SBHOutput Compare SB Register HighNA0xF7register.bmpNOCR2SB_11RW0OCR2SB_10RW0OCR2SB_9RW0OCR2SB_8RW0OCR2SBLOutput Compare SB Register LowNA0xF6register.bmpNOCR2SB_7RW0OCR2SB_6RW0OCR2SB_5RW0OCR2SB_4RW0OCR2SB_3RW0OCR2SB_2RW0OCR2SB_1RW0OCR2SB_0RW0OCR2RAHOutput Compare RA Register HighNA0xF5register.bmpNOCR2RA_11RW0OCR2RA_10RW0OCR2RA_9RW0OCR2RA_8RW0OCR2RALOutput Compare RA Register LowNA0xF4register.bmpNOCR2RA_7RW0OCR2RA_6RW0OCR2RA_5RW0OCR2RA_4RW0OCR2RA_3RW0OCR2RA_2RW0OCR2RA_1RW0OCR2RA_0RW0OCR2SAHOutput Compare SA Register HighNA0xF3register.bmpNOCR2SA_11RW0OCR2SA_10RW0OCR2SA_9RW0OCR2SA_8RW0OCR2SALOutput Compare SA Register LowNA0xF2register.bmpNOCR2SA_7RW0OCR2SA_6RW0OCR2SA_5RW0OCR2SA_4RW0OCR2SA_3RW0OCR2SA_2RW0OCR2SA_1RW0OCR2SA_0RW0POM2PSC 2 Output MatrixNA0xF1register.bmpYPOMV2B3Output Matrix Output B Ramp 3RW0POMV2B2Output Matrix Output B Ramp 2RW0POMV2B1Output Matrix Output B Ramp 2RW0POMV2B0Output Matrix Output B Ramp 0RW0POMV2A3Output Matrix Output A Ramp 3RW0POMV2A2Output Matrix Output A Ramp 2RW0POMV2A1Output Matrix Output A Ramp 1RW0POMV2A0Output Matrix Output A Ramp 0RW0PSOC2PSC2 Synchro and Output ConfigurationNA0xF0register.bmpYPOS23PSC 2 Output 23 SelectRW0POS22PSC 2 Output 22 SelectRW0PSYNC2_1Synchronization Out for ADC SelectionRW0PSYNC2_0Synchronization Out for ADC SelectionRW0POEN2DPSCOUT23 Output EnableRW0POEN2BPSCOUT21 Output EnableRW0POEN2CPSCOUT22 Output EnableRW0POEN2APSCOUT20 Output EnableRW0PIM2PSC2 Interrupt Mask RegisterNA$A5register.bmpYPSEIE2PSC 2 Synchro Error Interrupt EnableRW0PEVE2BExternal Event B Interrupt EnableRW0PEVE2AExternal Event A Interrupt EnableRW0PEOPE2End of Cycle Interrupt EnableRW0PIFR2PSC2 Interrupt Flag RegisterNA$A4register.bmpYPSEI2PSC 2 Synchro Error InterruptRW0PEV2BExternal Event B InterruptRW0PEV2AExternal Event A InterruptRW0PRN21Ramp NumberR0PRN20Ramp NumberR0PEOP2End of PSC2 InterruptRW0[EUDR:EUCSRA:EUCSRB:EUCSRC:MUBRRH:MUBRRL]
[MUBRRH:MUBRRL]
io_com.bmpEUDREUSART I/O Data RegisterNA0xCEio_com.bmpNEUDR7EUSART I/O Data Register bit 7RW0EUDR6EUSART I/O Data Register bit 6RW0EUDR5EUSART I/O Data Register bit 5RW0EUDR4EUSART I/O Data Register bit 4RW0EUDR3EUSART I/O Data Register bit 3RW0EUDR2EUSART I/O Data Register bit 2RW0EUDR1EUSART I/O Data Register bit 1RW0EUDR0EUSART I/O Data Register bit 0RW0EUCSRAEUSART Control and Status Register ANA0xC8io_flag.bmpYUTxS3EUSART Control and Status Register A Bit 7.RW0UTxS2EUSART Control and Status Register A Bit 6RW0UTxS1EUSART Control and Status Register A Bit 5RW1UTxS0EUSART Control and Status Register A Bit 4RW1URxS3EUSART Control and Status Register A Bit 3RW0URxS2EUSART Control and Status Register A Bit 2RW0URxS1EUSART Control and Status Register A Bit 1RW1URxS0EUSART Control and Status Register A Bit 0RW1EUCSRBEUSART Control Register BNA0xC9io_flag.bmpYEUSARTEUSART Enable BitRW0EUSBSEUSBS Enable BitRW0EMCHManchester Mode BitRW0BODROrder BitRW0EUCSRCEUSART Status Register CNA0xCAio_flag.bmpYFEMFrame Error Manchester BitR0F1617F1617 BitR0STP1Stop Bit 1R0STP0Stop Bit 0R0MUBRRHManchester Receiver Baud Rate Register High ByteNA0xCDio_com.bmpYMUBRR15Manchester Receiver Baud Rate Register Bit 15RW0MUBRR14Manchester Receiver Baud Rate Register Bit 14RW0MUBRR13Manchester Receiver Baud Rate Register Bit 13RW0MUBRR12Manchester Receiver Baud Rate Register Bit 12RW0MUBRR11Manchester Receiver Baud Rate Register Bit 11RW0MUBRR10Manchester Receiver Baud Rate Register Bit 10RW0MUBRR9Manchester Receiver Baud Rate Register Bit 9RW0MUBRR8Manchester Receiver Baud Rate Register Bit 8RW0MUBRRLManchester Receiver Baud Rate Register Low ByteNA0xCCio_com.bmpYMUBRR7Manchester Receiver Baud Rate Register Bit 7RW0MUBRR6Manchester Receiver Baud Rate Register Bit 6RW0MUBRR5Manchester Receiver Baud Rate Register Bit 5RW0MUBRR4Manchester Receiver Baud Rate Register Bit 4RW0MUBRR3Manchester Receiver Baud Rate Register Bit 3RW0MUBRR2Manchester Receiver Baud Rate Register Bit 2RW0MUBRR1Manchester Receiver Baud Rate Register Bit 1RW0MUBRR0Manchester Receiver Baud Rate Register Bit 0RW0[AC0CON:AC1CON:AC2CON]io_analo.bmpAlgComp_14AC0CONAnalog Comparator 0 Control RegisterNA$ADio_flag.bmpYAC0ENAnalog Comparator 0 Enable BitRW0AC0IEAnalog Comparator 0 Interrupt Enable BitRW0AC0IS1Analog Comparator 0 Interrupt Select BitRW0AC0IS0Analog Comparator 0 Interrupt Select BitRW0AC0M2Analog Comparator 0 Multiplexer RegisterRW0AC0M1Analog Comparator 0 Multiplexer RegsiterRW0AC0M0Analog Comparator 0 Multiplexer RegisterRW0AC1CONAnalog Comparator 1 Control RegisterNA$AEio_flag.bmpYAC1ENAnalog Comparator 1 Enable BitRW0AC1IEAnalog Comparator 1 Interrupt Enable BitRW0AC1IS1Analog Comparator 1 Interrupt Select BitRW0AC1IS0Analog Comparator 1 Interrupt Select BitRW0AC1ICEAnalog Comparator 1 Interrupt Capture Enable BitRW0AC1M2Analog Comparator 1 Multiplexer RegisterRW0AC1M1Analog Comparator 1 Multiplexer RegsiterRW0AC1M0Analog Comparator 1 Multiplexer RegisterRW0AC2CONAnalog Comparator 2 Control RegisterNA$AFio_flag.bmpYAC2ENAnalog Comparator 2 Enable BitRW0AC2IEAnalog Comparator 2 Interrupt Enable BitRW0AC2IS1Analog Comparator 2 Interrupt Select BitRW0AC2IS0Analog Comparator 2 Interrupt Select BitRW0AC2M2Analog Comparator 2 Multiplexer RegisterRW0AC2M1Analog Comparator 2 Multiplexer RegsiterRW0AC2M0Analog Comparator 2 Multiplexer RegisterRW0ACSRAnalog Comparator Status Registerio_flag.bmpYACCKDIVAnalog Comparator Clock DividerRW0AC2IFAnalog Comparator 2 Interrupt Flag BitRW0AC1IFAnalog Comparator 1 Interrupt Flag BitRW0AC0IFAnalog Comparator 0 Interrupt Flag BitRW0AC2OAnalog Comparator 2 Output BitRW0AC1OAnalog Comparator 1 Output BitRW0AC0OAnalog Comparator 0 Output BitRW0[DACH:DACL:DACON]((IF DACON.DALA = 0) LINK [DACH(1:0):DACL(7:0)]); (IF DACON.DALA = 1) LINK [DACH(7:0):DACL(7:6)]);io_analo.bmpDigital to Analog ConverterDACHDAC Data Register High ByteNA$ACio_analo.bmpYDACH7DAC Data Register High Byte Bit 7RW0DACH6DAC Data Register High Byte Bit 6RW0DACH5DAC Data Register High Byte Bit 5RW0DACH4DAC Data Register High Byte Bit 4RW0DACH3DAC Data Register High Byte Bit 3RW0DACH2DAC Data Register High Byte Bit 2RW0DACH1DAC Data Register High Byte Bit 1RW0DACH0DAC Data Register High Byte Bit 0RW0DACLDAC Data Register Low ByteNA$ABio_flag.bmpYDACL7DAC Data Register Low Byte Bit 7RW0DACL6DAC Data Register Low Byte Bit 6RW0DACL5DAC Data Register Low Byte Bit 5RW0DACL4DAC Data Register Low Byte Bit 4RW0DACL3DAC Data Register Low Byte Bit 3RW0DACL2DAC Data Register Low Byte Bit 2RW0DACL1DAC Data Register Low Byte Bit 1RW0DACL0DAC Data Register Low Byte Bit 0RW0DACONDAC Control RegisterNA$AAio_analo.bmpNDAATEDAC Auto Trigger Enable BitRW0DATS2DAC Trigger Selection Bit 2RW0DATS1DAC Trigger Selection Bit 1RW0DATS0DAC Trigger Selection Bit 0RW0DALADAC Left AdjustRW0DAOEDAC Output Enable BitRW0DAENDAC Enable BitRW0[SREG:SPH:SPL:MCUCR:MCUSR:OSCCAL:CLKPR:SMCR:GPIOR3:GPIOR2:GPIOR1:GPIOR0:PLLCSR]
[SPH:SPL]
io_cpu.bmpSREGStatus Register$3F$5Fio_sreg.bmpYIGlobal Interrupt EnableThe global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable bit is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts.RW0TBit Copy StorageThe bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction.RW0HHalf Carry FlagThe half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed information.RW0SSign BitThe S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruc-tion Set Description for detailed information.RW0VTwo's Complement Overflow FlagThe two’s complement overflow flag V supports two’s complement arithmetics. See the Instruction Set Description for detailed information.RW0NNegative FlagThe negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.RW0ZZero FlagThe zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.RW0CCarry FlagThe carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software.RW0SPHStack Pointer HighThe general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the AT90S4414/8515 supports up to 64 kB external SRAM, all 16-bits are used. The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or return from interrupt R$3E$5Eio_sph.bmpNSP15Stack pointer bit 15RW0SP14Stack pointer bit 14RW0SP13Stack pointer bit 13RW0SP12Stack pointer bit 12RW0SP11Stack pointer bit 11RW0SP10Stack pointer bit 10RW0SP9Stack pointer bit 9RW0SP8Stack pointer bit 8RW0SPLStack Pointer LowThe general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the AT90S4414/8515 supports up to 64 kB external SRAM, all 16-bits are used. The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or return from interrupt $3D$5Dio_sph.bmpNSP7Stack pointer bit 7RW0SP6Stack pointer bit 6RW0SP5Stack pointer bit 5RW0SP4Stack pointer bit 4RW0SP3Stack pointer bit 3RW0SP2Stack pointer bit 2RW0SP1Stack pointer bit 1RW0SP0Stack pointer bit 0RW0MCUCRMCU Control RegisterThe MCU Control Register contains control bits for general MCU functions.$35$55io_flag.bmpYSPIPSSPI Pin SelectRW0PUDPull-up disableWhen this bit is written to one,the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn registers are configured to enable the pull-ups ({DDxn,PORTxn}=0b01). RW0IVSELInterrupt Vector SelectWhen the IVSEL bit is cleared (zero),the interrupt vectors are placed at the start of the Flash memory.When this bit is set (one),the interrupt vectors are moved to the beginning of the Boot Loader section of the flash.The actual address of the start of the boot flash section is determined by the BOOTSZ fuses. RW0IVCEInterrupt Vector Change EnableThe IVCE bit must be written to logic one to enable change of the IVSEL bit.IVCE is cleared by hardware four cycles after it is written or when IVSEL is written.Setting the IVCE bit will disable interrupts. RW0MCUSRMCU Status RegisterThe MCU Status Register provides information on which reset source caused an MCU reset.$34$54io_flag.bmpYWDRFWatchdog Reset FlagThis bit is set if a watchdog reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.R/W0BORFBrown-out Reset FlagThis bit is set if a brown-out reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.R/W0EXTRFExternal Reset FlagThis bit is set if an external reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.R/W0PORFPower-on reset flagThis bit is set if a power-on reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the reset flags to identify a reset condition, the user should read and then reset the MCUCSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags.R/W0OSCCALOscillator Calibration ValueWriting the calibration byte to this address will trim the internal oscillator to remove process variations from the oscillator frequency. This is done automatically during chip reset. When OSCCAL is zero, the lowest available frequency is chosen. Writing non-zero values to this register will increase the frequency of the internal oscillator. Writing $FF to the register gives the highest available frequency. The calibrated oscillator is used to time EEPROM and Flash access. If EEPROM or Flash is written, do not calibrate to more than 10% above the nominal frequency. Otherwise, the EEPROM or Flash write may fail. Note that the Oscillator is intended for calibration to 1.0 MHz, 2.0 MHz, 4.0 MHz, or 8.0MHz. Tuning to other values is not guaranteed, as indicated in Table 14NA$66io_cpu.bmpNCAL6Oscillator Calibration Value Bit6R/W0CAL5Oscillator Calibration Value Bit5R/W0CAL4Oscillator Calibration Value Bit4R/W0CAL3Oscillator Calibration Value Bit3R/W0CAL2Oscillator Calibration Value Bit2R/W0CAL1Oscillator Calibration Value Bit1R/W0CAL0Oscillator Calibration Value Bit0R/W0CLKPRNA$61io_cpu.bmpYCLKPCECLKPS3CLKPS2CLKPS1CLKPS0SMCRSleep Mode Control RegisterThe Sleep Mode Control Register contains control bits for power management.$33$53io_cpu.bmpYSM2Sleep Mode Select bit 2These bits select between the five available sleep modes.RW0SM1Sleep Mode Select bit 1These bits select between the five available sleep modes.RW0SM0Sleep Mode Select bit 0These bits select between the five available sleep modes.RW0SESleep EnableThe SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed.ToRW0GPIOR3General Purpose IO Register 3$1B$3Bio_cpu.bmpYGPIOR37General Purpose IO Register 3 bit 7RW0GPIOR36General Purpose IO Register 3 bit 6RW0GPIOR35General Purpose IO Register 3 bit 5RW0GPIOR34General Purpose IO Register 3 bit 4RW0GPIOR33General Purpose IO Register 3 bit 3RW0GPIOR32General Purpose IO Register 3 bit 2RW0GPIOR31General Purpose IO Register 3 bit 1RW0GPIOR30General Purpose IO Register 3 bit 0RW0GPIOR2General Purpose IO Register 2$1A$3Aio_cpu.bmpYGPIOR27General Purpose IO Register 2 bit 7RW0GPIOR26General Purpose IO Register 2 bit 6RW0GPIOR25General Purpose IO Register 2 bit 5RW0GPIOR24General Purpose IO Register 2 bit 4RW0GPIOR23General Purpose IO Register 2 bit 3RW0GPIOR22General Purpose IO Register 2 bit 2RW0GPIOR21General Purpose IO Register 2 bit 1RW0GPIOR20General Purpose IO Register 2 bit 0RW0GPIOR1General Purpose IO Register 1$19$39io_cpu.bmpYGPIOR17General Purpose IO Register 1 bit 7RW0GPIOR16General Purpose IO Register 1 bit 6RW0GPIOR15General Purpose IO Register 1 bit 5RW0GPIOR14General Purpose IO Register 1 bit 4RW0GPIOR13General Purpose IO Register 1 bit 3RW0GPIOR12General Purpose IO Register 1 bit 2RW0GPIOR11General Purpose IO Register 1 bit 1RW0GPIOR10General Purpose IO Register 1 bit 0RW0GPIOR0General Purpose IO Register 0$1E$3Eio_cpu.bmpYGPIOR07General Purpose IO Register 0 bit 7RW0GPIOR06General Purpose IO Register 0 bit 6RW0GPIOR05General Purpose IO Register 0 bit 5RW0GPIOR04General Purpose IO Register 0 bit 4RW0GPIOR03General Purpose IO Register 0 bit 3RW0GPIOR02General Purpose IO Register 0 bit 2RW0GPIOR01General Purpose IO Register 0 bit 1RW0GPIOR00General Purpose IO Register 0 bit 0RW0PLLCSRPLL Control And Status Register$29$49io_sreg.bmpYPLLFPLL FactorThe PLLF bit is used to select the division factor of the PLL.RW0PLLEPLL EnableRW0PLOCKPLL Lock DetectorR0[PORTE:DDRE:PINE]io_port.bmpAVRSimIOPort.SimIOPortPORTEPort E Data Register$0E$2Eio_port.bmpNPORTE2RW0PORTE1RW0PORTE0RW0DDREPort E Data Direction Register$0D$2Dio_flag.bmpNDDE2RW0DDE1RW0DDE0RW0PINEPort E Input Pins$0C$2Cio_port.bmpNPINE2R0PINE1R0PINE0R0[TIMSK0:TIFR0:TCCR0A:TCCR0B:TCNT0:OCR0A:OCR0B:GTCCR]io_timer.bmpAt8pwm0_12TIMSK0Timer/Counter0 Interrupt Mask RegisterNA$6Eio_flag.bmpYOCIE0BTimer/Counter0 Output Compare Match B Interrupt EnableRW0OCIE0ATimer/Counter0 Output Compare Match A Interrupt EnableRW0TOIE0Timer/Counter0 Overflow Interrupt EnableRW0TIFR0Timer/Counter0 Interrupt Flag register$15$35io_flag.bmpYOCF0BTimer/Counter0 Output Compare Flag 0BRW0OCF0ATimer/Counter0 Output Compare Flag 0ARW0TOV0Timer/Counter0 Overflow FlagRW0TCCR0ATimer/Counter Control Register A$24$44io_flag.bmpYCOM0A1Compare Output Mode, Phase Correct PWM ModeRW0COM0A0Compare Output Mode, Phase Correct PWM ModeRW0COM0B1Compare Output Mode, Fast PWmW0COM0B0Compare Output Mode, Fast PWmRW0WGM01Waveform Generation ModeRW0WGM00Waveform Generation ModeRW0TCCR0BTimer/Counter Control Register B$25$45io_flag.bmpYFOC0AForce Output Compare AW0FOC0BForce Output Compare BW0WGM02RW0CS02Clock SelectRW0CS01Clock SelectRW0CS00Clock SelectRW0TCNT0Timer/Counter0The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT0 register blocks (removes) the compare match on the following timer clock. Modifying the counter (TCNT0) while the counter is running, introduces a risk of missing a compare match between TCNT0 the OCR0 register.$26$46io_timer.bmpNTCNT0_7RW0TCNT0_6RW0TCNT0_5RW0TCNT0_4RW0TCNT0_3RW0TCNT0_2RW0TCNT0_1RW0TCNT0_0RW0OCR0ATimer/Counter0 Output Compare RegisterThe Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC0 pin.$27$47io_timer.bmpNOCR0_7RW0OCR0_6RW0OCR0_5RW0OCR0_4RW0OCR0_3RW0OCR0_2RW0OCR0_1RW0OCR0_0RW0OCR0BTimer/Counter0 Output Compare RegisterThe Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC0 pin.$28$48io_timer.bmpNOCR0_7RW0OCR0_6RW0OCR0_5RW0OCR0_4RW0OCR0_3RW0OCR0_2RW0OCR0_1RW0OCR0_0RW0GTCCRGeneral Timer/Counter Control Register$23$43io_flag.bmpYTSMTimer/Counter Synchronization ModeWriting the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSR2 and PSR10 bits is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSR2 and PSR10 bits are cleared by hardware, and the Timer/Counters start counting simultaneouslRW0ICPSEL1Timer1 Input Capture Selection BitRW0PSR10Prescaler Reset Timer/Counter1 and Timer/Counter0When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers.RW0[TIMSK1:TIFR1:TCCR1A:TCCR1B:TCCR1C:TCNT1H:TCNT1L:OCR1AH:OCR1AL:OCR1BH:OCR1BL:ICR1H:ICR1L:GTCCR]
[TCNT1H:TCNT1L];[OCR1AH:OCR1AL];[OCR1BH:OCR1BL];[ICR1H:ICR1L]
io_timer.bmpt16pwm1_12.xmlTIMSK1Timer/Counter Interrupt Mask RegisterNA$6Fio_flag.bmpYICIE1Timer/Counter1 Input Capture Interrupt EnableWhen the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on pin 31, ICP, i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.RW0OCIE1BTimer/Counter1 Output CompareB Match Interrupt EnableWhen the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter1 occurs, i.e., when the OCF1B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.R0OCIE1ATimer/Counter1 Output CompareA Match Interrupt EnableWhen the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a CompareA match in Timer/Counter1 occurs, i.e., when the OCF1A bit is set in the Timer/Counter Interrupt Flag Register - TIFR.RW0TOIE1Timer/Counter1 Overflow Interrupt EnableWhen the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $006) is executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.RW0TIFR1Timer/Counter Interrupt Flag register$16$36io_flag.bmpYICF1Input Capture Flag 1The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to the input capture register - ICR1. ICF1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF1 is cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable), and ICF1 are set (one), the Timer/Counter1 Capture Interrupt is executed. RW0OCF1BOutput Compare Flag 1BThe OCF1B bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1B - Output Compare Register 1B. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1B (Timer/Counter1 Compare match InterruptB Enable), and the OCF1B are set (one), the Timer/Counter1 Compare B match Interrupt is executed.RW0OCF1AOutput Compare Flag 1AThe OCF1A bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare match InterruptA Enable), and the OCF1A are set (one), the Timer/Counter1 Compare A match Interrupt is executed. RW0TOV1Timer/Counter1 Overflow FlagThe TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the cor-responding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter1 changes counting direction at $0000.RW0TCCR1ATimer/Counter1 Control Register ANA$80io_flag.bmpYCOM1A1Compare Output Mode 1A, bit 1The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA. This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10.RW0COM1A0Comparet Ouput Mode 1A, bit 0The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA. This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10.RW0COM1B1Compare Output Mode 1B, bit 1The COM1B1 and COM1B0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.RW0COM1B0Compare Output Mode 1B, bit 0The COM1B1 and COM1B0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.RW0WGM11Waveform Generation ModeCombined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.RW0WGM10Waveform Generation ModeCombined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.RW0TCCR1BTimer/Counter1 Control Register BNA$81io_flag.bmpYICNC1Input Capture 1 Noise CancelerWhen the ICNC1 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the ICP - input capture pin - as specified. When the ICNC1 bit is set (one), four successive samples are measures on the ICP - input capture pin, and all samples must be high/low according to the input capture trigger specification in the ICES1 bit. The actual sampling frequency is XTAL clock frequency.RW0ICES1Input Capture 1 Edge SelectWhile the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the falling edge of the input capture pin - ICP. While the ICES1 bit is set (one), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the rising edge of the input capture pin - ICP.RW0WGM13Waveform Generation ModeCombined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.RW0WGM12Waveform Generation ModeCombined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.RW0CS12Prescaler source of Timer/Counter 1Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.RW0CS11Prescaler source of Timer/Counter 1Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.RW0CS10Prescaler source of Timer/Counter 1Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.RW0TCCR1CTimer/Counter1 Control Register CNA$82io_flag.bmpYFOC1ARW0FOC1BRW0TCNT1HTimer/Counter1 High ByteThis 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR1A, OCR1B and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt rouNA$85io_timer.bmpNTCNT1H7Timer/Counter1 High Byte bit 7RW0TCNT1H6Timer/Counter1 High Byte bit 6RW0TCNT1H5Timer/Counter1 High Byte bit 5RW0TCNT1H4Timer/Counter1 High Byte bit 4RW0TCNT1H3Timer/Counter1 High Byte bit 3RW0TCNT1H2Timer/Counter1 High Byte bit 2RW0TCNT1H1Timer/Counter1 High Byte bit 1RW0TCNT1H0Timer/Counter1 High Byte bit 0RW0TCNT1LTimer/Counter1 Low ByteThis 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR1A, OCR1B and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interruNA$84io_timer.bmpNTCNT1L7Timer/Counter1 Low Byte bit 7RW0TCNT1L6Timer/Counter1 Low Byte bit 6RW0TCNT1L5Timer/Counter1 Low Byte bit 5RW0TCNT1L4Timer/Counter1 Low Byte bit 4RW0TCNT1L3Timer/Counter1 Low Byte bit 3RW0TCNT1L2Timer/Counter1 Low Byte bit 2RW0TCNT1L1Timer/Counter1 Low Byte bit 1RW0TCNT1L0Timer/Counter1 Low Byte bit 0RW0OCR1AHTimer/Counter1 Outbut Compare Register High ByteThe output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interruNA$89io_timer.bmpNOCR1AH7Timer/Counter1 Outbut Compare Register High Byte bit 7RW0OCR1AH6Timer/Counter1 Outbut Compare Register High Byte bit 6RW0OCR1AH5Timer/Counter1 Outbut Compare Register High Byte bit 5RW0OCR1AH4Timer/Counter1 Outbut Compare Register High Byte bit 4RW0OCR1AH3Timer/Counter1 Outbut Compare Register High Byte bit 3RW0OCR1AH2Timer/Counter1 Outbut Compare Register High Byte bit 2RW0OCR1AH1Timer/Counter1 Outbut Compare Register High Byte bit 1RW0OCR1AH0Timer/Counter1 Outbut Compare Register High Byte bit 0RW0OCR1ALTimer/Counter1 Outbut Compare Register Low ByteThe output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interruNA$88io_timer.bmpNOCR1AL7Timer/Counter1 Outbut Compare Register Low Byte Bit 7RW0OCR1AL6Timer/Counter1 Outbut Compare Register Low Byte Bit 6RW0OCR1AL5Timer/Counter1 Outbut Compare Register Low Byte Bit 5RW0OCR1AL4Timer/Counter1 Outbut Compare Register Low Byte Bit 4RW0OCR1AL3Timer/Counter1 Outbut Compare Register Low Byte Bit 3RW0OCR1AL2Timer/Counter1 Outbut Compare Register Low Byte Bit 2RW0OCR1AL1Timer/Counter1 Outbut Compare Register Low Byte Bit 1RW0OCR1AL0Timer/Counter1 Outbut Compare Register Low Byte Bit 0RW0OCR1BHTimer/Counter1 Output Compare Register High ByteThe output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt roNA$8Bio_timer.bmpNOCR1BH7Timer/Counter1 Output Compare Register High Byte bit 7RW0OCR1BH6Timer/Counter1 Output Compare Register High Byte bit 6RW0OCR1BH5Timer/Counter1 Output Compare Register High Byte bit 5RW0OCR1BH4Timer/Counter1 Output Compare Register High Byte bit 4RW0OCR1BH3Timer/Counter1 Output Compare Register High Byte bit 3RW0OCR1BH2Timer/Counter1 Output Compare Register High Byte bit 2RW0OCR1BH1Timer/Counter1 Output Compare Register High Byte bit 1RW0OCR1BH0Timer/Counter1 Output Compare Register High Byte bit 0RW0OCR1BLTimer/Counter1 Output Compare Register Low ByteThe output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt routNA$8Aio_timer.bmpNOCR1BL7Timer/Counter1 Output Compare Register Low Byte bit 7R0OCR1BL6Timer/Counter1 Output Compare Register Low Byte bit 6RW0OCR1BL5Timer/Counter1 Output Compare Register Low Byte bit 5RW0OCR1BL4Timer/Counter1 Output Compare Register Low Byte bit 4RW0OCR1BL3Timer/Counter1 Output Compare Register Low Byte bit 3RW0OCR1BL2Timer/Counter1 Output Compare Register Low Byte bit 2RW0OCR1BL1Timer/Counter1 Output Compare Register Low Byte bit 1RW0OCR1BL0Timer/Counter1 Output Compare Register Low Byte bit 0RW0ICR1HTimer/Counter1 Input Capture Register High ByteThe input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES1) of the signal at the input capture pin -ICP - is detected, the current value of the Timer/Counter1 is transferred to the Input Capture Register - ICR1. At the same time, the input capture flag - ICF1 - is set (one). Since the Input Capture Register - ICR1 - is a 16-bit register, a temporary register TEMP is used when ICR1 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR1L, the data is sent to the CPU and the data of the high byte ICR1H is placed in the TEMP register. When the CPU reads the data in the high byte ICR1H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR1L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT1, OCR1A and OCR1B. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interruptNA$87io_timer.bmpNICR1H7Timer/Counter1 Input Capture Register High Byte bit 7RW0ICR1H6Timer/Counter1 Input Capture Register High Byte bit 6R0ICR1H5Timer/Counter1 Input Capture Register High Byte bit 5R0ICR1H4Timer/Counter1 Input Capture Register High Byte bit 4R0ICR1H3Timer/Counter1 Input Capture Register High Byte bit 3R0ICR1H2Timer/Counter1 Input Capture Register High Byte bit 2R0ICR1H1Timer/Counter1 Input Capture Register High Byte bit 1R0ICR1H0Timer/Counter1 Input Capture Register High Byte bit 0R0ICR1LTimer/Counter1 Input Capture Register Low ByteThe input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES1) of the signal at the input capture pin -ICP - is detected, the current value of the Timer/Counter1 is transferred to the Input Capture Register - ICR1. At the same time, the input capture flag - ICF1 - is set (one). Since the Input Capture Register - ICR1 - is a 16-bit register, a temporary register TEMP is used when ICR1 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR1L, the data is sent to the CPU and the data of the high byte ICR1H is placed in the TEMP register. When the CPU reads the data in the high byte ICR1H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR1L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT1, OCR1A and OCR1B. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interNA$86io_timer.bmpNICR1L7Timer/Counter1 Input Capture Register Low Byte bit 7R0ICR1L6Timer/Counter1 Input Capture Register Low Byte bit 6R0ICR1L5Timer/Counter1 Input Capture Register Low Byte bit 5R0ICR1L4Timer/Counter1 Input Capture Register Low Byte bit 4R0ICR1L3Timer/Counter1 Input Capture Register Low Byte bit 3R0ICR1L2Timer/Counter1 Input Capture Register Low Byte bit 2R0ICR1L1Timer/Counter1 Input Capture Register Low Byte bit 1R0ICR1L0Timer/Counter1 Input Capture Register Low Byte bit 0R0GTCCRGeneral Timer/Counter Control Register$23$43io_flag.bmpYTSMTimer/Counter Synchronization ModeWriting the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSR2 and PSR10 bits is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSR2 and PSR10 bits are cleared by hardware, and the Timer/Counters start counting simultaneousRW0PSRSYNCPrescaler Reset Timer/Counter1 and Timer/Counter0When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers.RW0[ADMUX:ADCSRA:ADCH:ADCL:ADCSRB:DIDR0:DIDR1]((IF ADMUX.ADLAR = 1) LINK [ADCH(1:0):ADCL(7:0)]); (IF ADMUX.ADLAR = 0) LINK [ADCH(7:0):ADCL(7:6)]);io_analo.bmpAD Converter Feature list: 10-bit Resolution. 0.5 LSB Integral Non-Linearity. +-2 LSB Absolute Accuracy. TBD - 260 µs Conversion Time. Up to TBD kSPS at maximum resolution. 8 Multiplexed Single Ended Input Channels. 7 Differential input channels (TQFP package only). 2 Differential input channels with optional gain of 10x and 200x (TQFP package only). Optional left adjustment for ADC result readout. 0 - VCC ADC Input Voltage Range. Selectable 2.56 V ADC reference voltage. Free Running or Single Conversion Mode. Interrupt on ADC Conversion Complete. Sleep Mode NoiADMUXThe ADC multiplexer Selection RegisterThese bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin.NA$7Cio_analo.bmpNREFS1Reference Selection Bit 1These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin.RW0REFS0Reference Selection Bit 0These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin.RW0ADLARLeft Adjust ResultThe ADLAR bit affects the presentation of the ADC conversion result in the ADC data register. If ADLAR is cleared, the result is right adjusted. If ADLAR is set, the result is left adjusted. Changing the ADLAR bit will affect the ADC data register immediately, regardless of any ongoing conversions. For a complete description of this bit, see “The ADC Data Register -ADCL and ADCH” on page 198. RW0MUX3Analog Channel and Gain Selection BitsThe value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).RW0MUX2Analog Channel and Gain Selection BitsThe value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).RW0MUX1Analog Channel and Gain Selection BitsThe value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).RW0MUX0Analog Channel and Gain Selection BitsThe value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).RW0ADCSRAThe ADC Control and Status registerNA$7Aio_flag.bmpYADENADC EnableWriting a logical ‘1’ to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.RW0ADSCADC Start ConversionIn Single Conversion Mode, a logical ‘1’ must be written to this bit to start each conversion. In Free Running Mode, a logical ‘1’ must be written to this bit to start the first conversion. The first time ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, an extended conversion will result. This extended conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. When a dummy conversion precedes a real conversion, ADSC will stay high until the real conversion completes. Writing a 0 to this bit has no effectRW0ADATEADC Auto Trigger EnableWhen this bit is written to one,Auto Triggering of the ADC is enabled.The ADC will start a conversion on a positive edge of the selected trigger signal.The trigger source is selected by setting the ADC Trigger Select bits,ADTS in ADCSRB. RW0ADIFADC Interrupt FlagThis bit is set (one) when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set (one). ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a read-modify-write on ADCSR, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used.RW0ADIEADC Interrupt EnableWhen this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Complete Interrupt is activated.RW0ADPS2ADC Prescaler Select BitsThese bits determine the division factor between the XTAL frequency and the input clock to the ADC.RW0ADPS1ADC Prescaler Select BitsThese bits determine the division factor between the XTAL frequency and the input clock to the ADC.RW0ADPS0ADC Prescaler Select BitsThese bits determine the division factor between the XTAL frequency and the input clock to the ADC.RW0ADCHADC Data Register High ByteWhen an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. The selected channel is differential if MUX4..0 are between ‘01000’ and ‘11101’, otherwise the selected channel is single ended. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8 bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUX4..0 bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adjNA$79io_analo.bmpNADCH7ADC Data Register High Byte Bit 7RW0ADCH6ADC Data Register High Byte Bit 6RW0ADCH5ADC Data Register High Byte Bit 5RW0ADCH4ADC Data Register High Byte Bit 4RW0ADCH3ADC Data Register High Byte Bit 3RW0ADCH2ADC Data Register High Byte Bit 2RW0ADCH1ADC Data Register High Byte Bit 1RW0ADCH0ADC Data Register High Byte Bit 0RW0ADCLADC Data Register Low ByteWhen an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. The selected channel is differential if MUX4..0 are between ‘01000’ and ‘11101’, otherwise the selected channel is single ended. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8 bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUX4..0 bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right aNA$78io_analo.bmpNADCL7ADC Data Register Low Byte Bit 7RW0ADCL6ADC Data Register Low Byte Bit 6RW0ADCL5ADC Data Register Low Byte Bit 5RW0ADCL4ADC Data Register Low Byte Bit 4RW0ADCL3ADC Data Register Low Byte Bit 3RW0ADCL2ADC Data Register Low Byte Bit 2RW0ADCL1ADC Data Register Low Byte Bit 1RW0ADCL0ADC Data Register Low Byte Bit 0RW0ADCSRBADC Control and Status Register BNA$7Bio_analo.bmpNADHSMADC High Speed ModeRW0ADASCRADC on Amplified Channel Start Conversion Request BitRW0ADTS3ADC Auto Trigger Source 3RW0ADTS2ADC Auto Trigger Source 2RW0ADTS1ADC Auto Trigger Source 1RW0ADTS0ADC Auto Trigger Source 0RW0DIDR0Digital Input Disable Register 0NA$7Eio_analo.bmpNADC7DADC7 Digital input DisableWhen this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. ADC6DADC6 Digital input DisableWhen this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. ADC5DADC5 Digital input DisableWhen this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. ADC4DADC4 Digital input DisableWhen this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. ADC3DADC3 Digital input DisableWhen this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. ADC2DADC2 Digital input DisableWhen this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. ADC1DADC1 Digital input DisableWhen this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. ADC0DADC0 Digital input DisableWhen this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. NA$7FACMP0DAMP0PDAMP0NDADC10DADC9DADC8D[UDR:UCSRA:UCSRB:UCSRC:UBRRH:UBRRL]io_com.bmpUsart_00UDRUSART I/O Data RegisterNA0xC6io_com.bmpNUDR7USART I/O Data Register bit 7RW0UDR6USART I/O Data Register bit 6RW0UDR5USART I/O Data Register bit 5RW0UDR4USART I/O Data Register bit 4RW0UDR3USART I/O Data Register bit 3RW0UDR2USART I/O Data Register bit 2RW0UDR1USART I/O Data Register bit 1RW0UDR0USART I/O Data Register bit 0RW0UCSRAUSART Control and Status register ANA0xC0io_flag.bmpYRXCUSART Receive CompleteR0TXCUSART Transmitt CompleteRW0UDREUSART Data Register EmptyR1FEFraming ErrorR0DORData OverrunR0UPEUSART Parity ErrorR0U2XDouble USART Transmission BitRW0MPCMMulti-processor Communication ModeRW0UCSRBUSART Control an Status register BNA0xC1io_flag.bmpYRXCIERX Complete Interrupt EnableRW0TXCIETX Complete Interrupt EnableRW0UDRIEUSART Data Register Empty Interrupt EnableRW0RXENReceiver EnableRW0TXENTransmitter EnableRW0UCSZ2Character SizeRW0RXB8Receive Data Bit 8R0TXB8Transmit Data Bit 8RW0UCSRCUSART Control an Status register CNA0xC2io_flag.bmpYUMSEL0USART Mode SelectRW0UPM1Parity Mode Bit 1RW0UPM0Parity Mode Bit 0RW0USBSStop Bit SelectRW0UCSZ1Character Size Bit 1RW1UCSZ0Character Size Bit 0RW1UCPOLClock PolarityRW0UBRRHUSART Baud Rate Register High ByteNA0xC5io_com.bmpYUBRR11USART Baud Rate Register Bit 11RW0UBRR10USART Baud Rate Register Bit 10RW0UBRR9USART Baud Rate Register Bit 9RW0UBRR8USART Baud Rate Register Bit 8RW0UBRRLUSART Baud Rate Register Low ByteNA0xC4io_com.bmpYUBRR7USART Baud Rate Register bit 7RW0UBRR6USART Baud Rate Register bit 6RW0UBRR5USART Baud Rate Register bit 5RW0UBRR4USART Baud Rate Register bit 4RW0UBRR3USART Baud Rate Register bit 3RW0UBRR2USART Baud Rate Register bit 2RW0UBRR1USART Baud Rate Register bit 1RW0UBRR0USART Baud Rate Register bit 0RW0[SPDR:SPSR:SPCR]io_com.bmpThe Serial Peripheral Interface(SPI) allows high-speed synchronous data transfer between the AT90S4414/8515 and peripheral devices or between several AVR devices. The AT90S4414/8515 SPI features include the following: • Full-duplex, 3-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Four Programmable Bit Rates • End of Transmission Interrupt Flag • Write Collision Flag Protection • Wakeup from Idle Mode (Slave Mode Only)SPCRSPI Control Register$2C$4Cio_flag.bmpYSPIESPI Interrupt EnableThis bit causes the SPI interrupt to be executed if SPIF bit in the SPSR register is set and the global interrupts are enabled.RW0SPESPI EnableWhen the SPE bit is set (one), the SPI is enabled. This bit must be set to enable any SPI operations.RW0DORDData OrderWhen the DORD bit is set (one), the LSB of the data word is transmitted first. When the DORD bit is cleared (zero), the MSB of the data word is transmitted first.RW0MSTRMaster/Slave SelectThis bit selects Master SPI mode when set (one), and Slave SPI mode when cleared (zero). If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI master mode.RW0CPOLClock polarityWhen this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is low when idle. Refer to Figure 36 and Figure 37 for additional information.RW0CPHAClock PhaseRefer to Figure 36 or Figure 37 for the functionality of this bit.RW0SPR1SPI Clock Rate Select 1These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave.RW0SPR0SPI Clock Rate Select 0These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave.RW0SPSRSPI Status Register$2D$4Dio_flag.bmpYSPIFSPI Interrupt FlagWhen a serial transfer is complete, the SPIF bit is set (one) and an interrupt is generated if SPIE in SPCR is set (one) and global interrupts are enabled. If SS is an input and is driven low when the SPI is in master mode, this will also set the SPIF flag. SPIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the SPI status register when SPIF is set (one), then accessing the SPI Data Register (SPDR).R0WCOLWrite Collision FlagThe WCOL bit is set if the SPI data register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Register when WCOL is set (one), and then accessing the SPI Data Register.R0SPI2XDouble SPI Speed BitWhen this bit is written logic one the SPI speed (SCK Frequency)will be doubled when the SPI is in master mode .This means that the minimum SCK period will be 2 CPU clock periods.When the SPI is configured as Slave,the SPI is only guaranteed to work at f osc /4orlower. The SPI interface on the ATmega162 is also used for program memory and EEPROM downloading or uploading. RW0SPDRSPI Data RegisterThe SPI Data Register is a read/write register used for data transfer between the register file and the SPI Shift register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read.$2E$4Eio_com.bmpNSPDR7SPI Data Register bit 7RWXSPDR6SPI Data Register bit 6RWXSPDR5SPI Data Register bit 5RWXSPDR4SPI Data Register bit 4RWXSPDR3SPI Data Register bit 3RWXSPDR2SPI Data Register bit 2RWXSPDR1SPI Data Register bit 1R0SPDR0SPI Data Register bit 0R0[WDTCSR]io_watch.bmpWDTCSRWatchdog Timer Control RegisterNA$60io_flag.bmpYWDIFWatchdog Timeout Interrupt FlagRW0WDIEWatchdog Timeout Interrupt EnableRW0WDP3Watchdog Timer Prescaler Bit 3RW0WDCEWatchdog Change EnableRW0WDEWatch Dog EnableWhen the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdogRW0WDP2Watch Dog Timer Prescaler bit 2RW0WDP1Watch Dog Timer Prescaler bit 1RW0WDP0Watch Dog Timer Prescaler bit 0RW0[EICRA:EIMSK:EIFR]io_ext.bmpThe external interrupts are triggered by the INT7:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT7:0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The external inter-rupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the Exter-nal Interrupt Control Registers - EICRA (INT3:0) and EICRB (INT7:4). When the external interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT7:4 requires the presence of an I/O clock, described in “Clock Systems and their Distribution” on page 29. Low level interrupts and the edge interrupt on INT3:0 are detected asynchronously. This implies that these inter-rupts can be used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode. Note that if a level triggered interrupt is used for wake-up from Power Down Mode, the changed level must be held for some time to wake up the MCU. This makes the MCU less sensitive to noise. The changed level is sampled twice by the watchdog oscillator clock. The period of the watchdog oscillator is 1 µs (nominal) at 5.0V and 25°C. The frequency of the watchdog oscillator is voltage dependent as shown in the Electrical Characteristics section. The MCU will wake up if the input has the required level during this sampling or if it is held until the end of the start-up time. The start-up time is defined by the SUT fuses as described in “Clock Systems and their Distribution” on page 29. If the level is sampled twice by the watchdog oscillator clock but disappears before the end of the start-up time, the MCU will still wake up, but no interrupt will be generated. The required level must be held long enough for the MCU to complete the wake up to trigger the level interruptEICRAExternal Interrupt Control Register AThis Register can not be reached in ATmega103 compatibility mode, but the initial value defines INT3:0 as low level inter-rupts,as in ATmega103. • Bits 7..0 - ISC31, ISC30 - ISC00, ISC00: External Interrupt 3-0 Sense Control bits The External Interrupts 3 - 0 are activated by the external pins INT3:0 if the SREG I-flag and the corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that activate the interrupts are defined in Table 47. Edges on INT3..INT0 are registered asynchronously. Pulses on INT3:0 pins wider than the minimum pulse width given in Table 48 will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an interrupt request as long as the pin is held low. When changing the ISCn bit, an interrupt can occur. Therefore, it is recommended to first disable INTn by clearing its Interrupt Enable bit in the EIMSK register. Then, the ISCn bit can be changed. Finally, the INTn interrupt flag should be cleared by writing a logical one to its Interrupt Flag bit (INTFn) in the EIFR register before the interrupt is re-enableNA$69io_flag.bmpYISC31External Interrupt Sense Control BitRW0ISC30External Interrupt Sense Control BitRW0ISC21External Interrupt Sense Control BitRW0ISC20External Interrupt Sense Control BitRW0ISC11External Interrupt Sense Control BitRW0ISC10External Interrupt Sense Control BitRW0ISC01External Interrupt Sense Control BitRW0ISC00External Interrupt Sense Control BitRW0EIMSKExternal Interrupt Mask Register$1D$3Dio_flag.bmpYINT3External Interrupt Request 3 EnableRW0INT2External Interrupt Request 2 EnableRW0INT1External Interrupt Request 1 EnableRW0INT0External Interrupt Request 0 EnableRW0EIFRExternal Interrupt Flag Register$1C$3Cio_flag.bmpYINTF3External Interrupt Flag 3RW0INTF2External Interrupt Flag 2RW0INTF1External Interrupt Flag 1RW0INTF0External Interrupt Flag 0RW0[EEARH:EEARL:EEDR:EECR]
[EEARH:EEARL]
io_cpu.bmpEEPROM Read/Write Access. The EEPROM access registers are accessible in the I/O space. The write access time for the EEPROM is given in Table 1. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page 19. for details on how to avoid problems in these situations.In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When theEEPROM is written, the CPU is halted for two clock cycles before the next instruction is executeEEARHEEPROM Read/Write Access High ByteBits 11..0 - EEAR11..0: EEPROM Address The EEPROM Address Registers - EEARH and EEARL specify the EEPROM address in the 4K bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 4096. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed. $22$42io_cpu.bmpNEEAR11EEPROM Read/Write Access Bit 11RW0EEAR10EEPROM Read/Write Access Bit 10RW0EEAR9EEPROM Read/Write Access Bit 9RW0EEAR8EEPROM Read/Write Access Bit 8RW0EEARLEEPROM Read/Write Access Low ByteBits 11..0 - EEAR11..0: EEPROM Address The EEPROM Address Registers - EEARH and EEARL specify the EEPROM address in the 4K bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 4096. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed. $21$41io_cpu.bmpNEEARL7EEPROM Read/Write Access Bit 7RW0EEARL6EEPROM Read/Write Access Bit 6RW0EEARL5EEPROM Read/Write Access Bit 5RW0EEARL4EEPROM Read/Write Access Bit 4RW0EEARL3EEPROM Read/Write Access Bit 3RW0EEARL2EEPROM Read/Write Access Bit 2RW0EEARL1EEPROM Read/Write Access Bit 1RW0EEARL0EEPROM Read/Write Access Bit 0RW0EEDREEPROM Data RegisterFor the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.$20$40io_cpu.bmpNEEDR7EEPROM Data Register bit 7RW0EEDR6EEPROM Data Register bit 6RW0EEDR5EEPROM Data Register bit 5RW0EEDR4EEPROM Data Register bit 4RW0EEDR3EEPROM Data Register bit 3RW0EEDR2EEPROM Data Register bit 2RW0EEDR1EEPROM Data Register bit 1RW0EEDR0EEPROM Data Register bit 0RW0EECREEPROM Control Register$1F$3Fio_flag.bmpYEEPM1EEPROM Programming Mode Bit 1The EEPROM Programming mode bit setting defines which programming action will be triggered when writing EEWE.RWXEEPM0EEPROM Programming Mode Bit 0The EEPROM Programming mode bit setting defines which programming action will be triggered when writing EEWE.RWXEERIEEEPROM Ready Interrupt EnableEEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared.RW0EEMWEEEPROM Master Write EnableThe EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is written to one, writing EEWE to one within 4 clock cycles will write data to the EEPROM at the selected address. If EEMWE is zero, writing EEWE to one will have no effect. When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure.RW0EEWEEEPROM Write EnableThe EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential): 1. Wait until EEWE becomes zero. 2. Wait until SPMEN in SPMCR becomes zero. 3. Write new EEPROM address to EEAR (optional). 4. Write new EEPROM data to EEDR (optional). 5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR. 6. Within four clock cycles after setting EEMWE, write a logical one to EEWE. The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a boot loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See “Boot Loader Support - Read While Write self-programming” on page 228 for details about boot programming. Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR regis-ter will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the 4 last steps to avoid these problems. When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruc-tion is executedRWXEEREEEPROM Read EnableThe EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR register. The calibrated oscillator is used to time the EEPROM accesses. Table 1 lists the typical programming time for EEPROM access from the CPURW0[JTAGICEmkII:STK500_2:STK500:SIMULATOR:AVRISPmkII]0x9381DebugWire0xF8,0x7F,0x60,0xFE,0xFF,0x33,0xBD,0xE00xF8,0x7F,0x40,0xEE,0xFF,0x33,0xBC,0xE00X00,0X00,0X00,0X00,0X00,0X00,0X00,0X000X00,0X00,0X00,0X00,0X00,0X00,0X00,0X000x53,0xC2,0xC0,0xDF,0xF7,0x0F,0x00,0x00,0x3F,0xE4,0x00,0x00,0x36,0x37,0x01,0xFC,0x05,0xFC,0x07,0xFC0x11,0xC2,0xC0,0xD8,0xF7,0x0F,0x00,0x00,0x3F,0xE4,0x00,0x00,0x36,0x33,0x01,0xFC,0x05,0xFC,0x07,0xFC0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x000x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x000x000X000X006440x0F800x0F800x0F000x0E000x0C000xFF0x20000x0000,320x0020,640x000x400x000x000x200x000xBD,0xF2,0xBD,0xE1,0xBB,0xCF,0xB4,0x00,0xBE,0x01,0xB6,0x01,0xBC,0x00,0xBB,0xBF,0x99,0xF9,0xBB,0xAF0xB6,0x01,0x110x3e0x3d0x310x000x000x000xF800x000x520120120x3f2001002532030x53114510x4164100x400x4C0x000x000x000x41450xC10xC20x000x000x0025625644440x0E 0x1E 0x0F 0x1F 0x2E 0x3E 0x2F 0x3F 0x4E 0x5E 0x4F 0x5F 0x6E 0x7E 0x6F 0x7F 0x66 0x76 0x67 0x77 0x6A 0x7A 0x6B 0x7B 0xBE 0xFD 0x00 0x01 0x00 0x00 0x00 0x001000511510151501050x0D25625650x0525625605050x661110xFF0xFF0xFF01AVRSimCoreV2.SimCoreV2AVRSimMemory8bit.SimMemory8bitAVRSimInterrupt.SimInterrupt0x1a016AVRSimIOPort.SimIOPortYAVRSimIOPort.SimIOPortYAVRSimIOPort.SimIOPortYAVRSimIOPort.SimIOPortYAVRSimIOExtInterrupt.SimIOExtInterrupt0x0A0x1D0x010x1C0x010x090x010x490x03AVRSimIOExtInterrupt.SimIOExtInterrupt0x130x1D0x020x1C0x020x090x020x490x0cAVRSimIOExtInterrupt.SimIOExtInterrupt0x180x1D0x040x1C0x040x090x040x490x30AVRSimIOExtInterrupt.SimIOExtInterrupt0x1C0x1D0x080x1C0x080x090x080x490xc0AvrSimIOtim8pwmsync2.tim8pwmsync20x00110x00100x001BPORTD3PORTE1PINC2AVRSimIOTimert16pwm1.SimIOTimert16pwm10x0B0x0C0x0D0x0F0x090x400x090x100x050x200x050x400x050x80AVRSimIOSPM.SimIOSPM0x1FAVRSimIOSpi.SimIOSpi0x140x030x020x030x080x030x040x030x040x01AVRSimIOUsart.SimIOUsart0x150x170x160x0C0x020x0C0x01AvrMasterTimer.MasterTimer12810x192048:4096:8192:16384:32768:65536:131072:262144:524288:1048576AVRSimADC.SimADC0x120xFF0xff0xFF0xFF