[CORE:PROGVOLT:POWER:LOCKBIT:MEMORY:INTERRUPT_VECTOR:PACKAGE:IO_MODULE:ICE_SETTINGS:ADMIN:PROGRAMMING:FUSE] V2E AVRSimCoreV2.SimCoreV2 [] [] [] 32 $00 $1B $1A $1D $1C $1F $1E 2.7 6.0 4.5 5.5 4MHz 25C TBD mA TBD mA TBD uA [LB1 = 1 : LB2 = 1] No memory lock features enabled. [LB1 = 0 : LB2 = 1] Further programming of Flash and EEPROM is enabled. [LB1 = 0 : LB2 = 0] Same as previous, but verify is also disabled 6 11 0x03 0x03 Mode 1: No memory lock features enabled 0x03 0x02 Mode 2: Further programming disabled 0x03 0x00 Mode 3: Further programming and verification disabled 0x0C 0x0C Application Protection Mode 1: No lock on SPM and LPM in Application Section 0x0C 0x08 Application Protection Mode 2: SPM prohibited in Application Section 0x0C 0x00 Application Protection Mode 3: LPM and SPM prohibited in Application Section 0x0C 0x04 Application Protection Mode 4: LPM prohibited in Application Section 0x30 0x30 Boot Loader Protection Mode 1: No lock on SPM and LPM in Boot Loader Section 0x30 0x20 Boot Loader Protection Mode 2: SPM prohibited in Boot Loader Section 0x30 0x00 Boot Loader Protection Mode 3: LPM and SPM prohibited in Boot Loader Section 0x30 0x10 Boot Loader Protection Mode 4: LPM prohibited in Boot Loader Section LB1 Lock bit LB2 Lock bit BLB01 Boot Lock bit BLB02 Boot Lock bit BLB11 Boot lock bit BLB12 Boot lock bit AVRSimMemory8bit.SimMemory8bit 8192 512 512 $0100 0 NA $0000 $003F $0060 $00FF $0020 $00FF NA 0xFF 0x010x020x040x080x80 NA 0xFE 0x010x020x040x080x100x200x400x80 NA 0xFD 0x010x020x040x080x100x200x400x80 NA 0xFC 0x010x020x040x080x100x200x400x80 NA 0xFB 0x010x020x040x080x100x200x400x80 NA 0xFA 0x010x020x040x080x100x200x400x80 NA 0xF9 0x010x020x040x080x100x200x400x80 NA 0xF8 0x010x020x040x080x100x200x400x80 NA 0xF7 0x010x020x040x08 NA 0xF6 0x010x020x040x080x100x200x400x80 NA 0xF5 0x010x020x040x08 NA 0xF4 0x010x020x040x080x100x200x400x80 NA 0xF3 0x010x020x040x08 NA 0xF2 0x010x020x040x080x100x200x400x80 NA 0xF1 0x010x020x040x080x100x200x400x80 NA 0xF0 0x010x020x040x080x100x200x400x80 NA 0xEF 0x010x020x040x080x80 NA 0xEE 0x010x020x040x080x100x200x400x80 NA 0xED 0x010x020x040x080x100x200x400x80 NA 0xEC 0x010x020x040x080x100x200x400x80 NA 0xEB 0x010x020x040x080x100x200x400x80 NA 0xEA 0x020x040x080x100x200x400x80 NA 0xE9 0x010x020x040x080x100x200x400x80 NA 0xE8 0x010x020x040x080x100x200x400x80 NA 0xE7 0x010x020x040x08 NA 0xE6 0x010x020x040x080x100x200x400x80 NA 0xE5 0x010x020x040x08 NA 0xE4 0x010x020x040x080x100x200x400x80 NA 0xE3 0x010x020x040x08 NA 0xE2 0x010x020x040x080x100x200x400x80 NA 0xE0 0x010x040x100x20 NA 0xDF 0x010x020x040x080x80 NA 0xDE 0x010x020x040x080x100x200x400x80 NA 0xDD 0x010x020x040x080x100x200x400x80 NA 0xDC 0x010x020x040x080x100x200x400x80 NA 0xDB 0x010x020x040x080x100x200x400x80 NA 0xDA 0x020x040x080x100x200x400x80 NA 0xD9 0x010x020x040x080x100x200x400x80 NA 0xD8 0x010x020x040x080x100x200x400x80 NA 0xD7 0x010x020x040x08 NA 0xD6 0x010x020x040x080x100x200x400x80 NA 0xD5 0x010x020x040x08 NA 0xD4 0x010x020x040x080x100x200x400x80 NA 0xD3 0x010x020x040x08 NA 0xD2 0x010x020x040x080x100x200x400x80 NA 0xD0 0x010x040x100x20 NA 0xCE 0x010x020x040x080x100x200x400x80 NA 0xCD 0x010x020x040x080x100x200x400x80 NA 0xCC 0x010x020x040x080x100x200x400x80 NA 0xCA 0x010x020x040x08 NA 0xC9 0x010x020x080x10 NA 0xC8 0x010x020x040x080x100x200x400x80 NA 0xC6 0x010x020x040x080x100x200x400x80 NA 0xC5 0x010x020x040x08 NA 0xC4 0x010x020x040x080x100x200x400x80 NA 0xC2 0x010x020x040x080x100x200x40 NA 0xC1 0x010x020x040x080x100x200x400x80 NA 0xC0 0x010x020x040x080x100x200x400x80 NA $AF 0x010x020x040x100x200x400x80 NA $AE 0x010x020x040x080x100x200x400x80 NA $AD 0x010x020x040x100x200x400x80 NA $AC 0x010x020x040x080x100x200x400x80 NA $AB 0x010x020x040x080x100x200x400x80 NA $AA 0x010x020x040x100x200x400x80 NA $A5 0x010x080x100x20 NA $A4 0x010x020x040x080x100x200x400x80 NA $A3 0x010x080x100x20 NA $A2 0x010x020x040x080x100x200x400x80 NA $A1 0x010x080x100x20 NA $A0 0x010x020x040x080x100x200x400x80 NA $8B 0x010x020x040x080x100x200x400x80 NA $8A 0x010x020x040x080x100x200x400x80 NA $89 0x010x020x040x080x100x200x400x80 NA $88 0x010x020x040x080x100x200x400x80 NA $87 0x010x020x040x080x100x200x400x80 NA $86 0x010x020x040x080x100x200x400x80 NA $85 0x010x020x040x080x100x200x400x80 NA $84 0x010x020x040x080x100x200x400x80 NA $82 0x400x80 NA $81 0x010x020x040x080x100x400x80 NA $80 0x010x020x100x200x400x80 NA $7F 0x010x020x040x080x100x20 NA $7E 0x010x020x040x080x100x200x400x80 NA $7C 0x010x020x040x080x200x400x80 NA $7B 0x010x020x040x080x100x80 NA $7A 0x010x020x040x080x100x200x400x80 NA $79 0x010x020x040x080x100x200x400x80 NA $78 0x010x020x040x080x100x200x400x80 NA $77 NA $76 NA $6F 0x010x020x040x20 NA $6E 0x010x020x04 NA $69 0x010x020x040x080x100x200x400x80 NA $66 0x010x020x040x080x100x200x40 NA $64 NA $61 0x010x020x040x080x80 NA $60 0x010x020x040x080x100x200x400x80 $3F $5F 0x010x020x040x080x100x200x400x80 $3E $5E 0x010x020x040x080x100x200x400x80 $3D $5D 0x010x020x040x080x100x200x400x80 $37 $57 0x010x020x040x080x100x400x80 $35 $55 0x010x020x100x80 $34 $54 0x010x020x040x08 $33 $53 0x010x020x040x08 $30 $50 $2E $4E 0x010x020x040x080x100x200x400x80 $2D $4D 0x010x400x80 $2C $4C 0x010x020x040x080x100x200x400x80 $29 $49 0x010x020x04 $28 $48 0x010x020x040x080x100x200x400x80 $27 $47 0x010x020x040x080x100x200x400x80 $26 $46 0x010x020x040x080x100x200x400x80 $25 $45 0x010x020x040x080x400x80 $24 $44 0x010x020x100x200x400x80 $23 $43 0x010x400x800x01 $22 $42 0x010x020x040x08 $21 $41 0x010x020x040x080x100x200x400x80 $20 $40 0x010x020x040x080x100x200x400x80 $1F $3F 0x010x020x040x080x100x20 $1E $3E 0x010x020x040x080x100x200x400x80 $1D $3D 0x010x020x040x08 $1C $3C 0x010x020x040x08 $1B $3B 0x010x020x040x080x100x200x400x80 $1A $3A 0x010x020x040x080x100x200x400x80 $19 $39 0x010x020x040x080x100x200x400x80 $16 $36 0x010x020x040x20 $15 $35 0x010x020x04 $0E $2E 0x010x020x04 $0D $2D 0x010x020x04 $0C $2C 0x010x020x04 $0B $2B 0x010x020x040x080x100x200x400x80 $0A $2A 0x010x020x040x080x100x200x400x80 $09 $29 0x010x020x040x080x100x200x400x80 $08 $28 0x010x020x040x080x100x200x400x80 $07 $27 0x010x020x040x080x100x200x400x80 $06 $26 0x010x020x040x080x100x200x400x80 $05 $25 0x010x020x040x080x100x200x400x80 $04 $24 0x010x020x040x080x100x200x400x80 $03 $23 0x010x020x040x080x100x200x400x80 $C00 $FFF $0 $BFF 32 128 4 $0 $F80 $F80 256 8 $0 $F00 $F00 512 16 $0 $E00 $E00 1024 32 $0 $C00 $C00 32 AVRSimInterrupt.SimInterrupt $0000 RESET External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset and JTAG AVR Reset $0001 PSC2 CAPT PSC2 Capture Event $0002 PSC2 EC PSC2 End Cycle $0003 PSC1 CAPT PSC1 Capture Event $0004 PSC1 EC PSC1 End Cycle $0005 PSC0 CAPT PSC0 Capture Event $0006 PSC0 EC PSC0 End Cycle $0007 ANALOG COMP 0 Analog Comparator 0 $0008 ANALOG COMP 1 Analog Comparator 1 $0009 ANALOG COMP 2 Analog Comparator 2 $000A INT0 External Interrupt Request 0 $000B TIMER1 CAPT Timer/Counter1 Capture Event $000C TIMER1 COMPA Timer/Counter1 Compare Match A $000D TIMER1 COMPB Timer/Counter Compare Match B $000E RESERVED15 $000F TIMER1 OVF Timer/Counter1 Overflow $0010 TIMER0 COMP A Timer/Counter0 Compare Match A $0011 TIMER0 OVF Timer/Counter0 Overflow $0012 ADC ADC Conversion Complete $0013 INT1 External Interrupt Request 1 $0014 SPI, STC SPI Serial Transfer Complete $0015 USART, RX USART, Rx Complete $0016 USART, UDRE USART Data Register Empty $0017 USART, TX USART, Tx Complete $0018 INT2 External Interrupt Request 2 $0019 WDT Watchdog Timeout Interrupt $001A EE READY EEPROM Ready $001B TIMER0 COMPB Timer Counter 0 Compare Match B $001C INT3 External Interrupt Request 3 $001D RESERVED30 $001E RESERVED31 $001F SPM READY Store Program Memory Read [QFN:SOIC] 32 [PD2:PSCIN2:OC1A:MISO_A] [PD3:TXD:DALI:OC0A:SS:MOSI_A] [PC1:PSCIN1:OC1B] [VCC] [GND] [PC2:T0:PSCOUT22] [PC3:T1:PSCOUT23] [PB0:MISO:PSCOUT20] [PB1:MOSI:PSCOUT21] [PE1:OC0B:XTAL1] [PE2:ADC0:XTAL2] [PD4:ADC1:RXD:DALI:ICP1:SCK_A] [PD5:ADC2:ACOMP2] [PD6:ADC3:ACMPM:INT0] [PD7:ACMP0] [PB2:ADC5:INT1] [PC4:ADC8:AMP1-] [PC5:ADC9:AMP1+] [AVCC] [AGND] [AREF] [PC6:ADC10:ACMP1] [PB3:AMP0-] [PB4:AMP0+] [PC7:D2A] [PB5:ADC6:INT2] [PB6:ADC7:PSCOUT11:ICP1B] [PB7:ADC4:PSCOUT01:SCK) [PD0:PSCOUT00:XCK:SSA] [PC0:INT3:PSCOUT10] [PE0:RESET:OCD] [PD1:PSCIN0:CLK0] 32 [PD0:PSCOUT00:XCK:SSA] [PC0:INT3:PSCOUT10] [PE0:RESET:OCD] [PD1:PSCIN0:CLK0] [PD2:PSCIN2:OC1A:MISO_A] [PD3:TXD:DALI:OC0A:SS:MOSI_A] [PC1:PSCIN1:OC1B] [VCC] [GND] [PC2:T0:PSCOUT22] [PC3:T1:PSCOUT23] [PB0:MISO:PSCOUT20] [PB1:MOSI:PSCOUT21] [PE1:OC0B:XTAL1] [PE2:ADC0:XTAL2] [PD4:ADC1:RXD:DALI:ICP1:SCK_A] [PD5:ADC2:ACOMP2] [PD6:ADC3:ACMPM:INT0] [PD7:ACMP0] [PB2:ADC5:INT1] [PC4:ADC8:AMP1-] [PC5:ADC9:AMP1+] [AVCC] [AGND] [AREF] [PC6:ADC10:ACMP1] [PB3:AMP0-] [PB4:AMP0+] [PC7:D2A] [PB5:ADC6:INT2] [PB6:ADC7:PSCOUT11:ICP1B] [PB7:ADC4:PSCOUT01:SCK) AT90PWM3 8MHz 154 RELEASED $1E $93 $81 0xff,0xdf,0xff 0xff,0xdf,0xff 1,0x20,0x20,WARNING! These fuse settings will disable the ISP interface! 1,0x80,0x00,WARNING! Disabling external reset will make the ISP interface inaccessible! 1,0x40,0x00,WARNING! Enabling DEBUGWIRE will make the ISP interface inaccessible! 1,0x20,0x20,WARNING! These fuse settings will disable the ISP interface! 1,0x80,0x00,WARNING! Disabling external reset will make the ISP interface inaccessible! 1,0x40,0x00,WARNING! Enabling DEBUGWIRE will make the ISP interface inaccessible! 0x00,8.0 MHz 64 4 [LOW:HIGH:EXTENDED] 8 CLKDIV8 Divide clock by 8 0 CKOUT Oscillator output option 1 SUT1 Select start-up time 0 SUT0 Select start-up time 0 CKSEL3 Select Clock Source 0 CKSEL2 Select Clock Source 0 CKSEL1 Select Clock Source 0 CKSEL0 Select Clock Source 1 55 0x80 0x00 Divide clock by 8 internally; [CKDIV8=0] 0x40 0x00 Clock output on PORTD1; [CKOUT=0] 0x3F 0x00 Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms; [CKSEL=0000 SUT=00] 0x3F 0x10 Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms; [CKSEL=0000 SUT=01] 0x3F 0x20 Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms; [CKSEL=0000 SUT=10] 0x3F 0x02 Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms; [CKSEL=0010 SUT=00] 0x3F 0x12 Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms; [CKSEL=0010 SUT=01] 0x3F 0x22 Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms; [CKSEL=0010 SUT=10]; default value 0x3F 0x08 Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms; [CKSEL=1000 SUT=00] 0x3F 0x18 Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms; [CKSEL=1000 SUT=01] 0x3F 0x28 Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms; [CKSEL=1000 SUT=10] 0x3F 0x38 Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms; [CKSEL=1000 SUT=11] 0x3F 0x09 Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms; [CKSEL=1001 SUT=00] 0x3F 0x19 Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms; [CKSEL=1001 SUT=01] 0x3F 0x29 Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms; [CKSEL=1001 SUT=10] 0x3F 0x39 Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms; [CKSEL=1001 SUT=11] 0x3F 0x0A Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms; [CKSEL=1010 SUT=00] 0x3F 0x1A Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms; [CKSEL=1010 SUT=01] 0x3F 0x2A Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms; [CKSEL=1010 SUT=10] 0x3F 0x3A Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms; [CKSEL=1010 SUT=11] 0x3F 0x0B Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms; [CKSEL=1011 SUT=00] 0x3F 0x1B Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms; [CKSEL=1011 SUT=01] 0x3F 0x2B Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms; [CKSEL=1011 SUT=10] 0x3F 0x3B Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms; [CKSEL=1011 SUT=11] 0x3F 0x0C Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms; [CKSEL=1100 SUT=00] 0x3F 0x1C Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms; [CKSEL=1100 SUT=01] 0x3F 0x2C Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms; [CKSEL=1100 SUT=10] 0x3F 0x3C Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms; [CKSEL=1100 SUT=11] 0x3F 0x0D Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms; [CKSEL=1101 SUT=00] 0x3F 0x1D Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms; [CKSEL=1101 SUT=01] 0x3F 0x2D Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms; [CKSEL=1101 SUT=10] 0x3F 0x3D Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms; [CKSEL=1101 SUT=11] 0x3F 0x0E Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms; [CKSEL=1110 SUT=00] 0x3F 0x1E Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms; [CKSEL=1110 SUT=01] 0x3F 0x2E Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms; [CKSEL=1110 SUT=10] 0x3F 0x3E Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms; [CKSEL=1110 SUT=11] 0x3F 0x0F Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms; [CKSEL=1111 SUT=00] 0x3F 0x1F Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms; [CKSEL=1111 SUT=01] 0x3F 0x2F Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms; [CKSEL=1111 SUT=10] 0x3F 0x3F Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms; [CKSEL=1111 SUT=11] 0x3F 0x03 PLL clock /4; PLL input: Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 1K CK/14 CK + 0 ms; [CKSEL=0011 SUT=00] 0x3F 0x13 PLL clock /4; PLL input: Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4.1 ms; [CKSEL=0011 SUT=01] 0x3F 0x23 PLL clock /4; PLL input: Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 1K CK/14 CK + 65 ms; [CKSEL=0011 SUT=10] 0x3F 0x33 PLL clock /4; PLL input: Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms; [CKSEL=0011 SUT=11] 0x3F 0x01 PLL clock /4; PLL input: Ext. Clock; Start-up time PWRDWN/RESET: 6K CK/14 CK + 0 ms; [CKSEL=0001 SUT=00] 0x3F 0x11 PLL clock /4; PLL input: Ext. Clock; Start-up time PWRDWN/RESET: 6K CK/14 CK + 4 ms; [CKSEL=0001 SUT=01] 0x3F 0x21 PLL clock /4; PLL input: Ext. Clock; Start-up time PWRDWN/RESET: 6K CK/14 CK + 64 ms; [CKSEL=0001 SUT=10] 0x3F 0x05 PLL clock /4; PLL input: Ext. Crystal Osc.; Start-up time PWRDWN/RESET: 1K CK/14 CK + 0 ms; [CKSEL=0101 SUT=00] 0x3F 0x15 PLL clock /4; PLL input: Ext. Crystal Osc.; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4 ms; [CKSEL=0101 SUT=01] 0x3F 0x25 PLL clock /4; PLL input: Ext. Crystal Osc.; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4 ms; [CKSEL=0101 SUT=10] 0x3F 0x35 PLL clock /4; PLL input: Ext. Crystal Osc.; Start-up time PWRDWN/RESET: 16K CK/14 CK + 64 ms; [CKSEL=0101 SUT=11] 0x3F 0x04 Ext. Crystal Osc.; PLL input: Ext. Crystal Osc.; Start-up time PWRDWN/RESET: 1K CK/14 CK + 0 ms; [CKSEL=0100 SUT=00] 0x3F 0x14 Ext. Crystal Osc.; PLL input: Ext. Crystal Osc.; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4 ms; [CKSEL=0100 SUT=01] 0x3F 0x24 Ext. Crystal Osc.; PLL input: Ext. Crystal Osc.; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4 ms; [CKSEL=0100 SUT=10] 0x3F 0x34 Ext. Crystal Osc.; PLL input: Ext. Crystal Osc.; Start-up time PWRDWN/RESET: 16K CK/14 CK + 64 ms; [CKSEL=0100 SUT=11] 8 RSTDISBL External Reset Disable 1 DWEN dwbugWIRE Enable 1 SPIEN Enable Serial programming and Data Downloading 0 WDTON Watchdog timer always on 1 EESAVE EEPROM memory is preserved through chip erase 1 BOOTSZ1 Select Boot Size 0 BOOTSZ0 Select Boot Size 0 BOOTRST Select Reset Vector 1 13 0x80 0x00 Reset Disabled (Enable PC6 as i/o pin); [RSTDISBL=0] 0x40 0x00 Debug Wire enable; [DWEN=0] 0x20 0x00 Serial program downloading (SPI) enabled; [SPIEN=0] 0x10 0x00 Watch-dog Timer always on; [WDTON=0] 0x08 0x00 Preserve EEPROM memory through the Chip Erase cycle; [EESAVE=0] 0x07 0x07 Brown-out detection disabled; [BODLEVEL=111] 0x07 0x06 Brown-out detection level at VCC=4.5 V; [BODLEVEL=110] 0x07 0x05 Brown-out detection level at VCC=2.7 V; [BODLEVEL=101] 0x07 0x04 Brown-out detection level at VCC=4.3 V; [BODLEVEL=100] 0x07 0x03 Brown-out detection level at VCC=4.4 V; [BODLEVEL=011] 0x07 0x02 Brown-out detection level at VCC=4.2 V; [BODLEVEL=010] 0x07 0x01 Brown-out detection level at VCC=2.8 V; [BODLEVEL=001] 0x07 0x00 Brown-out detection level at VCC=2.6 V; [BODLEVEL=000] 4 BODLEVEL2 Brown out detector trigger level 1 BODLEVEL1 Brown-out Detector trigger level 1 BODLEVEL0 Brown-out Detector trigger level 1 TA0SEL (Reserved to factory tests) 1 9 0x10 0x00 PSCOUT Reset Value; [PSCRV=1] 0x80 0x00 PSC2 Reset Behavior; [PSC2RB=0] 0x40 0x00 PSC1 Reset Behavior; [PSC1RB=0] 0x20 0x00 PSC0 Reset Behavior; [PSC0RB=0] 0x06 0x06 Boot Flash section size=128 words Boot start address=$0F80; [BOOTSZ=11] 0x06 0x04 Boot Flash section size=256 words Boot start address=$0F00; [BOOTSZ=10] 0x06 0x02 Boot Flash section size=512 words Boot start address=$0E00; [BOOTSZ=01] 0x06 0x00 Boot Flash section size=1024 words Boot start address=$0C00; [BOOTSZ=00] ; default value 0x01 0x00 Boot Reset vector Enabled (default address=$0000); [BOOTRST=0] [PORTB:PORTC:PORTD:BOOT_LOAD:EUSART:ANALOG_COMPARATOR:DA_CONVERTER:CPU:PORTE:TIMER_COUNTER_0:TIMER_COUNTER_1:AD_CONVERTER:USART:SPI:WATCHDOG:EXTERNAL_INTERRUPT:EEPROM:PSC0:PSC1:PSC2] [PORTB:DDRB:PINB] io_port.bmp AVRSimIOPort.SimIOPort PORTB Port B Data Register $05 $25 io_port.bmp N PORTB7 Port B Data Register bit 7 RW 0 PORTB6 Port B Data Register bit 6 RW 0 PORTB5 Port B Data Register bit 5 RW 0 PORTB4 Port B Data Register bit 4 RW 0 PORTB3 Port B Data Register bit 3 RW 0 PORTB2 Port B Data Register bit 2 RW 0 PORTB1 Port B Data Register bit 1 RW 0 PORTB0 Port B Data Register bit 0 RW 0 DDRB Port B Data Direction Register $04 $24 io_flag.bmp N DDB7 Port B Data Direction Register bit 7 RW 0 DDB6 Port B Data Direction Register bit 6 RW 0 DDB5 Port B Data Direction Register bit 5 RW 0 DDB4 Port B Data Direction Register bit 4 RW 0 DDB3 Port B Data Direction Register bit 3 RW 0 DDB2 Port B Data Direction Register bit 2 RW 0 DDB1 Port B Data Direction Register bit 1 RW 0 DDB0 Port B Data Direction Register bit 0 RW 0 PINB Port B Input Pins The Port B Input Pins address - PINB - is not a register, and this address enables access to the physical value on each Port B pin. When reading PORTB, the Port B Data Latch is read, and when reading PINB, the logical values present on the pins are read. $03 $23 io_port.bmp N PINB7 Port B Input Pins bit 7 R 0 PINB6 Port B Input Pins bit 6 R 0 PINB5 Port B Input Pins bit 5 R 0 PINB4 Port B Input Pins bit 4 R 0 PINB3 Port B Input Pins bit 3 R 0 PINB2 Port B Input Pins bit 2 R 0 PINB1 Port B Input Pins bit 1 R 0 PINB0 Port B Input Pins bit 0 R 0 [PORTC:DDRC:PINC] io_port.bmp AVRSimIOPort.SimIOPort PORTC Port C Data Register $08 $28 io_port.bmp N PORTC7 Port C Data Register bit 7 RW 0 PORTC6 Port C Data Register bit 6 RW 0 PORTC5 Port C Data Register bit 5 RW 0 PORTC4 Port C Data Register bit 4 RW 0 PORTC3 Port C Data Register bit 3 RW 0 PORTC2 Port C Data Register bit 2 RW 0 PORTC1 Port C Data Register bit 1 RW 0 PORTC0 Port C Data Register bit 0 RW 0 DDRC Port C Data Direction Register $07 $27 io_flag.bmp N DDC7 Port C Data Direction Register bit 7 RW 0 DDC6 Port C Data Direction Register bit 6 RW 0 DDC5 Port C Data Direction Register bit 5 RW 0 DDC4 Port C Data Direction Register bit 4 RW 0 DDC3 Port C Data Direction Register bit 3 RW 0 DDC2 Port C Data Direction Register bit 2 RW 0 DDC1 Port C Data Direction Register bit 1 RW 0 DDC0 Port C Data Direction Register bit 0 RW 0 PINC Port C Input Pins The Port C Input Pins address - PINC - is not a register, and this address enables access to the physical value on each Port C pin. When reading PORTC, the Port C Data Latch is read, and when reading PINC, the logical values present on the pins are read. $06 $26 io_port.bmp N PINC7 Port C Input Pins bit 7 R 0 PINC6 Port C Input Pins bit 6 R 0 PINC5 Port C Input Pins bit 5 R 0 PINC4 Port C Input Pins bit 4 R 0 PINC3 Port C Input Pins bit 3 R 0 PINC2 Port C Input Pins bit 2 R 0 PINC1 Port C Input Pins bit 1 R 0 PINC0 Port C Input Pins bit 0 R 0 [PORTD:DDRD:PIND] io_port.bmp AVRSimIOPort.SimIOPort PORTD Port D Data Register $0B $2B io_port.bmp N PORTD7 Port D Data Register bit 7 RW 0 PORTD6 Port D Data Register bit 6 RW 0 PORTD5 Port D Data Register bit 5 RW 0 PORTD4 Port D Data Register bit 4 RW 0 PORTD3 Port D Data Register bit 3 RW 0 PORTD2 Port D Data Register bit 2 RW 0 PORTD1 Port D Data Register bit 1 RW 0 PORTD0 Port D Data Register bit 0 RW 0 DDRD Port D Data Direction Register $0A $2A io_flag.bmp N DDD7 Port D Data Direction Register bit 7 RW 0 DDD6 Port D Data Direction Register bit 6 RW 0 DDD5 Port D Data Direction Register bit 5 RW 0 DDD4 Port D Data Direction Register bit 4 RW 0 DDD3 Port D Data Direction Register bit 3 RW 0 DDD2 Port D Data Direction Register bit 2 RW 0 DDD1 Port D Data Direction Register bit 1 RW 0 DDD0 Port D Data Direction Register bit 0 RW 0 PIND Port D Input Pins The Port D Input Pins address - PIND - is not a register, and this address enables access to the physical value on each Port D pin. When reading PORTD, the Port D Data Latch is read, and when reading PIND, the logical values present on the pins are read. $09 $29 io_port.bmp N PIND7 Port D Input Pins bit 7 R 0 PIND6 Port D Input Pins bit 6 R 0 PIND5 Port D Input Pins bit 5 R 0 PIND4 Port D Input Pins bit 4 R 0 PIND3 Port D Input Pins bit 3 R 0 PIND2 Port D Input Pins bit 2 R 0 PIND1 Port D Input Pins bit 1 R 0 PIND0 Port D Input Pins bit 0 R 0 [SPMCSR] io_cpu.bmp AVRSimIOSPM.SimIOSPM The Boot Loader Support provides a real Read While Write self-programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program. The Boot Loader program can use any available data interface and associated proto-col to read code and write (program) that code into the Flash memory, or read the code from the program memory. The program code within the Boot Loader section has the capability to write into the entire Flash, including the Boot Loader Memory. The Boot Loader can thus even modify itself, and it can also erase itself from the code if the feature is not needed anymore. The size of the Boot Loader Memory is configurable with fuses and the Boot Loader has two separate sets of Boot Lock Bits which can be set independently. This gives the user a unique flexibility to select different levels of protection. Boot Loader Features: Read While Write self-programming. Flexibl Boot Memory size. High security (separate Boot Lock bits for a flexible protection). Separate fuse to select reset vector Optimized page (1) size. Code efficient algorithm Efficient read-modify-write suppor SPMCSR SPMCR Store Program Memory Control Register The Store Program Memory Control Register contains the control bits needed to control the Boot Loader operations. $37 $57 io_flag.bmp Y SPMIE SPM Interrupt Enable When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN bit in the SPMCR register is cleared. RW 0 RWWSB ASB Read While Write Section Busy When a self-programming (page erase or page write) operation to the RWW section is initiated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a self-programming operation is completed. Alternatively the RWWSB bit will auto-matically be cleared if a page load operation is initiated. R 0 RWWSRE ASRE Read While Write section read enable When programming (page erase or page write) to the RWW section, the RWW section is blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW section, the user software must wait until the programming is completed (SPMEN will be cleared). Then, if the RWWSRE bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles re-enables the RWW section. The RWW section cannot be re-enabled while Flash is busy with a page erase or a page write (SPMEN is set). If the RWWSRE bit is written while the Flash is being loaded, the Flash load operation will abort and the data loaded will be lo RW 0 BLBSET Boot Lock Bit Set If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles sets Boot Lock bits, according to the data in R0. The data in R1 and the address in the Z pointer are ignored. The BLBSET bit will automatically be cleared upon completion of the lock bit set, or if no SPM instruction is executed within four clock cycles. An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCR register, will read either the Lock-bits or the Fuse bits (depending on Z0 in the Z pointer) into the destination register. See “Reading the Fuse and Lock Bits from Software” on page 235 for details RW 0 PGWRT Page Write If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPM instruction is exe-cuted within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed. RW 0 PGERS Page Erase If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page erase. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a page erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed. RW 0 SPMEN Store Program Memory Enable This bit enables the SPM instruction for the next four clock cycles. If written to one together with either RWWSRE, BLB-SET, PGWRT or PGERS, the following SPM instruction will have a special meaning, see description above. If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z pointer. The LSB of the Z pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During page erase and page write, the SPMEN bit remain high until the operation is completed. Writing any other combination than “10001”, "01001", "00101", "00011" or "00001" in the lower five bits will have no effec RW 0 [EUDR:EUCSRA:EUCSRB:EUCSRC:MUBRRH:MUBRRL] [MUBRRH:MUBRRL] io_com.bmp EUDR EUSART I/O Data Register NA 0xCE io_com.bmp N EUDR7 EUSART I/O Data Register bit 7 RW 0 EUDR6 EUSART I/O Data Register bit 6 RW 0 EUDR5 EUSART I/O Data Register bit 5 RW 0 EUDR4 EUSART I/O Data Register bit 4 RW 0 EUDR3 EUSART I/O Data Register bit 3 RW 0 EUDR2 EUSART I/O Data Register bit 2 RW 0 EUDR1 EUSART I/O Data Register bit 1 RW 0 EUDR0 EUSART I/O Data Register bit 0 RW 0 EUCSRA EUSART Control and Status Register A NA 0xC8 io_flag.bmp Y UTxS3 EUSART Control and Status Register A Bit 7 . RW 0 UTxS2 EUSART Control and Status Register A Bit 6 RW 0 UTxS1 EUSART Control and Status Register A Bit 5 RW 1 UTxS0 EUSART Control and Status Register A Bit 4 RW 1 URxS3 EUSART Control and Status Register A Bit 3 RW 0 URxS2 EUSART Control and Status Register A Bit 2 RW 0 URxS1 EUSART Control and Status Register A Bit 1 RW 1 URxS0 EUSART Control and Status Register A Bit 0 RW 1 EUCSRB EUSART Control Register B NA 0xC9 io_flag.bmp Y EUSART EUSART Enable Bit RW 0 EUSBS EUSBS Enable Bit RW 0 EMCH Manchester Mode Bit RW 0 BODR Order Bit RW 0 EUCSRC EUSART Status Register C NA 0xCA io_flag.bmp Y FEM Frame Error Manchester Bit R 0 F1617 F1617 Bit R 0 STP1 Stop Bit 1 R 0 STP0 Stop Bit 0 R 0 MUBRRH Manchester Receiver Baud Rate Register High Byte NA 0xCD io_com.bmp Y MUBRR15 Manchester Receiver Baud Rate Register Bit 15 RW 0 MUBRR14 Manchester Receiver Baud Rate Register Bit 14 RW 0 MUBRR13 Manchester Receiver Baud Rate Register Bit 13 RW 0 MUBRR12 Manchester Receiver Baud Rate Register Bit 12 RW 0 MUBRR11 Manchester Receiver Baud Rate Register Bit 11 RW 0 MUBRR10 Manchester Receiver Baud Rate Register Bit 10 RW 0 MUBRR9 Manchester Receiver Baud Rate Register Bit 9 RW 0 MUBRR8 Manchester Receiver Baud Rate Register Bit 8 RW 0 MUBRRL Manchester Receiver Baud Rate Register Low Byte NA 0xCC io_com.bmp Y MUBRR7 Manchester Receiver Baud Rate Register Bit 7 RW 0 MUBRR6 Manchester Receiver Baud Rate Register Bit 6 RW 0 MUBRR5 Manchester Receiver Baud Rate Register Bit 5 RW 0 MUBRR4 Manchester Receiver Baud Rate Register Bit 4 RW 0 MUBRR3 Manchester Receiver Baud Rate Register Bit 3 RW 0 MUBRR2 Manchester Receiver Baud Rate Register Bit 2 RW 0 MUBRR1 Manchester Receiver Baud Rate Register Bit 1 RW 0 MUBRR0 Manchester Receiver Baud Rate Register Bit 0 RW 0 [AC0CON:AC1CON:AC2CON] io_analo.bmp AlgComp_14 AC0CON Analog Comparator 0 Control Register NA $AD io_flag.bmp Y AC0EN Analog Comparator 0 Enable Bit RW 0 AC0IE Analog Comparator 0 Interrupt Enable Bit RW 0 AC0IS1 Analog Comparator 0 Interrupt Select Bit RW 0 AC0IS0 Analog Comparator 0 Interrupt Select Bit RW 0 AC0M2 Analog Comparator 0 Multiplexer Register RW 0 AC0M1 Analog Comparator 0 Multiplexer Regsiter RW 0 AC0M0 Analog Comparator 0 Multiplexer Register RW 0 AC1CON Analog Comparator 1 Control Register NA $AE io_flag.bmp Y AC1EN Analog Comparator 1 Enable Bit RW 0 AC1IE Analog Comparator 1 Interrupt Enable Bit RW 0 AC1IS1 Analog Comparator 1 Interrupt Select Bit RW 0 AC1IS0 Analog Comparator 1 Interrupt Select Bit RW 0 AC1ICE Analog Comparator 1 Interrupt Capture Enable Bit RW 0 AC1M2 Analog Comparator 1 Multiplexer Register RW 0 AC1M1 Analog Comparator 1 Multiplexer Regsiter RW 0 AC1M0 Analog Comparator 1 Multiplexer Register RW 0 AC2CON Analog Comparator 2 Control Register NA $AF io_flag.bmp Y AC2EN Analog Comparator 2 Enable Bit RW 0 AC2IE Analog Comparator 2 Interrupt Enable Bit RW 0 AC2IS1 Analog Comparator 2 Interrupt Select Bit RW 0 AC2IS0 Analog Comparator 2 Interrupt Select Bit RW 0 AC2M2 Analog Comparator 2 Multiplexer Register RW 0 AC2M1 Analog Comparator 2 Multiplexer Regsiter RW 0 AC2M0 Analog Comparator 2 Multiplexer Register RW 0 ACSR Analog Comparator Status Register io_flag.bmp Y ACCKDIV Analog Comparator Clock Divider RW 0 AC2IF Analog Comparator 2 Interrupt Flag Bit RW 0 AC1IF Analog Comparator 1 Interrupt Flag Bit RW 0 AC0IF Analog Comparator 0 Interrupt Flag Bit RW 0 AC2O Analog Comparator 2 Output Bit RW 0 AC1O Analog Comparator 1 Output Bit RW 0 AC0O Analog Comparator 0 Output Bit RW 0 [DACH:DACL:DACON] ((IF DACON.DALA = 0) LINK [DACH(1:0):DACL(7:0)]); (IF DACON.DALA = 1) LINK [DACH(7:0):DACL(7:6)]); io_analo.bmp Digital to Analog Converter DACH DAC Data Register High Byte NA $AC io_analo.bmp Y DACH7 DAC Data Register High Byte Bit 7 RW 0 DACH6 DAC Data Register High Byte Bit 6 RW 0 DACH5 DAC Data Register High Byte Bit 5 RW 0 DACH4 DAC Data Register High Byte Bit 4 RW 0 DACH3 DAC Data Register High Byte Bit 3 RW 0 DACH2 DAC Data Register High Byte Bit 2 RW 0 DACH1 DAC Data Register High Byte Bit 1 RW 0 DACH0 DAC Data Register High Byte Bit 0 RW 0 DACL DAC Data Register Low Byte NA $AB io_flag.bmp Y DACL7 DAC Data Register Low Byte Bit 7 RW 0 DACL6 DAC Data Register Low Byte Bit 6 RW 0 DACL5 DAC Data Register Low Byte Bit 5 RW 0 DACL4 DAC Data Register Low Byte Bit 4 RW 0 DACL3 DAC Data Register Low Byte Bit 3 RW 0 DACL2 DAC Data Register Low Byte Bit 2 RW 0 DACL1 DAC Data Register Low Byte Bit 1 RW 0 DACL0 DAC Data Register Low Byte Bit 0 RW 0 DACON DAC Control Register NA $AA io_analo.bmp N DAATE DAC Auto Trigger Enable Bit RW 0 DATS2 DAC Trigger Selection Bit 2 RW 0 DATS1 DAC Trigger Selection Bit 1 RW 0 DATS0 DAC Trigger Selection Bit 0 RW 0 DALA DAC Left Adjust RW 0 DAOE DAC Output Enable Bit RW 0 DAEN DAC Enable Bit RW 0 [SREG:SPH:SPL:MCUCR:MCUSR:OSCCAL:CLKPR:SMCR:GPIOR3:GPIOR2:GPIOR1:GPIOR0:PLLCSR] [SPH:SPL] io_cpu.bmp SREG Status Register $3F $5F io_sreg.bmp Y I Global Interrupt Enable The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable bit is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. RW 0 T Bit Copy Storage The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction. RW 0 H Half Carry Flag The half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed information. RW 0 S Sign Bit The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruc-tion Set Description for detailed information. RW 0 V Two's Complement Overflow Flag The two’s complement overflow flag V supports two’s complement arithmetics. See the Instruction Set Description for detailed information. RW 0 N Negative Flag The negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information. RW 0 Z Zero Flag The zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information. RW 0 C Carry Flag The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software. RW 0 SPH Stack Pointer High The general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the AT90S4414/8515 supports up to 64 kB external SRAM, all 16-bits are used. The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or return from interrupt R $3E $5E io_sph.bmp N SP15 Stack pointer bit 15 RW 0 SP14 Stack pointer bit 14 RW 0 SP13 Stack pointer bit 13 RW 0 SP12 Stack pointer bit 12 RW 0 SP11 Stack pointer bit 11 RW 0 SP10 Stack pointer bit 10 RW 0 SP9 Stack pointer bit 9 RW 0 SP8 Stack pointer bit 8 RW 0 SPL Stack Pointer Low The general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the AT90S4414/8515 supports up to 64 kB external SRAM, all 16-bits are used. The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or return from interrupt $3D $5D io_sph.bmp N SP7 Stack pointer bit 7 RW 0 SP6 Stack pointer bit 6 RW 0 SP5 Stack pointer bit 5 RW 0 SP4 Stack pointer bit 4 RW 0 SP3 Stack pointer bit 3 RW 0 SP2 Stack pointer bit 2 RW 0 SP1 Stack pointer bit 1 RW 0 SP0 Stack pointer bit 0 RW 0 MCUCR MCU Control Register The MCU Control Register contains control bits for general MCU functions. $35 $55 io_flag.bmp Y SPIPS SPI Pin Select RW 0 PUD Pull-up disable When this bit is written to one,the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn registers are configured to enable the pull-ups ({DDxn,PORTxn}=0b01). RW 0 IVSEL Interrupt Vector Select When the IVSEL bit is cleared (zero),the interrupt vectors are placed at the start of the Flash memory.When this bit is set (one),the interrupt vectors are moved to the beginning of the Boot Loader section of the flash.The actual address of the start of the boot flash section is determined by the BOOTSZ fuses. RW 0 IVCE Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit.IVCE is cleared by hardware four cycles after it is written or when IVSEL is written.Setting the IVCE bit will disable interrupts. RW 0 MCUSR MCU Status Register The MCU Status Register provides information on which reset source caused an MCU reset. $34 $54 io_flag.bmp Y WDRF Watchdog Reset Flag This bit is set if a watchdog reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag. R/W 0 BORF Brown-out Reset Flag This bit is set if a brown-out reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag. R/W 0 EXTRF External Reset Flag This bit is set if an external reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag. R/W 0 PORF Power-on reset flag This bit is set if a power-on reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the reset flags to identify a reset condition, the user should read and then reset the MCUCSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags. R/W 0 OSCCAL Oscillator Calibration Value Writing the calibration byte to this address will trim the internal oscillator to remove process variations from the oscillator frequency. This is done automatically during chip reset. When OSCCAL is zero, the lowest available frequency is chosen. Writing non-zero values to this register will increase the frequency of the internal oscillator. Writing $FF to the register gives the highest available frequency. The calibrated oscillator is used to time EEPROM and Flash access. If EEPROM or Flash is written, do not calibrate to more than 10% above the nominal frequency. Otherwise, the EEPROM or Flash write may fail. Note that the Oscillator is intended for calibration to 1.0 MHz, 2.0 MHz, 4.0 MHz, or 8.0MHz. Tuning to other values is not guaranteed, as indicated in Table 14 NA $66 io_cpu.bmp N CAL6 Oscillator Calibration Value Bit6 R/W 0 CAL5 Oscillator Calibration Value Bit5 R/W 0 CAL4 Oscillator Calibration Value Bit4 R/W 0 CAL3 Oscillator Calibration Value Bit3 R/W 0 CAL2 Oscillator Calibration Value Bit2 R/W 0 CAL1 Oscillator Calibration Value Bit1 R/W 0 CAL0 Oscillator Calibration Value Bit0 R/W 0 CLKPR NA $61 io_cpu.bmp Y CLKPCE CLKPS3 CLKPS2 CLKPS1 CLKPS0 SMCR Sleep Mode Control Register The Sleep Mode Control Register contains control bits for power management. $33 $53 io_cpu.bmp Y SM2 Sleep Mode Select bit 2 These bits select between the five available sleep modes. RW 0 SM1 Sleep Mode Select bit 1 These bits select between the five available sleep modes. RW 0 SM0 Sleep Mode Select bit 0 These bits select between the five available sleep modes. RW 0 SE Sleep Enable The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed.To RW 0 GPIOR3 General Purpose IO Register 3 $1B $3B io_cpu.bmp Y GPIOR37 General Purpose IO Register 3 bit 7 RW 0 GPIOR36 General Purpose IO Register 3 bit 6 RW 0 GPIOR35 General Purpose IO Register 3 bit 5 RW 0 GPIOR34 General Purpose IO Register 3 bit 4 RW 0 GPIOR33 General Purpose IO Register 3 bit 3 RW 0 GPIOR32 General Purpose IO Register 3 bit 2 RW 0 GPIOR31 General Purpose IO Register 3 bit 1 RW 0 GPIOR30 General Purpose IO Register 3 bit 0 RW 0 GPIOR2 General Purpose IO Register 2 $1A $3A io_cpu.bmp Y GPIOR27 General Purpose IO Register 2 bit 7 RW 0 GPIOR26 General Purpose IO Register 2 bit 6 RW 0 GPIOR25 General Purpose IO Register 2 bit 5 RW 0 GPIOR24 General Purpose IO Register 2 bit 4 RW 0 GPIOR23 General Purpose IO Register 2 bit 3 RW 0 GPIOR22 General Purpose IO Register 2 bit 2 RW 0 GPIOR21 General Purpose IO Register 2 bit 1 RW 0 GPIOR20 General Purpose IO Register 2 bit 0 RW 0 GPIOR1 General Purpose IO Register 1 $19 $39 io_cpu.bmp Y GPIOR17 General Purpose IO Register 1 bit 7 RW 0 GPIOR16 General Purpose IO Register 1 bit 6 RW 0 GPIOR15 General Purpose IO Register 1 bit 5 RW 0 GPIOR14 General Purpose IO Register 1 bit 4 RW 0 GPIOR13 General Purpose IO Register 1 bit 3 RW 0 GPIOR12 General Purpose IO Register 1 bit 2 RW 0 GPIOR11 General Purpose IO Register 1 bit 1 RW 0 GPIOR10 General Purpose IO Register 1 bit 0 RW 0 GPIOR0 General Purpose IO Register 0 $1E $3E io_cpu.bmp Y GPIOR07 General Purpose IO Register 0 bit 7 RW 0 GPIOR06 General Purpose IO Register 0 bit 6 RW 0 GPIOR05 General Purpose IO Register 0 bit 5 RW 0 GPIOR04 General Purpose IO Register 0 bit 4 RW 0 GPIOR03 General Purpose IO Register 0 bit 3 RW 0 GPIOR02 General Purpose IO Register 0 bit 2 RW 0 GPIOR01 General Purpose IO Register 0 bit 1 RW 0 GPIOR00 General Purpose IO Register 0 bit 0 RW 0 PLLCSR PLL Control And Status Register $29 $49 io_sreg.bmp Y PLLF PLL Factor The PLLF bit is used to select the division factor of the PLL. RW 0 PLLE PLL Enable RW 0 PLOCK PLL Lock Detector R 0 [PORTE:DDRE:PINE] io_port.bmp AVRSimIOPort.SimIOPort PORTE Port E Data Register $0E $2E io_port.bmp N PORTE2 RW 0 PORTE1 RW 0 PORTE0 RW 0 DDRE Port E Data Direction Register $0D $2D io_flag.bmp N DDE2 RW 0 DDE1 RW 0 DDE0 RW 0 PINE Port E Input Pins $0C $2C io_port.bmp N PINE2 R 0 PINE1 R 0 PINE0 R 0 [TIMSK0:TIFR0:TCCR0A:TCCR0B:TCNT0:OCR0A:OCR0B:GTCCR] io_timer.bmp At8pwm0_12 TIMSK0 Timer/Counter0 Interrupt Mask Register NA $6E io_flag.bmp Y OCIE0B Timer/Counter0 Output Compare Match B Interrupt Enable RW 0 OCIE0A Timer/Counter0 Output Compare Match A Interrupt Enable RW 0 TOIE0 Timer/Counter0 Overflow Interrupt Enable RW 0 TIFR0 Timer/Counter0 Interrupt Flag register $15 $35 io_flag.bmp Y OCF0B Timer/Counter0 Output Compare Flag 0B RW 0 OCF0A Timer/Counter0 Output Compare Flag 0A RW 0 TOV0 Timer/Counter0 Overflow Flag RW 0 TCCR0A Timer/Counter Control Register A $24 $44 io_flag.bmp Y COM0A1 Compare Output Mode, Phase Correct PWM Mode RW 0 COM0A0 Compare Output Mode, Phase Correct PWM Mode RW 0 COM0B1 Compare Output Mode, Fast PWm W 0 COM0B0 Compare Output Mode, Fast PWm RW 0 WGM01 Waveform Generation Mode RW 0 WGM00 Waveform Generation Mode RW 0 TCCR0B Timer/Counter Control Register B $25 $45 io_flag.bmp Y FOC0A Force Output Compare A W 0 FOC0B Force Output Compare B W 0 WGM02 RW 0 CS02 Clock Select RW 0 CS01 Clock Select RW 0 CS00 Clock Select RW 0 TCNT0 Timer/Counter0 The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT0 register blocks (removes) the compare match on the following timer clock. Modifying the counter (TCNT0) while the counter is running, introduces a risk of missing a compare match between TCNT0 the OCR0 register. $26 $46 io_timer.bmp N TCNT0_7 RW 0 TCNT0_6 RW 0 TCNT0_5 RW 0 TCNT0_4 RW 0 TCNT0_3 RW 0 TCNT0_2 RW 0 TCNT0_1 RW 0 TCNT0_0 RW 0 OCR0A Timer/Counter0 Output Compare Register The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC0 pin. $27 $47 io_timer.bmp N OCR0_7 RW 0 OCR0_6 RW 0 OCR0_5 RW 0 OCR0_4 RW 0 OCR0_3 RW 0 OCR0_2 RW 0 OCR0_1 RW 0 OCR0_0 RW 0 OCR0B Timer/Counter0 Output Compare Register The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC0 pin. $28 $48 io_timer.bmp N OCR0_7 RW 0 OCR0_6 RW 0 OCR0_5 RW 0 OCR0_4 RW 0 OCR0_3 RW 0 OCR0_2 RW 0 OCR0_1 RW 0 OCR0_0 RW 0 GTCCR General Timer/Counter Control Register $23 $43 io_flag.bmp Y TSM Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSR2 and PSR10 bits is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSR2 and PSR10 bits are cleared by hardware, and the Timer/Counters start counting simultaneousl RW 0 ICPSEL1 Timer1 Input Capture Selection Bit RW 0 PSR10 Prescaler Reset Timer/Counter1 and Timer/Counter0 When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. RW 0 [TIMSK1:TIFR1:TCCR1A:TCCR1B:TCCR1C:TCNT1H:TCNT1L:OCR1AH:OCR1AL:OCR1BH:OCR1BL:ICR1H:ICR1L:GTCCR] [TCNT1H:TCNT1L];[OCR1AH:OCR1AL];[OCR1BH:OCR1BL];[ICR1H:ICR1L] io_timer.bmp t16pwm1_12.xml TIMSK1 Timer/Counter Interrupt Mask Register NA $6F io_flag.bmp Y ICIE1 Timer/Counter1 Input Capture Interrupt Enable When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on pin 31, ICP, i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR. RW 0 OCIE1B Timer/Counter1 Output CompareB Match Interrupt Enable When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter1 occurs, i.e., when the OCF1B bit is set in the Timer/Counter Interrupt Flag Register - TIFR. R 0 OCIE1A Timer/Counter1 Output CompareA Match Interrupt Enable When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a CompareA match in Timer/Counter1 occurs, i.e., when the OCF1A bit is set in the Timer/Counter Interrupt Flag Register - TIFR. RW 0 TOIE1 Timer/Counter1 Overflow Interrupt Enable When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $006) is executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR. RW 0 TIFR1 Timer/Counter Interrupt Flag register $16 $36 io_flag.bmp Y ICF1 Input Capture Flag 1 The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to the input capture register - ICR1. ICF1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF1 is cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable), and ICF1 are set (one), the Timer/Counter1 Capture Interrupt is executed. RW 0 OCF1B Output Compare Flag 1B The OCF1B bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1B - Output Compare Register 1B. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1B (Timer/Counter1 Compare match InterruptB Enable), and the OCF1B are set (one), the Timer/Counter1 Compare B match Interrupt is executed. RW 0 OCF1A Output Compare Flag 1A The OCF1A bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare match InterruptA Enable), and the OCF1A are set (one), the Timer/Counter1 Compare A match Interrupt is executed. RW 0 TOV1 Timer/Counter1 Overflow Flag The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the cor-responding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter1 changes counting direction at $0000. RW 0 TCCR1A Timer/Counter1 Control Register A NA $80 io_flag.bmp Y COM1A1 Compare Output Mode 1A, bit 1 The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA. This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10. RW 0 COM1A0 Comparet Ouput Mode 1A, bit 0 The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA. This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10. RW 0 COM1B1 Compare Output Mode 1B, bit 1 The COM1B1 and COM1B0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin. RW 0 COM1B0 Compare Output Mode 1B, bit 0 The COM1B1 and COM1B0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin. RW 0 WGM11 Waveform Generation Mode Combined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table. RW 0 WGM10 Waveform Generation Mode Combined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table. RW 0 TCCR1B Timer/Counter1 Control Register B NA $81 io_flag.bmp Y ICNC1 Input Capture 1 Noise Canceler When the ICNC1 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the ICP - input capture pin - as specified. When the ICNC1 bit is set (one), four successive samples are measures on the ICP - input capture pin, and all samples must be high/low according to the input capture trigger specification in the ICES1 bit. The actual sampling frequency is XTAL clock frequency. RW 0 ICES1 Input Capture 1 Edge Select While the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the falling edge of the input capture pin - ICP. While the ICES1 bit is set (one), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the rising edge of the input capture pin - ICP. RW 0 WGM13 Waveform Generation Mode Combined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table. RW 0 WGM12 Waveform Generation Mode Combined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table. RW 0 CS12 Prescaler source of Timer/Counter 1 Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge. RW 0 CS11 Prescaler source of Timer/Counter 1 Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge. RW 0 CS10 Prescaler source of Timer/Counter 1 Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge. RW 0 TCCR1C Timer/Counter1 Control Register C NA $82 io_flag.bmp Y FOC1A RW 0 FOC1B RW 0 TCNT1H Timer/Counter1 High Byte This 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR1A, OCR1B and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt rou NA $85 io_timer.bmp N TCNT1H7 Timer/Counter1 High Byte bit 7 RW 0 TCNT1H6 Timer/Counter1 High Byte bit 6 RW 0 TCNT1H5 Timer/Counter1 High Byte bit 5 RW 0 TCNT1H4 Timer/Counter1 High Byte bit 4 RW 0 TCNT1H3 Timer/Counter1 High Byte bit 3 RW 0 TCNT1H2 Timer/Counter1 High Byte bit 2 RW 0 TCNT1H1 Timer/Counter1 High Byte bit 1 RW 0 TCNT1H0 Timer/Counter1 High Byte bit 0 RW 0 TCNT1L Timer/Counter1 Low Byte This 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR1A, OCR1B and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interru NA $84 io_timer.bmp N TCNT1L7 Timer/Counter1 Low Byte bit 7 RW 0 TCNT1L6 Timer/Counter1 Low Byte bit 6 RW 0 TCNT1L5 Timer/Counter1 Low Byte bit 5 RW 0 TCNT1L4 Timer/Counter1 Low Byte bit 4 RW 0 TCNT1L3 Timer/Counter1 Low Byte bit 3 RW 0 TCNT1L2 Timer/Counter1 Low Byte bit 2 RW 0 TCNT1L1 Timer/Counter1 Low Byte bit 1 RW 0 TCNT1L0 Timer/Counter1 Low Byte bit 0 RW 0 OCR1AH Timer/Counter1 Outbut Compare Register High Byte The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interru NA $89 io_timer.bmp N OCR1AH7 Timer/Counter1 Outbut Compare Register High Byte bit 7 RW 0 OCR1AH6 Timer/Counter1 Outbut Compare Register High Byte bit 6 RW 0 OCR1AH5 Timer/Counter1 Outbut Compare Register High Byte bit 5 RW 0 OCR1AH4 Timer/Counter1 Outbut Compare Register High Byte bit 4 RW 0 OCR1AH3 Timer/Counter1 Outbut Compare Register High Byte bit 3 RW 0 OCR1AH2 Timer/Counter1 Outbut Compare Register High Byte bit 2 RW 0 OCR1AH1 Timer/Counter1 Outbut Compare Register High Byte bit 1 RW 0 OCR1AH0 Timer/Counter1 Outbut Compare Register High Byte bit 0 RW 0 OCR1AL Timer/Counter1 Outbut Compare Register Low Byte The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interru NA $88 io_timer.bmp N OCR1AL7 Timer/Counter1 Outbut Compare Register Low Byte Bit 7 RW 0 OCR1AL6 Timer/Counter1 Outbut Compare Register Low Byte Bit 6 RW 0 OCR1AL5 Timer/Counter1 Outbut Compare Register Low Byte Bit 5 RW 0 OCR1AL4 Timer/Counter1 Outbut Compare Register Low Byte Bit 4 RW 0 OCR1AL3 Timer/Counter1 Outbut Compare Register Low Byte Bit 3 RW 0 OCR1AL2 Timer/Counter1 Outbut Compare Register Low Byte Bit 2 RW 0 OCR1AL1 Timer/Counter1 Outbut Compare Register Low Byte Bit 1 RW 0 OCR1AL0 Timer/Counter1 Outbut Compare Register Low Byte Bit 0 RW 0 OCR1BH Timer/Counter1 Output Compare Register High Byte The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt ro NA $8B io_timer.bmp N OCR1BH7 Timer/Counter1 Output Compare Register High Byte bit 7 RW 0 OCR1BH6 Timer/Counter1 Output Compare Register High Byte bit 6 RW 0 OCR1BH5 Timer/Counter1 Output Compare Register High Byte bit 5 RW 0 OCR1BH4 Timer/Counter1 Output Compare Register High Byte bit 4 RW 0 OCR1BH3 Timer/Counter1 Output Compare Register High Byte bit 3 RW 0 OCR1BH2 Timer/Counter1 Output Compare Register High Byte bit 2 RW 0 OCR1BH1 Timer/Counter1 Output Compare Register High Byte bit 1 RW 0 OCR1BH0 Timer/Counter1 Output Compare Register High Byte bit 0 RW 0 OCR1BL Timer/Counter1 Output Compare Register Low Byte The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt rout NA $8A io_timer.bmp N OCR1BL7 Timer/Counter1 Output Compare Register Low Byte bit 7 R 0 OCR1BL6 Timer/Counter1 Output Compare Register Low Byte bit 6 RW 0 OCR1BL5 Timer/Counter1 Output Compare Register Low Byte bit 5 RW 0 OCR1BL4 Timer/Counter1 Output Compare Register Low Byte bit 4 RW 0 OCR1BL3 Timer/Counter1 Output Compare Register Low Byte bit 3 RW 0 OCR1BL2 Timer/Counter1 Output Compare Register Low Byte bit 2 RW 0 OCR1BL1 Timer/Counter1 Output Compare Register Low Byte bit 1 RW 0 OCR1BL0 Timer/Counter1 Output Compare Register Low Byte bit 0 RW 0 ICR1H Timer/Counter1 Input Capture Register High Byte The input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES1) of the signal at the input capture pin -ICP - is detected, the current value of the Timer/Counter1 is transferred to the Input Capture Register - ICR1. At the same time, the input capture flag - ICF1 - is set (one). Since the Input Capture Register - ICR1 - is a 16-bit register, a temporary register TEMP is used when ICR1 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR1L, the data is sent to the CPU and the data of the high byte ICR1H is placed in the TEMP register. When the CPU reads the data in the high byte ICR1H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR1L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT1, OCR1A and OCR1B. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt NA $87 io_timer.bmp N ICR1H7 Timer/Counter1 Input Capture Register High Byte bit 7 RW 0 ICR1H6 Timer/Counter1 Input Capture Register High Byte bit 6 R 0 ICR1H5 Timer/Counter1 Input Capture Register High Byte bit 5 R 0 ICR1H4 Timer/Counter1 Input Capture Register High Byte bit 4 R 0 ICR1H3 Timer/Counter1 Input Capture Register High Byte bit 3 R 0 ICR1H2 Timer/Counter1 Input Capture Register High Byte bit 2 R 0 ICR1H1 Timer/Counter1 Input Capture Register High Byte bit 1 R 0 ICR1H0 Timer/Counter1 Input Capture Register High Byte bit 0 R 0 ICR1L Timer/Counter1 Input Capture Register Low Byte The input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES1) of the signal at the input capture pin -ICP - is detected, the current value of the Timer/Counter1 is transferred to the Input Capture Register - ICR1. At the same time, the input capture flag - ICF1 - is set (one). Since the Input Capture Register - ICR1 - is a 16-bit register, a temporary register TEMP is used when ICR1 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR1L, the data is sent to the CPU and the data of the high byte ICR1H is placed in the TEMP register. When the CPU reads the data in the high byte ICR1H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR1L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT1, OCR1A and OCR1B. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within inter NA $86 io_timer.bmp N ICR1L7 Timer/Counter1 Input Capture Register Low Byte bit 7 R 0 ICR1L6 Timer/Counter1 Input Capture Register Low Byte bit 6 R 0 ICR1L5 Timer/Counter1 Input Capture Register Low Byte bit 5 R 0 ICR1L4 Timer/Counter1 Input Capture Register Low Byte bit 4 R 0 ICR1L3 Timer/Counter1 Input Capture Register Low Byte bit 3 R 0 ICR1L2 Timer/Counter1 Input Capture Register Low Byte bit 2 R 0 ICR1L1 Timer/Counter1 Input Capture Register Low Byte bit 1 R 0 ICR1L0 Timer/Counter1 Input Capture Register Low Byte bit 0 R 0 GTCCR General Timer/Counter Control Register $23 $43 io_flag.bmp Y TSM Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSR2 and PSR10 bits is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSR2 and PSR10 bits are cleared by hardware, and the Timer/Counters start counting simultaneous RW 0 PSRSYNC Prescaler Reset Timer/Counter1 and Timer/Counter0 When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. RW 0 [ADMUX:ADCSRA:ADCH:ADCL:ADCSRB:DIDR0:DIDR1] ((IF ADMUX.ADLAR = 1) LINK [ADCH(1:0):ADCL(7:0)]); (IF ADMUX.ADLAR = 0) LINK [ADCH(7:0):ADCL(7:6)]); io_analo.bmp AD Converter Feature list: 10-bit Resolution. 0.5 LSB Integral Non-Linearity. +-2 LSB Absolute Accuracy. TBD - 260 µs Conversion Time. Up to TBD kSPS at maximum resolution. 8 Multiplexed Single Ended Input Channels. 7 Differential input channels (TQFP package only). 2 Differential input channels with optional gain of 10x and 200x (TQFP package only). Optional left adjustment for ADC result readout. 0 - VCC ADC Input Voltage Range. Selectable 2.56 V ADC reference voltage. Free Running or Single Conversion Mode. Interrupt on ADC Conversion Complete. Sleep Mode Noi ADMUX The ADC multiplexer Selection Register These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin. NA $7C io_analo.bmp N REFS1 Reference Selection Bit 1 These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin. RW 0 REFS0 Reference Selection Bit 0 These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin. RW 0 ADLAR Left Adjust Result The ADLAR bit affects the presentation of the ADC conversion result in the ADC data register. If ADLAR is cleared, the result is right adjusted. If ADLAR is set, the result is left adjusted. Changing the ADLAR bit will affect the ADC data register immediately, regardless of any ongoing conversions. For a complete description of this bit, see “The ADC Data Register -ADCL and ADCH” on page 198. RW 0 MUX3 Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). RW 0 MUX2 Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). RW 0 MUX1 Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). RW 0 MUX0 Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). RW 0 ADCSRA The ADC Control and Status register NA $7A io_flag.bmp Y ADEN ADC Enable Writing a logical ‘1’ to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion. RW 0 ADSC ADC Start Conversion In Single Conversion Mode, a logical ‘1’ must be written to this bit to start each conversion. In Free Running Mode, a logical ‘1’ must be written to this bit to start the first conversion. The first time ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, an extended conversion will result. This extended conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. When a dummy conversion precedes a real conversion, ADSC will stay high until the real conversion completes. Writing a 0 to this bit has no effect RW 0 ADATE ADC Auto Trigger Enable When this bit is written to one,Auto Triggering of the ADC is enabled.The ADC will start a conversion on a positive edge of the selected trigger signal.The trigger source is selected by setting the ADC Trigger Select bits,ADTS in ADCSRB. RW 0 ADIF ADC Interrupt Flag This bit is set (one) when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set (one). ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a read-modify-write on ADCSR, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used. RW 0 ADIE ADC Interrupt Enable When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Complete Interrupt is activated. RW 0 ADPS2 ADC Prescaler Select Bits These bits determine the division factor between the XTAL frequency and the input clock to the ADC. RW 0 ADPS1 ADC Prescaler Select Bits These bits determine the division factor between the XTAL frequency and the input clock to the ADC. RW 0 ADPS0 ADC Prescaler Select Bits These bits determine the division factor between the XTAL frequency and the input clock to the ADC. RW 0 ADCH ADC Data Register High Byte When an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. The selected channel is differential if MUX4..0 are between ‘01000’ and ‘11101’, otherwise the selected channel is single ended. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8 bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUX4..0 bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adj NA $79 io_analo.bmp N ADCH7 ADC Data Register High Byte Bit 7 RW 0 ADCH6 ADC Data Register High Byte Bit 6 RW 0 ADCH5 ADC Data Register High Byte Bit 5 RW 0 ADCH4 ADC Data Register High Byte Bit 4 RW 0 ADCH3 ADC Data Register High Byte Bit 3 RW 0 ADCH2 ADC Data Register High Byte Bit 2 RW 0 ADCH1 ADC Data Register High Byte Bit 1 RW 0 ADCH0 ADC Data Register High Byte Bit 0 RW 0 ADCL ADC Data Register Low Byte When an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. The selected channel is differential if MUX4..0 are between ‘01000’ and ‘11101’, otherwise the selected channel is single ended. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8 bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUX4..0 bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right a NA $78 io_analo.bmp N ADCL7 ADC Data Register Low Byte Bit 7 RW 0 ADCL6 ADC Data Register Low Byte Bit 6 RW 0 ADCL5 ADC Data Register Low Byte Bit 5 RW 0 ADCL4 ADC Data Register Low Byte Bit 4 RW 0 ADCL3 ADC Data Register Low Byte Bit 3 RW 0 ADCL2 ADC Data Register Low Byte Bit 2 RW 0 ADCL1 ADC Data Register Low Byte Bit 1 RW 0 ADCL0 ADC Data Register Low Byte Bit 0 RW 0 ADCSRB ADC Control and Status Register B NA $7B io_analo.bmp N ADHSM ADC High Speed Mode RW 0 ADASCR ADC on Amplified Channel Start Conversion Request Bit RW 0 ADTS3 ADC Auto Trigger Source 3 RW 0 ADTS2 ADC Auto Trigger Source 2 RW 0 ADTS1 ADC Auto Trigger Source 1 RW 0 ADTS0 ADC Auto Trigger Source 0 RW 0 DIDR0 Digital Input Disable Register 0 NA $7E io_analo.bmp N ADC7D ADC7 Digital input Disable When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. ADC6D ADC6 Digital input Disable When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. ADC5D ADC5 Digital input Disable When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. ADC4D ADC4 Digital input Disable When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. ADC3D ADC3 Digital input Disable When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. ADC2D ADC2 Digital input Disable When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. ADC1D ADC1 Digital input Disable When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. ADC0D ADC0 Digital input Disable When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. NA $7F ACMP0D AMP0PD AMP0ND ADC10D ADC9D ADC8D [UDR:UCSRA:UCSRB:UCSRC:UBRRH:UBRRL] io_com.bmp Usart_00 UDR USART I/O Data Register NA 0xC6 io_com.bmp N UDR7 USART I/O Data Register bit 7 RW 0 UDR6 USART I/O Data Register bit 6 RW 0 UDR5 USART I/O Data Register bit 5 RW 0 UDR4 USART I/O Data Register bit 4 RW 0 UDR3 USART I/O Data Register bit 3 RW 0 UDR2 USART I/O Data Register bit 2 RW 0 UDR1 USART I/O Data Register bit 1 RW 0 UDR0 USART I/O Data Register bit 0 RW 0 UCSRA USART Control and Status register A NA 0xC0 io_flag.bmp Y RXC USART Receive Complete R 0 TXC USART Transmitt Complete RW 0 UDRE USART Data Register Empty R 1 FE Framing Error R 0 DOR Data Overrun R 0 UPE USART Parity Error R 0 U2X Double USART Transmission Bit RW 0 MPCM Multi-processor Communication Mode RW 0 UCSRB USART Control an Status register B NA 0xC1 io_flag.bmp Y RXCIE RX Complete Interrupt Enable RW 0 TXCIE TX Complete Interrupt Enable RW 0 UDRIE USART Data Register Empty Interrupt Enable RW 0 RXEN Receiver Enable RW 0 TXEN Transmitter Enable RW 0 UCSZ2 Character Size RW 0 RXB8 Receive Data Bit 8 R 0 TXB8 Transmit Data Bit 8 RW 0 UCSRC USART Control an Status register C NA 0xC2 io_flag.bmp Y UMSEL0 USART Mode Select RW 0 UPM1 Parity Mode Bit 1 RW 0 UPM0 Parity Mode Bit 0 RW 0 USBS Stop Bit Select RW 0 UCSZ1 Character Size Bit 1 RW 1 UCSZ0 Character Size Bit 0 RW 1 UCPOL Clock Polarity RW 0 UBRRH USART Baud Rate Register High Byte NA 0xC5 io_com.bmp Y UBRR11 USART Baud Rate Register Bit 11 RW 0 UBRR10 USART Baud Rate Register Bit 10 RW 0 UBRR9 USART Baud Rate Register Bit 9 RW 0 UBRR8 USART Baud Rate Register Bit 8 RW 0 UBRRL USART Baud Rate Register Low Byte NA 0xC4 io_com.bmp Y UBRR7 USART Baud Rate Register bit 7 RW 0 UBRR6 USART Baud Rate Register bit 6 RW 0 UBRR5 USART Baud Rate Register bit 5 RW 0 UBRR4 USART Baud Rate Register bit 4 RW 0 UBRR3 USART Baud Rate Register bit 3 RW 0 UBRR2 USART Baud Rate Register bit 2 RW 0 UBRR1 USART Baud Rate Register bit 1 RW 0 UBRR0 USART Baud Rate Register bit 0 RW 0 [SPDR:SPSR:SPCR] io_com.bmp The Serial Peripheral Interface(SPI) allows high-speed synchronous data transfer between the AT90S4414/8515 and peripheral devices or between several AVR devices. The AT90S4414/8515 SPI features include the following: • Full-duplex, 3-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Four Programmable Bit Rates • End of Transmission Interrupt Flag • Write Collision Flag Protection • Wakeup from Idle Mode (Slave Mode Only) SPCR SPI Control Register $2C $4C io_flag.bmp Y SPIE SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR register is set and the global interrupts are enabled. RW 0 SPE SPI Enable When the SPE bit is set (one), the SPI is enabled. This bit must be set to enable any SPI operations. RW 0 DORD Data Order When the DORD bit is set (one), the LSB of the data word is transmitted first. When the DORD bit is cleared (zero), the MSB of the data word is transmitted first. RW 0 MSTR Master/Slave Select This bit selects Master SPI mode when set (one), and Slave SPI mode when cleared (zero). If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI master mode. RW 0 CPOL Clock polarity When this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is low when idle. Refer to Figure 36 and Figure 37 for additional information. RW 0 CPHA Clock Phase Refer to Figure 36 or Figure 37 for the functionality of this bit. RW 0 SPR1 SPI Clock Rate Select 1 These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave. RW 0 SPR0 SPI Clock Rate Select 0 These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave. RW 0 SPSR SPI Status Register $2D $4D io_flag.bmp Y SPIF SPI Interrupt Flag When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is generated if SPIE in SPCR is set (one) and global interrupts are enabled. If SS is an input and is driven low when the SPI is in master mode, this will also set the SPIF flag. SPIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the SPI status register when SPIF is set (one), then accessing the SPI Data Register (SPDR). R 0 WCOL Write Collision Flag The WCOL bit is set if the SPI data register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Register when WCOL is set (one), and then accessing the SPI Data Register. R 0 SPI2X Double SPI Speed Bit When this bit is written logic one the SPI speed (SCK Frequency)will be doubled when the SPI is in master mode .This means that the minimum SCK period will be 2 CPU clock periods.When the SPI is configured as Slave,the SPI is only guaranteed to work at f osc /4orlower. The SPI interface on the ATmega162 is also used for program memory and EEPROM downloading or uploading. RW 0 SPDR SPI Data Register The SPI Data Register is a read/write register used for data transfer between the register file and the SPI Shift register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read. $2E $4E io_com.bmp N SPDR7 SPI Data Register bit 7 RW X SPDR6 SPI Data Register bit 6 RW X SPDR5 SPI Data Register bit 5 RW X SPDR4 SPI Data Register bit 4 RW X SPDR3 SPI Data Register bit 3 RW X SPDR2 SPI Data Register bit 2 RW X SPDR1 SPI Data Register bit 1 R 0 SPDR0 SPI Data Register bit 0 R 0 [WDTCSR] io_watch.bmp WDTCSR Watchdog Timer Control Register NA $60 io_flag.bmp Y WDIF Watchdog Timeout Interrupt Flag RW 0 WDIE Watchdog Timeout Interrupt Enable RW 0 WDP3 Watchdog Timer Prescaler Bit 3 RW 0 WDCE Watchdog Change Enable RW 0 WDE Watch Dog Enable When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog RW 0 WDP2 Watch Dog Timer Prescaler bit 2 RW 0 WDP1 Watch Dog Timer Prescaler bit 1 RW 0 WDP0 Watch Dog Timer Prescaler bit 0 RW 0 [EICRA:EIMSK:EIFR] io_ext.bmp The external interrupts are triggered by the INT7:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT7:0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The external inter-rupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the Exter-nal Interrupt Control Registers - EICRA (INT3:0) and EICRB (INT7:4). When the external interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT7:4 requires the presence of an I/O clock, described in “Clock Systems and their Distribution” on page 29. Low level interrupts and the edge interrupt on INT3:0 are detected asynchronously. This implies that these inter-rupts can be used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode. Note that if a level triggered interrupt is used for wake-up from Power Down Mode, the changed level must be held for some time to wake up the MCU. This makes the MCU less sensitive to noise. The changed level is sampled twice by the watchdog oscillator clock. The period of the watchdog oscillator is 1 µs (nominal) at 5.0V and 25°C. The frequency of the watchdog oscillator is voltage dependent as shown in the Electrical Characteristics section. The MCU will wake up if the input has the required level during this sampling or if it is held until the end of the start-up time. The start-up time is defined by the SUT fuses as described in “Clock Systems and their Distribution” on page 29. If the level is sampled twice by the watchdog oscillator clock but disappears before the end of the start-up time, the MCU will still wake up, but no interrupt will be generated. The required level must be held long enough for the MCU to complete the wake up to trigger the level interrupt EICRA External Interrupt Control Register A This Register can not be reached in ATmega103 compatibility mode, but the initial value defines INT3:0 as low level inter-rupts,as in ATmega103. • Bits 7..0 - ISC31, ISC30 - ISC00, ISC00: External Interrupt 3-0 Sense Control bits The External Interrupts 3 - 0 are activated by the external pins INT3:0 if the SREG I-flag and the corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that activate the interrupts are defined in Table 47. Edges on INT3..INT0 are registered asynchronously. Pulses on INT3:0 pins wider than the minimum pulse width given in Table 48 will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an interrupt request as long as the pin is held low. When changing the ISCn bit, an interrupt can occur. Therefore, it is recommended to first disable INTn by clearing its Interrupt Enable bit in the EIMSK register. Then, the ISCn bit can be changed. Finally, the INTn interrupt flag should be cleared by writing a logical one to its Interrupt Flag bit (INTFn) in the EIFR register before the interrupt is re-enable NA $69 io_flag.bmp Y ISC31 External Interrupt Sense Control Bit RW 0 ISC30 External Interrupt Sense Control Bit RW 0 ISC21 External Interrupt Sense Control Bit RW 0 ISC20 External Interrupt Sense Control Bit RW 0 ISC11 External Interrupt Sense Control Bit RW 0 ISC10 External Interrupt Sense Control Bit RW 0 ISC01 External Interrupt Sense Control Bit RW 0 ISC00 External Interrupt Sense Control Bit RW 0 EIMSK External Interrupt Mask Register $1D $3D io_flag.bmp Y INT3 External Interrupt Request 3 Enable RW 0 INT2 External Interrupt Request 2 Enable RW 0 INT1 External Interrupt Request 1 Enable RW 0 INT0 External Interrupt Request 0 Enable RW 0 EIFR External Interrupt Flag Register $1C $3C io_flag.bmp Y INTF3 External Interrupt Flag 3 RW 0 INTF2 External Interrupt Flag 2 RW 0 INTF1 External Interrupt Flag 1 RW 0 INTF0 External Interrupt Flag 0 RW 0 [EEARH:EEARL:EEDR:EECR] [EEARH:EEARL] io_cpu.bmp EEPROM Read/Write Access. The EEPROM access registers are accessible in the I/O space. The write access time for the EEPROM is given in Table 1. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page 19. for details on how to avoid problems in these situations.In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When theEEPROM is written, the CPU is halted for two clock cycles before the next instruction is execute EEARH EEPROM Read/Write Access High Byte Bits 11..0 - EEAR11..0: EEPROM Address The EEPROM Address Registers - EEARH and EEARL specify the EEPROM address in the 4K bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 4096. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed. $22 $42 io_cpu.bmp N EEAR11 EEPROM Read/Write Access Bit 11 RW 0 EEAR10 EEPROM Read/Write Access Bit 10 RW 0 EEAR9 EEPROM Read/Write Access Bit 9 RW 0 EEAR8 EEPROM Read/Write Access Bit 8 RW 0 EEARL EEPROM Read/Write Access Low Byte Bits 11..0 - EEAR11..0: EEPROM Address The EEPROM Address Registers - EEARH and EEARL specify the EEPROM address in the 4K bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 4096. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed. $21 $41 io_cpu.bmp N EEARL7 EEPROM Read/Write Access Bit 7 RW 0 EEARL6 EEPROM Read/Write Access Bit 6 RW 0 EEARL5 EEPROM Read/Write Access Bit 5 RW 0 EEARL4 EEPROM Read/Write Access Bit 4 RW 0 EEARL3 EEPROM Read/Write Access Bit 3 RW 0 EEARL2 EEPROM Read/Write Access Bit 2 RW 0 EEARL1 EEPROM Read/Write Access Bit 1 RW 0 EEARL0 EEPROM Read/Write Access Bit 0 RW 0 EEDR EEPROM Data Register For the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR. $20 $40 io_cpu.bmp N EEDR7 EEPROM Data Register bit 7 RW 0 EEDR6 EEPROM Data Register bit 6 RW 0 EEDR5 EEPROM Data Register bit 5 RW 0 EEDR4 EEPROM Data Register bit 4 RW 0 EEDR3 EEPROM Data Register bit 3 RW 0 EEDR2 EEPROM Data Register bit 2 RW 0 EEDR1 EEPROM Data Register bit 1 RW 0 EEDR0 EEPROM Data Register bit 0 RW 0 EECR EEPROM Control Register $1F $3F io_flag.bmp Y EEPM1 EEPROM Programming Mode Bit 1 The EEPROM Programming mode bit setting defines which programming action will be triggered when writing EEWE. RW X EEPM0 EEPROM Programming Mode Bit 0 The EEPROM Programming mode bit setting defines which programming action will be triggered when writing EEWE. RW X EERIE EEPROM Ready Interrupt Enable EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared. RW 0 EEMWE EEPROM Master Write Enable The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is written to one, writing EEWE to one within 4 clock cycles will write data to the EEPROM at the selected address. If EEMWE is zero, writing EEWE to one will have no effect. When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure. RW 0 EEWE EEPROM Write Enable The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential): 1. Wait until EEWE becomes zero. 2. Wait until SPMEN in SPMCR becomes zero. 3. Write new EEPROM address to EEAR (optional). 4. Write new EEPROM data to EEDR (optional). 5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR. 6. Within four clock cycles after setting EEMWE, write a logical one to EEWE. The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a boot loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See “Boot Loader Support - Read While Write self-programming” on page 228 for details about boot programming. Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR regis-ter will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the 4 last steps to avoid these problems. When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruc-tion is executed RW X EERE EEPROM Read Enable The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR register. The calibrated oscillator is used to time the EEPROM accesses. Table 1 lists the typical programming time for EEPROM access from the CPU RW 0 [PICR0H:PICR0L:PFRC0B:PFRC0A:PCTL0:PCNF0:OCR0RBH:OCR0RBL:OCR0SBH:OCR0SBL:OCR0RAH:OCR0RAL:OCR0SAH:OCR0SAL:PSOC0:PIM0:PIFR0] io_com.bmp Power Stage Controller PICR0H PSC 0 Input Capture Register High NA 0xDF register.bmp N PCST0 PSC 0 Capture Software Trigger Bit RW 0 PICR0_11 R 0 PICR0_10 R 0 PICR0_9 R 0 PICR0_8 R 0 PICR0L PSC 0 Input Capture Register Low NA 0xDE register.bmp N PICR0_7 R 0 PICR0_6 R 0 PICR0_5 R 0 PICR0_4 R 0 PICR0_3 R 0 PICR0_2 R 0 PICR0_1 R 0 PICR0_0 R 0 PFRC0B PSC 0 Input B Control NA 0xDD register.bmp Y PCAE0B PSC 0 Capture Enable Input Part B RW 0 PISEL0B PSC 0 Input Select for Part B RW 0 PELEV0B PSC 0 Edge Level Selector on Input Part B RW 0 PFLTE0B PSC 0 Filter Enable on Input Part B RW 0 PRFM0B3 PSC 0 Retrigger and Fault Mode for Part B RW 0 PRFM0B2 PSC 0 Retrigger and Fault Mode for Part B RW 0 PRFM0B1 PSC 0 Retrigger and Fault Mode for Part B RW 0 PRFM0B0 PSC 0 Retrigger and Fault Mode for Part B RW 0 PFRC0A PSC 0 Input A Control NA 0xDC register.bmp Y PCAE0A PSC 0 Capture Enable Input Part A RW 0 PISEL0A PSC 0 Input Select for Part A RW 0 PELEV0A PSC 0 Edge Level Selector on Input Part A RW 0 PFLTE0A PSC 0 Filter Enable on Input Part A RW 0 PRFM0A3 PSC 0 Retrigger and Fault Mode for Part A RW 0 PRFM0A2 PSC 0 Retrigger and Fault Mode for Part A RW 0 PRFM0A1 PSC 0 Retrigger and Fault Mode for Part A RW 0 PRFM0A0 PSC 0 Retrigger and Fault Mode for Part A RW 0 PCTL0 PSC 0 Control Register NA 0xDB register.bmp Y PPRE01 PSC 0 Prescaler Select 1 RW 0 PPRE00 PSC 0 Prescaler Select 0 RW 0 PBFM0 PSC 0 Balance Flank Width Modulation RW 0 PAOC0B PSC 0 Asynchronous Output Control B RW 0 PAOC0A PSC 0 Asynchronous Output Control A RW 0 PARUN0 PSC0 Auto Run RW 0 PCCYC0 PSC0 Complete Cycle RW 0 PRUN0 PSC 0 Run RW 0 PCNF0 PSC 0 Configuration Register NA 0xDA register.bmp Y PFIFTY0 PSC 0 Fifty RW 0 PALOCK0 PSC 0 Autolock RW 0 PLOCK0 PSC 0 Lock RW 0 PMODE01 PSC 0 Mode RW 0 PMODE00 PSC 0 Mode RW 0 POP0 PSC 0 Output Polarity RW 0 PCLKSEL0 PSC 0 Input Clock Select RW 0 OCR0RBH Output Compare RB Register High NA 0xD9 register.bmp N OCR0RB_05 RW 0 OCR0RB_04 RW 0 OCR0RB_03 RW 0 OCR0RB_02 RW 0 OCR0RB_01 RW 0 OCR0RB_00 RW 0 OCR0RB_9 RW 0 OCR0RB_8 RW 0 OCR0RBL Output Compare RB Register Low NA 0xD8 register.bmp N OCR0RB_7 RW 0 OCR0RB_6 RW 0 OCR0RB_5 RW 0 OCR0RB_4 RW 0 OCR0RB_3 RW 0 OCR0RB_2 RW 0 OCR0RB_1 RW 0 OCR0RB_0 RW 0 OCR0SBH Output Compare SB Register High NA 0xD7 register.bmp N OCR0SB_01 RW 0 OCR0SB_00 RW 0 OCR0SB_9 RW 0 OCR0SB_8 RW 0 OCR0SBL Output Compare SB Register Low NA 0xD6 register.bmp N OCR0SB_7 RW 0 OCR0SB_6 RW 0 OCR0SB_5 RW 0 OCR0SB_4 RW 0 OCR0SB_3 RW 0 OCR0SB_2 RW 0 OCR0SB_1 RW 0 OCR0SB_0 RW 0 OCR0RAH Output Compare RA Register High NA 0xD5 register.bmp N OCR0RA_01 RW 0 OCR0RA_00 RW 0 OCR0RA_9 RW 0 OCR0RA_8 RW 0 OCR0RAL Output Compare RA Register Low NA 0xD4 register.bmp N OCR0RA_7 RW 0 OCR0RA_6 RW 0 OCR0RA_5 RW 0 OCR0RA_4 RW 0 OCR0RA_3 RW 0 OCR0RA_2 RW 0 OCR0RA_1 RW 0 OCR0RA_0 RW 0 OCR0SAH Output Compare SA Register High NA 0xD3 register.bmp N OCR0SA_01 RW 0 OCR0SA_00 RW 0 OCR0SA_9 RW 0 OCR0SA_8 RW 0 OCR0SAL Output Compare SA Register Low NA 0xD2 register.bmp N OCR0SA_7 RW 0 OCR0SA_6 RW 0 OCR0SA_5 RW 0 OCR0SA_4 RW 0 OCR0SA_3 RW 0 OCR0SA_2 RW 0 OCR0SA_1 RW 0 OCR0SA_0 RW 0 PSOC0 PSC0 Synchro and Output Configuration NA 0xD0 register.bmp Y PSYNC01 Synchronization Out for ADC Selection RW 0 PSYNC00 Synchronization Out for ADC Selection RW 0 POEN0B PSCOUT01 Output Enable RW 0 POEN0A PSCOUT00 Output Enable RW 0 PIM0 PSC0 Interrupt Mask Register NA $A1 register.bmp Y PSEIE0 PSC 0 Synchro Error Interrupt Enable RW 0 PEVE0B External Event B Interrupt Enable RW 0 PEVE0A External Event A Interrupt Enable RW 0 PEOPE0 End of Cycle Interrupt Enable RW 0 PIFR0 PSC0 Interrupt Flag Register NA $A0 register.bmp Y POAC0B PSC 0 Output A Activity R 0 POAC0A PSC 0 Output A Activity R 0 PSEI0 PSC 0 Synchro Error Interrupt RW 0 PEV0B External Event B Interrupt RW 0 PEV0A External Event A Interrupt RW 0 PRN01 Ramp Number R 0 PRN00 Ramp Number R 0 PEOP0 End of PSC0 Interrupt RW 0 [PICR1H:PICR1L:PFRC1B:PFRC1A:PCTL1:PCNF1:OCR1RBH:OCR1RBL:OCR1SBH:OCR1SBL:OCR1RAH:OCR1RAL:OCR1SAH:OCR1SAL:PSOC1:PIM1:PIFR1] io_com.bmp Power Stage Controller PICR1H PSC 1 Input Capture Register High NA 0xEF register.bmp N PCST1 PSC 1 Capture Software Trigger Bit RW 0 PICR1_11 R 0 PICR1_10 R 0 PICR1_9 R 0 PICR1_8 R 0 PICR1L PSC 1 Input Capture Register Low NA 0xEE register.bmp N PICR1_7 R 0 PICR1_6 R 0 PICR1_5 R 0 PICR1_4 R 0 PICR1_3 R 0 PICR1_2 R 0 PICR1_1 R 0 PICR1_0 R 0 PFRC1B PSC 1 Input B Control NA 0xED register.bmp Y PCAE1B PSC 1 Capture Enable Input Part B RW 0 PISEL1B PSC 1 Input Select for Part B RW 0 PELEV1B PSC 1 Edge Level Selector on Input Part B RW 0 PFLTE1B PSC 1 Filter Enable on Input Part B RW 0 PRFM1B3 PSC 1 Retrigger and Fault Mode for Part B RW 0 PRFM1B2 PSC 1 Retrigger and Fault Mode for Part B RW 0 PRFM1B1 PSC 1 Retrigger and Fault Mode for Part B RW 0 PRFM1B0 PSC 1 Retrigger and Fault Mode for Part B RW 0 PFRC1A PSC 1 Input B Control NA 0xEC register.bmp Y PCAE1A PSC 1 Capture Enable Input Part A RW 0 PISEL1A PSC 1 Input Select for Part A RW 0 PELEV1A PSC 1 Edge Level Selector on Input Part A RW 0 PFLTE1A PSC 1 Filter Enable on Input Part A RW 0 PRFM1A3 PSC 1 Retrigger and Fault Mode for Part A RW 0 PRFM1A2 PSC 1 Retrigger and Fault Mode for Part A RW 0 PRFM1A1 PSC 1 Retrigger and Fault Mode for Part A RW 0 PRFM1A0 PSC 1 Retrigger and Fault Mode for Part A RW 0 PCTL1 PSC 1 Control Register NA 0xEB register.bmp Y PPRE11 PSC 1 Prescaler Select 1 RW 0 PPRE10 PSC 1 Prescaler Select 0 RW 0 PBFM1 Balance Flank Width Modulation RW 0 PAOC1B PSC 1 Asynchronous Output Control B RW 0 PAOC1A PSC 1 Asynchronous Output Control A RW 0 PARUN1 PSC1 Auto Run RW 0 PCCYC1 PSC1 Complete Cycle RW 0 PRUN1 PSC 1 Run RW 0 PCNF1 PSC 1 Configuration Register NA 0xEA register.bmp Y PFIFTY1 PSC 1 Fifty RW 0 PALOCK1 PSC 1 Autolock RW 0 PLOCK1 PSC 1 Lock RW 0 PMODE11 PSC 1 Mode RW 0 PMODE10 PSC 1 Mode RW 0 POP1 PSC 1 Output Polarity RW 0 PCLKSEL1 PSC 1 Input Clock Select RW 0 OCR1RBH Output Compare RB Register High NA 0xE9 register.bmp N OCR1RB_15 RW 0 OCR1RB_14 RW 0 OCR1RB_13 RW 0 OCR1RB_12 RW 0 OCR1RB_11 RW 0 OCR1RB_10 RW 0 OCR1RB_9 RW 0 OCR1RB_8 RW 0 OCR1RBL Output Compare RB Register Low NA 0xE8 register.bmp N OCR1RB_7 RW 0 OCR1RB_6 RW 0 OCR1RB_5 RW 0 OCR1RB_4 RW 0 OCR1RB_3 RW 0 OCR1RB_2 RW 0 OCR1RB_1 RW 0 OCR1RB_0 RW 0 OCR1SBH Output Compare SB Register High NA 0xE7 register.bmp N OCR1SB_11 RW 0 OCR1SB_10 RW 0 OCR1SB_9 RW 0 OCR1SB_8 RW 0 OCR1SBL Output Compare SB Register Low NA 0xE6 register.bmp N OCR1SB_7 RW 0 OCR1SB_6 RW 0 OCR1SB_5 RW 0 OCR1SB_4 RW 0 OCR1SB_3 RW 0 OCR1SB_2 RW 0 OCR1SB_1 RW 0 OCR1SB_0 RW 0 OCR1RAH Output Compare RA Register High NA 0xE5 register.bmp N OCR1RA_11 RW 0 OCR1RA_10 RW 0 OCR1RA_9 RW 0 OCR1RA_8 RW 0 OCR1RAL Output Compare RA Register Low NA 0xE4 register.bmp N OCR1RA_7 RW 0 OCR1RA_6 RW 0 OCR1RA_5 RW 0 OCR1RA_4 RW 0 OCR1RA_3 RW 0 OCR1RA_2 RW 0 OCR1RA_1 RW 0 OCR1RA_0 RW 0 OCR1SAH Output Compare SA Register High NA 0xE3 register.bmp N OCR1SA_11 RW 0 OCR1SA_10 RW 0 OCR1SA_9 RW 0 OCR1SA_8 RW 0 OCR1SAL Output Compare SA Register Low NA 0xE2 register.bmp N OCR1SA_7 RW 0 OCR1SA_6 RW 0 OCR1SA_5 RW 0 OCR1SA_4 RW 0 OCR1SA_3 RW 0 OCR1SA_2 RW 0 OCR1SA_1 RW 0 OCR1SA_0 RW 0 PSOC1 PSC1 Synchro and Output Configuration NA 0xE0 register.bmp Y PSYNC1_1 Synchronization Out for ADC Selection RW 0 PSYNC1_0 Synchronization Out for ADC Selection RW 0 POEN1B PSCOUT11 Output Enable RW 0 POEN1A PSCOUT10 Output Enable RW 0 PIM1 PSC1 Interrupt Mask Register NA $A3 register.bmp Y PSEIE1 PSC 1 Synchro Error Interrupt Enable RW 0 PEVE1B External Event B Interrupt Enable RW 0 PEVE1A External Event A Interrupt Enable RW 0 PEOPE1 End of Cycle Interrupt Enable RW 0 PIFR1 PSC1 Interrupt Flag Register NA $A2 register.bmp Y POAC1B PSC 1 Output B Activity R 0 POAC1A PSC 1 Output A Activity R 0 PSEI1 PSC 1 Synchro Error Interrupt RW 0 PEV1B External Event B Interrupt RW 0 PEV1A External Event A Interrupt RW 0 PRN11 Ramp Number R 0 PRN10 Ramp Number R 0 PEOP1 End of PSC1 Interrupt RW 0 [PICR2H:PICR2L:PFRC2B:PFRC2A:PCTL2:PCNF2:OCR2RBH:OCR2RBL:OCR2SBH:OCR2SBL:OCR2RAH:OCR2RAL:OCR2SAH:OCR2SAL:POM2:PSOC2:PIM2:PIFR2] io_com.bmp Power Stage Controller PICR2H PSC 2 Input Capture Register High NA 0xFF register.bmp N PCST2 PSC 2 Capture Software Trigger Bit RW 0 PICR2_11 R 0 PICR2_10 R 0 PICR2_9 R 0 PICR2_8 R 0 PICR2L PSC 2 Input Capture Register Low NA 0xFE register.bmp N PICR2_7 R 0 PICR2_6 R 0 PICR2_5 R 0 PICR2_4 R 0 PICR2_3 R 0 PICR2_2 R 0 PICR2_1 R 0 PICR2_0 R 0 PFRC2B PSC 2 Input B Control NA 0xFD register.bmp Y PCAE2B PSC 2 Capture Enable Input Part B RW 0 PISEL2B PSC 2 Input Select for Part B RW 0 PELEV2B PSC 2 Edge Level Selector on Input Part B RW 0 PFLTE2B PSC 2 Filter Enable on Input Part B RW 0 PRFM2B3 PSC 2 Retrigger and Fault Mode for Part B RW 0 PRFM2B2 PSC 2 Retrigger and Fault Mode for Part B RW 0 PRFM2B1 PSC 2 Retrigger and Fault Mode for Part B RW 0 PRFM2B0 PSC 2 Retrigger and Fault Mode for Part B RW 0 PFRC2A PSC 2 Input B Control NA 0xFC register.bmp Y PCAE2A PSC 2 Capture Enable Input Part A RW 0 PISEL2A PSC 2 Input Select for Part A RW 0 PELEV2A PSC 2 Edge Level Selector on Input Part A RW 0 PFLTE2A PSC 2 Filter Enable on Input Part A RW 0 PRFM2A3 PSC 2 Retrigger and Fault Mode for Part A RW 0 PRFM2A2 PSC 2 Retrigger and Fault Mode for Part A RW 0 PRFM2A1 PSC 2 Retrigger and Fault Mode for Part A RW 0 PRFM2A0 PSC 2 Retrigger and Fault Mode for Part A RW 0 PCTL2 PSC 2 Control Register NA 0xFB register.bmp Y PPRE21 PSC 2 Prescaler Select 1 RW 0 PPRE20 PSC 2 Prescaler Select 0 RW 0 PBFM2 Balance Flank Width Modulation RW 0 PAOC2B PSC 2 Asynchronous Output Control B RW 0 PAOC2A PSC 2 Asynchronous Output Control A RW 0 PARUN2 PSC2 Auto Run RW 0 PCCYC2 PSC2 Complete Cycle RW 0 PRUN2 PSC 2 Run RW 0 PCNF2 PSC 2 Configuration Register NA 0xFA register.bmp Y PFIFTY2 PSC 2 Fifty RW 0 PALOCK2 PSC 2 Autolock RW 0 PLOCK2 PSC 2 Lock RW 0 PMODE21 PSC 2 Mode RW 0 PMODE20 PSC 2 Mode RW 0 POP2 PSC 2 Output Polarity RW 0 PCLKSEL2 PSC 2 Input Clock Select RW 0 POME2 PSC 2 Output Matrix Enable RW 0 OCR2RBH Output Compare RB Register High NA 0xF9 register.bmp N OCR2RB_15 RW 0 OCR2RB_14 RW 0 OCR2RB_13 RW 0 OCR2RB_12 RW 0 OCR2RB_11 RW 0 OCR2RB_10 RW 0 OCR2RB_9 RW 0 OCR2RB_8 RW 0 OCR2RBL Output Compare RB Register Low NA 0xF8 register.bmp N OCR2RB_7 RW 0 OCR2RB_6 RW 0 OCR2RB_5 RW 0 OCR2RB_4 RW 0 OCR2RB_3 RW 0 OCR2RB_2 RW 0 OCR2RB_1 RW 0 OCR2RB_0 RW 0 OCR2SBH Output Compare SB Register High NA 0xF7 register.bmp N OCR2SB_11 RW 0 OCR2SB_10 RW 0 OCR2SB_9 RW 0 OCR2SB_8 RW 0 OCR2SBL Output Compare SB Register Low NA 0xF6 register.bmp N OCR2SB_7 RW 0 OCR2SB_6 RW 0 OCR2SB_5 RW 0 OCR2SB_4 RW 0 OCR2SB_3 RW 0 OCR2SB_2 RW 0 OCR2SB_1 RW 0 OCR2SB_0 RW 0 OCR2RAH Output Compare RA Register High NA 0xF5 register.bmp N OCR2RA_11 RW 0 OCR2RA_10 RW 0 OCR2RA_9 RW 0 OCR2RA_8 RW 0 OCR2RAL Output Compare RA Register Low NA 0xF4 register.bmp N OCR2RA_7 RW 0 OCR2RA_6 RW 0 OCR2RA_5 RW 0 OCR2RA_4 RW 0 OCR2RA_3 RW 0 OCR2RA_2 RW 0 OCR2RA_1 RW 0 OCR2RA_0 RW 0 OCR2SAH Output Compare SA Register High NA 0xF3 register.bmp N OCR2SA_11 RW 0 OCR2SA_10 RW 0 OCR2SA_9 RW 0 OCR2SA_8 RW 0 OCR2SAL Output Compare SA Register Low NA 0xF2 register.bmp N OCR2SA_7 RW 0 OCR2SA_6 RW 0 OCR2SA_5 RW 0 OCR2SA_4 RW 0 OCR2SA_3 RW 0 OCR2SA_2 RW 0 OCR2SA_1 RW 0 OCR2SA_0 RW 0 POM2 PSC 2 Output Matrix NA 0xF1 register.bmp Y POMV2B3 Output Matrix Output B Ramp 3 RW 0 POMV2B2 Output Matrix Output B Ramp 2 RW 0 POMV2B1 Output Matrix Output B Ramp 2 RW 0 POMV2B0 Output Matrix Output B Ramp 0 RW 0 POMV2A3 Output Matrix Output A Ramp 3 RW 0 POMV2A2 Output Matrix Output A Ramp 2 RW 0 POMV2A1 Output Matrix Output A Ramp 1 RW 0 POMV2A0 Output Matrix Output A Ramp 0 RW 0 PSOC2 PSC2 Synchro and Output Configuration NA 0xF0 register.bmp Y POS23 PSC 2 Output 23 Select RW 0 POS22 PSC 2 Output 22 Select RW 0 PSYNC2_1 Synchronization Out for ADC Selection RW 0 PSYNC2_0 Synchronization Out for ADC Selection RW 0 POEN2D PSCOUT23 Output Enable RW 0 POEN2B PSCOUT21 Output Enable RW 0 POEN2C PSCOUT22 Output Enable RW 0 POEN2A PSCOUT20 Output Enable RW 0 PIM2 PSC2 Interrupt Mask Register NA $A5 register.bmp Y PSEIE2 PSC 2 Synchro Error Interrupt Enable RW 0 PEVE2B External Event B Interrupt Enable RW 0 PEVE2A External Event A Interrupt Enable RW 0 PEOPE2 End of Cycle Interrupt Enable RW 0 PIFR2 PSC2 Interrupt Flag Register NA $A4 register.bmp Y POAC2B PSC 2 Output A Activity R 0 POAC2A PSC 2 Output A Activity R 0 PSEI2 PSC 2 Synchro Error Interrupt RW 0 PEV2B External Event B Interrupt RW 0 PEV2A External Event A Interrupt RW 0 PRN21 Ramp Number R 0 PRN20 Ramp Number R 0 PEOP2 End of PSC2 Interrupt RW 0 [STK500_2:STK500:SIMULATOR:AVRISPmkII:JTAGICEmkII]2001002532030x53114510x4164100x400x4C0x000x000x000x41450xC10xC20x000x000x0025625644440x0E 0x1E 0x0F 0x1F 0x2E 0x3E 0x2F 0x3F 0x4E 0x5E 0x4F 0x5F 0x6E 0x7E 0x6F 0x7F 0x66 0x76 0x67 0x77 0x6A 0x7A 0x6B 0x7B 0xBE 0xFD 0x00 0x01 0x00 0x00 0x00 0x001000511510151501050x0D25625650x052562560505 0x66 1 1 1 0xFF 0xFF 0xFF 0 1 AVRSimCoreV2.SimCoreV2 AVRSimMemory8bit.SimMemory8bit AVRSimInterrupt.SimInterrupt 0x1a 0 16 AVRSimIOPort.SimIOPort Y AVRSimIOPort.SimIOPort Y AVRSimIOPort.SimIOPort Y AVRSimIOPort.SimIOPort Y AVRSimIOExtInterrupt.SimIOExtInterrupt 0x0A 0x1D 0x01 0x1C 0x01 0x09 0x01 0x49 0x03 AVRSimIOExtInterrupt.SimIOExtInterrupt 0x13 0x1D 0x02 0x1C 0x02 0x09 0x02 0x49 0x0c AVRSimIOExtInterrupt.SimIOExtInterrupt 0x18 0x1D 0x04 0x1C 0x04 0x09 0x04 0x49 0x30 AVRSimIOExtInterrupt.SimIOExtInterrupt 0x1C 0x1D 0x08 0x1C 0x08 0x09 0x08 0x49 0xc0 AvrSimIOtim8pwmsync2.tim8pwmsync2 0x0011 0x0010 0x001B PORTD 3 PORTE 1 PINC 2 AVRSimIOTimert16pwm1.SimIOTimert16pwm1 0x0B 0x0C 0x0D 0x0F 0x09 0x40 0x09 0x10 0x05 0x20 0x05 0x40 0x05 0x80 AVRSimIOSPM.SimIOSPM 0x1F AVRSimIOSpi.SimIOSpi 0x14 0x03 0x02 0x03 0x08 0x03 0x04 0x03 0x04 0x01 AVRSimIOUsart.SimIOUsart 0x15 0x17 0x16 0x0C 0x02 0x0C 0x01 AvrMasterTimer.MasterTimer 128 1 0x19 2048:4096:8192:16384:32768:65536:131072:262144:524288:1048576 AVRSimADC.SimADC 0x12 0xFF 0xff 0xFF 0xFF 0x9383 DebugWire 0xF8,0x7F,0x60,0xFE,0xFF,0x33,0xBD,0xE0 0xF8,0x7F,0x40,0xEE,0xFF,0x33,0xBC,0xE0 0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00 0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00 0x53,0xC2,0xC0,0xDF,0xF7,0x0F,0x00,0x00,0x3F,0xE4,0x00,0x00,0x36,0x37,0x01,0xFC,0x05,0xFC,0x07,0xFC 0x11,0xC2,0xC0,0xD8,0xF7,0x0F,0x00,0x00,0x3F,0xE4,0x00,0x00,0x36,0x33,0x01,0xFC,0x05,0xFC,0x07,0xFC 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 0x00 0X00 0X00 64 4 0x0F80 0x0F80 0x0F00 0x0E00 0x0C00 0xFF 0x2000 0x0000,32 0x0020,64 0x00 0x40 0x00 0x00 0x20 0x00 0xBD,0xF2,0xBD,0xE1,0xBB,0xCF,0xB4,0x00,0xBE,0x01,0xB6,0x01,0xBC,0x00,0xBB,0xBF,0x99,0xF9,0xBB,0xAF 0xB6,0x01,0x11 0x3e 0x3d 0x31 0x00 0x00 0x00 0xF80 0x00 0x52 0 1 2 0 1 2 0x3f