[ADMIN:CORE:INTERRUPT_VECTOR:MEMORY:PACKAGE:POWER:PROGVOLT:FUSE:PROGRAMMING:IO_MODULE:ICE_SETTINGS:LOCKBIT] ATmega103 6MHz 215 RELEASED $1E $97 $01 V2 AVRSimCoreV2.SimCoreV2 [] [movw:break:lpm rd,z:spm] [] 32 $00 $1B $1A $1D $1C $1F $1E 24 $000 RESET External Reset, Power-on Reset and Watchdog Reset $002 INT0 External Interrupt 0 $004 INT1 External Interrupt 1 $006 INT2 External Interrupt 2 $008 INT3 External Interrupt 3 $00A INT4 External Interrupt 4 $00C INT5 External Interrupt 5 $00E INT6 External Interrupt 6 $010 INT7 External Interrupt 7 $012 TIMER2_COMP Timer/Counter2 Compare Match $014 TIMER2_OVF Timer/Counter2 Overflow $016 TIMER1_CAPT Timer/Counter1 Capture Event $018 TIMER1_COMPA Timer/Counter1 Compare Match A $01A TIMER1_COMPB Timer/Counter1 Compare Match B $01C TIMER1_OVF Timer/Counter1 Overflow $01E TIMER0_COMP Timer/Counter0 Compare Match $020 TIMER0_OVF Timer/Counter0 Overflow $022 SPI,STC SPI Serial Transfer Complete $024 UART,RX UART, Rx Complete $026 UART,UDRE UART Data Register Empty $028 UART,TX UART, Tx Complete $02A ADC ADC Conversion Complete $02C EE_READY EEPROM Ready $02E ANALOG_COMP Analog Comparator AVRSimMemory8bit.SimMemory8bit 131072 4096 4000 $60 65536 $1000 $00 $3F NA NA $20 $5F $3F $5F 0x010x020x040x080x100x200x400x80 $3E $5E 0x010x020x040x080x100x200x400x80 $3D $5D 0x010x020x040x080x100x200x400x80 $3C $5C 0x010x020x040x080x100x200x400x80 $3B $5B 0x01 $3A $5A 0x010x020x040x080x100x200x400x80 $39 $59 0x010x020x040x080x100x200x400x80 $38 $58 0x100x200x400x80 $37 $57 0x400x800x010x020x040x080x100x20 $36 $56 0x400x800x010x020x040x080x100x20 $35 $55 0x080x100x200x400x80 $34 $54 0x010x02 $33 $53 0x010x020x040x080x100x200x40 $32 $52 0x010x020x040x080x100x200x400x80 $31 $51 0x010x020x040x080x100x200x400x80 $30 $50 0x010x020x040x08 $2F $4F 0x010x020x100x200x400x80 $2E $4E 0x010x020x040x080x400x80 $2D $4D 0x010x020x040x080x100x200x400x80 $2C $4C 0x010x020x040x080x100x200x400x80 $2B $4B 0x010x020x040x080x100x200x400x80 $2A $4A 0x010x020x040x080x100x200x400x80 $29 $49 0x010x020x040x080x100x200x400x80 $28 $48 0x010x020x040x080x100x200x400x80 $27 $47 0x010x020x040x080x100x200x400x80 $26 $46 0x010x020x040x080x100x200x400x80 $25 $45 0x010x020x040x080x100x200x40 $24 $44 0x010x020x040x080x100x200x400x80 $23 $43 0x010x020x040x080x100x200x400x80 $21 $41 0x010x020x040x080x10 $1F $3F 0x010x020x040x08 $1E $3E 0x010x020x040x080x100x200x400x80 $1D $3D 0x010x020x040x080x100x200x400x80 $1C $3C 0x010x020x040x08 $1B $3B $ff 0x010x020x040x080x100x200x400x80 $1A $3A 0x010x020x040x080x100x200x400x80 $19 $39 0x010x020x040x080x100x200x400x80 $18 $38 $ff 0x010x020x040x080x100x200x400x80 $17 $37 0x010x020x040x080x100x200x400x80 $16 $36 0x010x020x040x080x100x200x400x80 $15 $35 $ff 0x010x020x040x080x100x200x400x80 $12 $32 0x010x020x040x080x100x200x400x80 $11 $31 0x010x020x040x080x100x200x400x80 $10 $30 0x010x020x040x080x100x200x400x80 $0F $2F 0x010x020x040x080x100x200x400x80 $0E $2E 0x400x80 $0D $2D 0x010x020x040x080x100x200x400x80 $0C $2C 0x010x020x040x080x100x200x400x80 $0B $2B 0x080x100x200x400x80 $0A $2A 0x010x020x040x080x100x200x400x80 $09 $29 0x010x020x040x080x100x200x400x80 $08 $28 0x010x020x040x080x100x200x80 $07 $27 0x010x020x04 $06 $26 0x010x020x040x080x100x400x80 $05 $25 0x010x02 $04 $24 0x010x020x040x080x100x200x400x80 $03 $23 $ff 0x010x020x040x080x100x200x400x80 $02 $22 0x010x020x040x080x100x200x400x80 $01 $21 0x010x020x040x080x100x200x400x80 $00 $20 $ff 0x010x020x040x080x100x200x400x80 [TQFP] 64 ['PEN] [PE0:RXD0:PDI] PDI, Serial Programming Data Input. During Serial Program Downloading, this pin is used as data input line for the ATmega104. RXD0, USART0 Receive Pin. Receive Data (Data input pin for the USART0). When the USART0 receiver is enabled this pin is configured as an input regardless of the value of DDRE0. When the USART0 forces this pin to be an input, a logical one in PORTE0 will turn on the internal pull-up. [PE1:TXD0:PDO] PDO, Serial Programming Data Output. During Serial Program Downloading, this pin is used as data output line for the ATmega104. TXD0, UART0 Transmit Pin. [PE2:AC+] [PE3:AC-] [PE4:INT4] INT4, External Interrupt source 4: The PE4 pin can serve as an external interrupt source. [PE5:INT5] INT5, External Interrupt source 5: The PE5 pin can serve as an external interrupt source. [PE6:INT6] INT6, External Interrupt source 6: The PE6 pin can serve as an external interrupt source. [PE7:INT7] INT7, External Interrupt source 7: The PE7 pin can serve as an external interrupt source. [PB0:'SS] SS: Slave port select input. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB0. As a slave, the SPI is activated when this pin is driven low. When the SPI is enabled as a master, the data direc-tion of this pin is controlled by DDB0. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB0 bit. [PB1:SCK] SCK: Master clock output, slave clock input pin for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB1. When the SPI is enabled as a master, the data direction of this pin is con-trolled by DDB1. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB1 bit. [PB2:MOSI] MOSI: SPI Master data output, slave data input for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB2. When the SPI is enabled as a master, the data direction of this pin is con-trolled by DDB2. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB2 bit. [PB3:MISO] MISO: Master data input, slave data output pin for SPI channel. When the SPI is enabled as a master, this pin is configured as an input regardless of the setting of DDB3. When the SPI is enabled as a slave, the data direction of this pin is controlled by DDB3. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB3 bit. [PB4:OC0:PWM0] OC0, Output Compare match output: The PB4 pin can serve as an external output for the Timer/Counter0 output compare. The pin has to be configured as an output (DDB4 set (one)) to serve this function. The OC0 pin is also the output pin for the PWM mode timer function. [PB5:OC1A:PWM1A] OC1A, Output Compare matchA output: The PB5 pin can serve as an external output for the Timer/Counter1 output com-pareA. The pin has to be configured as an output (DDB5 set (one)) to serve this function. The OC1A pin is also the output pin for the PWM mode timer function. [PB6:OC1B:PWM1B] OC1B, Output Compare matchB output: The PB6 pin can serve as an external output for the Timer/Counter1 output compare B. The pin has to be configured as an output (DDB6 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM mode timer function. [PB7:OC2:PWM2:OC1C] OC2, Output Compare match output: The PB7 pin can serve as an external output for the Timer/Counter2 output compare. The pin has to be configured as an output (DDB7 set (one)) to serve this function. The OC2 pin is also the output pin for the PWM mode timer function. [TOSC2] TOSC2, Timer Oscillator pin 2. [TOSC1] TOSC1, Timer Oscillator pin 1 ['RESET] [VCC] [GND] [XTAL2] [XTAL1] [PD0:'INT0] INT0, External Interrupt source 0. The PD0 pin can serve as external active low interrupt source to the MCU. The internal pull up MOS resistors can be activated as described above. See the interrupt description for further details, and how to enable the source. [PD1:'INT1] INT1, External Interrupt source 1. The PD1 pin can serve as external active low interrupt source to the MCU. The internal pull up MOS resistors can be activated as described above. See the interrupt description for further details, and how to enable the source. [PD2:'INT2] INT2, External Interrupt source 2. The PD2 pin can serve as external active low interrupt source to the MCU. The internal pull up MOS resistors can be activated as described above. See the interrupt description for further details, and how to enable the source. [PD3:'INT3] INT3, External Interrupt source 3. The PD3 pin can serve as external active low interrupt source to the MCU. The internal pull up MOS resistors can be activated as described above. See the interrupt description for further details, and how to enable the source. [PD4:IC1] IC1 - Input Capture Pin1: The PD4 pin can act as an input capture pin for Timer/Counter1. [PD5] [PD6:T1] T1, Timer/Counter1 counter source. [PD7:T2] T2, Timer/Counter2 counter source. ['WR] WR is the external data memory write control strobe. ['RD] RD is the external data memory read control strobe. [PC0:A8] [PC1:A9] [PC2:A10] [PC3:A11] [PC4:A12] [PC5:A13] [PC6:A14] [PC7:A15] [ALE] ALE is the external data memory Address Latch Enable signal. [PA7:AD7] [PA6:AD6] [PA5:AD5] [PA4:AD4] [PA3:AD3] [PA2:AD2] [PA1:AD1] [PA0:AD0] [VCC] [GND] [PF7:ADC7] ADC7, Analog to Digital Converter, channel 7. [PF6:ADC6] ADC6, Analog to Digital Converter, channel 6. [PF5:ADC5] ADC5, Analog to Digital Converter, channel 5. [PF4:ADC4] ADC4, Analog to Digital Converter, channel 4. [PF3:ADC3] Analog to Digital Converter, Channel 3 [PF2:ADC2] Analog to Digital Converter, Channel 2 [PF1:ADC1] Analog to Digital Converter, Channel 1 [PF0:ADC0] Analog to Digital Converter, Channel 0 [AREF] [GND] [AVCC] 4MHz 25C 5.5mA 1.6mA <1uA 4.0 5.0 4.0 5.0 [LOW:HIGH:EXTENDED] 8 BODLEVEL Brown out detector trigger level 1 BODEN Brown out detector enable 1 SUT1 Select start-up time 0 SUT0 Select start-up time 0 CKSEL3 Select Clock Source 0 CKSEL2 Select Clock Source 0 CKSEL1 Select Clock Source 0 CKSEL0 Select Clock Source 1 6 0x20 0x00 Serial program downloading (SPI) enabled 0x08 0x00 Preserve EEPROM memory through the Chip Erase cycle 0x03 0x00 SUT=00 Start-up time=5 CPU cycles 0x03 0x01 SUT=01 Start-up time=0.5 ms 0x03 0x02 SUT=10 Start-up time=4.0 ms 0x03 0x03 SUT=11 Start-up time=16.0 ms; default value 0xdf 0,0x20,0x20,WARNING! These fuse settings will disable the ISP interface! 0,0x20,0x20,WARNING! These fuse settings will disable the ISP interface! 256 0 [LB1 = 1 : LB2 = 1] No memory lock features enabled. [LB1 = 0 : LB2 = 1] Further programming of Flash and EEPROM is enabled. [LB1 = 0 : LB2 = 0] Same as previous, but verify is also disabled 3 2 0x06 0x06 Mode 1: No memory lock features enabled 0x06 0x04 Mode 2: Further programming disabled 0x06 0x00 Mode 3: Further programming and verification disabled LB1 Lockbit LB2 Lockbit [AD_CONVERTER:ANALOG_COMPARATOR:SPI:UART:CPU:EXTERNAL_INTERRUPT:EEPROM:PORTA:PORTB:PORTD:PORTC:PORTE:PORTF:TIMER_COUNTER_2:TIMER_COUNTER_0:TIMER_COUNTER_1:WATCHDOG] [ADMUX:ADCSR:ADCH:ADCL] ((IF ADMUX.ADLAR = 1) LINK [ADCH(1:0):ADCL(7:0)]); (IF ADMUX.ADLAR = 0) LINK [ADCH(7:0):ADCL(7:6)]); io_analo.bmp ADConv_01 AD Converter Feature list: 10-bit Resolution. 0.5 LSB Integral Non-Linearity. +-2 LSB Absolute Accuracy. TBD - 260 µs Conversion Time. Up to TBD kSPS at maximum resolution. 8 Multiplexed Single Ended Input Channels. 7 Differential input channels (TQFP package only). 2 Differential input channels with optional gain of 10x and 200x (TQFP package only). Optional left adjustment for ADC result readout. 0 - VCC ADC Input Voltage Range. Selectable 2.56 V ADC reference voltage. Free Running or Single Conversion Mode. Interrupt on ADC Conversion Complete. Sleep Mode Noise ADMUX The ADC multiplexer Selection Register $07 $27 io_analo.bmp N MUX2 Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). RW 0 MUX1 Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). RW 0 MUX0 Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). RW 0 ADCSR The ADC Control and Status register $06 $26 io_flag.bmp Y ADEN ADC Enable Writing a logical ‘1’ to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion. RW 0 ADSC ADC Start Conversion In Single Conversion Mode, a logical ‘1’ must be written to this bit to start each conversion. In Free Running Mode, a logical ‘1’ must be written to this bit to start the first conversion. The first time ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, an extended conversion will result. This extended conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. When a dummy conversion precedes a real conversion, ADSC will stay high until the real conversion completes. Writing a 0 to this bit has no effect RW 0 ADIF ADC Interrupt Flag This bit is set (one) when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set (one). ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a read-modify-write on ADCSR, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used. RW 0 ADIE ADC Interrupt Enable When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Complete Interrupt is activated. RW 0 ADPS2 ADC Prescaler Select Bits These bits determine the division factor between the XTAL frequency and the input clock to the ADC. RW 0 ADPS1 ADC Prescaler Select Bits These bits determine the division factor between the XTAL frequency and the input clock to the ADC. RW 0 ADPS0 ADC Prescaler Select Bits These bits determine the division factor between the XTAL frequency and the input clock to the ADC. RW 0 ADCH ADC Data Register High Byte When an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. The selected channel is differential if MUX4..0 are between ‘01000’ and ‘11101’, otherwise the selected channel is single ended. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8 bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUX4..0 bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adjus $05 $25 io_analo.bmp N ADC9 ADC Data Register High Byte Bit 1 RW 0 ADC8 ADC Data Register High Byte Bit 0 RW 0 ADCL ADC Data Register Low Byte When an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. The selected channel is differential if MUX4..0 are between ‘01000’ and ‘11101’, otherwise the selected channel is single ended. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8 bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUX4..0 bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adj $04 $24 io_analo.bmp N ADC7 ADC Data Register Low Byte Bit 7 RW 0 ADC6 ADC Data Register Low Byte Bit 6 RW 0 ADC5 ADC Data Register Low Byte Bit 5 RW 0 ADC4 ADC Data Register Low Byte Bit 4 RW 0 ADC3 ADC Data Register Low Byte Bit 3 RW 0 ADC2 ADC Data Register Low Byte Bit 2 RW 0 ADC1 ADC Data Register Low Byte Bit 1 RW 0 ADC0 ADC Data Register Low Byte Bit 0 RW 0 [ACSR] io_analo.bmp The analog comparator compares the input values on the positive input PB2 (AIN0) and negative input PB3 (AIN1). When the voltage on the positive input PB2 (AIN0) is higher than the voltage on the negative input PB3 (AIN1), the Analog Com-parator Output, ACO is set (one). The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator. The user can select Inter-rupt triggering on comparator output rise, fall or toggle ACSR Analog Comparator Control And Status Register $08 $28 io_analo.bmp Y ACD Analog Comparator Disable When this bit is set(one), the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed. RW 0 ACO Analog Comparator Output When this bit is set(one), the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed. R 0 ACI Analog Comparator Interrupt Flag This bit is set (one) when a comparator output event triggers the interrupt mode defined by ACI1 and ACI0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set (one) and the I-bit in SREG is set (one). ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag. Observe however, that if another bit in this register is modified using the SBI or CBI instruction, ACI will be cleared if it has become set before the operation RW 0 ACIE Analog Comparator Interrupt Enable When the ACIE bit is set (one) and the I-bit in the Status Register is set (one), the analog comparator interrupt is activated. When Cleared (Zero), the interrupt is disabled. RW 0 ACIC Analog Comparator Input Capture Enable When set (one), this bit enables the Input Capture function in Timer/Counter1 to be triggered by the analog comparator. The comparator output is in this case directly connected to the Input Capture front-end logic, making the comparator utilize the noise canceler and edge select features of the Timer/Counter1 Input Capture interrupt. When cleared (zero), no connection between the analog comparator and the Input Capture function is given. To make the comparator trigger the Timer/Counter1 Input Capture interrupt, the TICIE1 bit in the Timer Interrupt Mask Register (TIMSK) must be set (one) RW 0 ACIS1 Analog Comparator Interrupt Mode Select bit 1 These bits determine which comparator events that trigger the Analog Comparator interrupt. RW 0 ACIS0 Analog Comparator Interrupt Mode Select bit 0 These bits determine which comparator events that trigger the Analog Comparator interrupt. RW 0 [SPDR:SPSR:SPCR] io_com.bmp The Serial Peripheral Interface(SPI) allows high-speed synchronous data transfer between the AT90S4414/8515 and peripheral devices or between several AVR devices. The AT90S4414/8515 SPI features include the following: • Full-duplex, 3-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Four Programmable Bit Rates • End of Transmission Interrupt Flag • Write Collision Flag Protection • Wakeup from Idle Mode (Slave Mode Only) SPCR SPI Control Register $0D $2D io_flag.bmp Y SPIE SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR register is set and the global interrupts are enabled. RW 0 SPE SPI Enable When the SPE bit is set (one), the SPI is enabled. This bit must be set to enable any SPI operations. RW 0 DORD Data Order When the DORD bit is set (one), the LSB of the data word is transmitted first. When the DORD bit is cleared (zero), the MSB of the data word is transmitted first. RW 0 MSTR Master/Slave Select This bit selects Master SPI mode when set (one), and Slave SPI mode when cleared (zero). If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI master mode. RW 0 CPOL Clock polarity When this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is low when idle. Refer to Figure 36 and Figure 37 for additional information. RW 0 CPHA Clock Phase Refer to Figure 36 or Figure 37 for the functionality of this bit. RW 0 SPR1 SPI Clock Rate Select 1 These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave. RW 0 SPR0 SPI Clock Rate Select 0 These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave. RW 0 SPSR SPI Status Register $0E $2E io_flag.bmp Y SPIF SPI Interrupt Flag When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is generated if SPIE in SPCR is set (one) and global interrupts are enabled. If SS is an input and is driven low when the SPI is in master mode, this will also set the SPIF flag. SPIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the SPI status register when SPIF is set (one), then accessing the SPI Data Register (SPDR). R 0 WCOL Write Collision Flag The WCOL bit is set if the SPI data register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Register when WCOL is set (one), and then accessing the SPI Data Register. R 0 SPDR SPI Data Register The SPI Data Register is a read/write register used for data transfer between the register file and the SPI Shift register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read. $0F $2F io_com.bmp N SPDR7 SPI Data Register bit 7 RW X SPDR6 SPI Data Register bit 6 RW X SPDR5 SPI Data Register bit 5 RW X SPDR4 SPI Data Register bit 4 RW X SPDR3 SPI Data Register bit 3 RW X SPDR2 SPI Data Register bit 2 RW X SPDR1 SPI Data Register bit 1 R 0 SPDR0 SPI Data Register bit 0 R 0 [UDR:USR:UCR:UBRR] io_com.bmp Uart_00 UDR UART I/O Data Register The UDR register is actually two physically separate registers sharing the same I/O address. When writing to the register, the UART Transmit Data register is written. When reading from UDR, the UART Receive Data register is read. $0C $2C io_com.bmp N UDR7 UART I/O Data Register bit 7 RW 0 UDR6 UART I/O Data Register bit 6 RW 0 UDR5 UART I/O Data Register bit 5 RW 0 UDR4 UART I/O Data Register bit 4 RW 0 UDR3 UART I/O Data Register bit 3 RW 0 UDR2 UART I/O Data Register bit 2 RW 0 UDR1 UART I/O Data Register bit 1 RW 0 UDR0 UART I/O Data Register bit 0 RW 0 USR UART Status Register The USR register is a read-only register providing information on the UART Status. $0B $2B io_flag.bmp Y RXC UART Receive Complete This bit is set (one) when a received character is transferred from the Receiver Shift register to UDR. The bit is set regard-less of any detected framing errors. When the RXCIE bit in UCR is set, the UART Receive Complete interrupt will be executed when RXC is set(one). RXC is cleared by reading UDR. When interrupt-driven data reception is used, the UART Receive Complete Interrupt routine must read UDR in order to clear RXC, otherwise a new interrupt will occur once the interrupt routine terminates. R 0 TXC UART Transmit Complete This bit is set (one) when the entire character (including the stop bit) in the Transmit Shift register has been shifted out and no new data has been written to UDR. This flag is especially useful in half-duplex communications interfaces, where a transmitting application must enter receive mode and free the communications bus immediately after completing the transmission. When the TXCIE bit in UCR is set, setting of TXC causes the UART Transmit Complete interrupt to be executed. TXC is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the TXC bit is cleared (zero) by writing a logical one to the bit RW 0 UDRE UART Data Register Empty This bit is set (one) when a character written to UDR is transferred to the Transmit shift register. Setting of this bit indicates that the transmitter is ready to receive a new character for transmission. When the UDRIE bit in UCR is set, the UART Transmit Complete interrupt to be executed as long as UDRE is set. UDRE is cleared by writing UDR. When interrupt-driven data transmittal is used, the UART Data Register Empty Interrupt routine must write UDR in order to clear UDRE, otherwise a new interrupt will occur once the interrupt routine terminates. UDRE is set (one) during reset to indicate that the transmitter is ready R 1 FE Framing Error This bit is set if a Framing Error condition is detected, i.e. when the stop bit of an incoming character is zero. The FE bit is cleared when the stop bit of received data is one. R 0 OR Overrun This bit is set if an Overrun condition is detected, i.e. when a character already present in the UDR register is not read before the next character has been shifted into the Receiver Shift register. The OR bit is buffered, which means that it will be set once the valid data still in UDRE is read. The OR bit is cleared (zero) when data is received and transferred to UDR. R 0 UCR UART Control Register $0A $2A io_flag.bmp Y RXCIE RX Complete Interrupt Enable When this bit is set (one), a setting of the RXC bit in USR will cause the Receive Complete interrupt routine to be executed provided that global interrupts are enabled. RW 0 TXCIE TX Complete Interrupt Enable When this bit is set (one), a setting of the TXC bit in USR will cause the Transmit Complete interrupt routine to be executed provided that global interrupts are enabled. RW 0 UDRIE UART Data Register Empty Interrupt Enable When this bit is set (one), a setting of the UDRE bit in USR will cause the UART Data Register Empty interrupt routine to be executed provided that global interrupts are enabled. RW 0 RXEN Receiver Enable This bit enables the UART receiver when set (one). When the receiver is disabled, the TXC, OR and FE status flags cannot become set. If these flags are set, turning off RXEN does not cause them to be cleared. RW 0 TXEN Transmitter Enable This bit enables the UART transmitter when set (one). When disabling the transmitter while transmitting a character, the transmitter is not disabled before the character in the shift register plus any following character in UDR has been completely transmitted. RW 0 CHR9 9-bit Characters When this bit is set (one) transmitted and received characters are 9 bit long plus start and stop bits. The 9th bit is read and written by using the RXB8 and TXB8 bits in UCR, respectively. The 9th data bit can be used as an extra stop bit or a parity bit. RW 0 RXB8 Receive Data Bit 8 When CHR9 is set (one), RXB8 is the 9th data bit of the received character. R 1 TXB8 Transmit Data Bit 8 When CHR9 is set (one), TXB8 is the 9th data bit in the character to be transmitted. W 0 UBRR UART BAUD Rate Register $09 $29 io_com.bmp N UBRR7 UART Baud Rate Register bit 7 RW 0 UBRR6 UART Baud Rate Register bit 6 RW 0 UBRR5 UART Baud Rate Register bit 5 RW 0 UBRR4 UART Baud Rate Register bit 4 RW 0 UBRR3 UART Baud Rate Register bit 3 RW 0 UBRR2 UART Baud Rate Register bit 2 RW 0 UBRR1 UART Baud Rate Register bit 1 RW 0 UBRR0 UART Baud Rate Register bit 0 RW 0 [SREG:SPH:SPL:MCUCR:MCUSR:XDIV:RAMPZ] [SPH:SPL] io_cpu.bmp SREG Status Register $3F $5F io_sreg.bmp Y I Global Interrupt Enable The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable bit is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. RW 0 T Bit Copy Storage The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction. RW 0 H Half Carry Flag The half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed information. RW 0 S Sign Bit The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruc-tion Set Description for detailed information. RW 0 V Two's Complement Overflow Flag The two’s complement overflow flag V supports two’s complement arithmetics. See the Instruction Set Description for detailed information. RW 0 N Negative Flag The negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information. RW 0 Z Zero Flag The zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information. RW 0 C Carry Flag The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software. RW 0 SPH Stack Pointer High The general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the AT90S4414/8515 supports up to 64 kB external SRAM, all 16-bits are used. The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or return from interrupt R $3E $5E io_sph.bmp N SP15 Stack pointer bit 15 RW 0 SP14 Stack pointer bit 14 RW 0 SP13 Stack pointer bit 13 RW 0 SP12 Stack pointer bit 12 RW 0 SP11 Stack pointer bit 11 RW 0 SP10 Stack pointer bit 10 RW 0 SP9 Stack pointer bit 9 RW 0 SP8 Stack pointer bit 8 RW 0 SPL Stack Pointer Low The general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the AT90S4414/8515 supports up to 64 kB external SRAM, all 16-bits are used. The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or return from interrupt $3D $5D io_sph.bmp N SP7 Stack pointer bit 7 RW 0 SP6 Stack pointer bit 6 RW 0 SP5 Stack pointer bit 5 RW 0 SP4 Stack pointer bit 4 RW 0 SP3 Stack pointer bit 3 RW 0 SP2 Stack pointer bit 2 RW 0 SP1 Stack pointer bit 1 RW 0 SP0 Stack pointer bit 0 RW 0 MCUCR MCU Control Register The MCU Control Register contains control bits for general MCU functions. $35 $55 io_flag.bmp Y SRE External SRAM Enable Writing SRE to one enables the External Memory Interface.The pin functions AD7:0, A15:8, ALE, WR, and RD are acti-vated as the alternate pin functions. The SRE bit overrides any pin direction settings in the respective data direction regis-ters. Writing SRE to zero, disables the External Memory Interface and the normal pin and data direction settings are used. RW 0 SRW External SRAM Wait State Select For a detailed description in non ATmega103 Compatibility mode, see common description for the SRWn bits below (XMRA description). In ATmega103 Compatibility mode, writing SRW10 to one enables the wait state and one extra cycle is added during read/write strobe as shown in Figure 14. RW 0 SE Sleep Enable RW 0 SM1 Sleep Mode Select The description is to long for the tooltip help, please refer to the manual RW 0 SM0 Sleep Mode Select The description is to long for the tooltip help, please refer to the manual RW 0 MCUSR MCU Status Register The MCU Status Register provides information on which reset source caused a MCU reset. $34 $54 io_flag.bmp Y EXTRF EXTREF External Reset Flag This bit is set if an external reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag. R/W 0 PORF Power-on reset flag This bit is set if a power-on reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the reset flags to identify a reset condition, the user should read and then reset the MCUCSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags. R/W 0 XDIV XTAL Divide Control Register The XTAL Divide Control Register is used to divide the Source clock frequency by a number in the range 1 - 129. This fea-ture can be used to decrease power consumption when the requirement for processing power is low. $3C $5C io_cpu.bmp N XDIVEN XTAL Divide Enable When the XDIVEN bit is written one, the clock frequency of the CPU and all peripherals (clk I/O , clk ADC , clk CPU , clk FLASH ) is divided by the factor defined by the setting of XDIV6 - XDIV0. This bit can be written run-time to vary the clock frequency as suitable to the application. R/W 0 XDIV6 XTAl Divide Select Bit 6 These bits define the division factor that applies when the XDIVEN bit is set (one). Please refer to the manual for details on the formulas. R/W 0 XDIV5 XTAl Divide Select Bit 5 These bits define the division factor that applies when the XDIVEN bit is set (one). Please refer to the manual for details on the formulas. R/W 0 XDIV4 XTAl Divide Select Bit 4 These bits define the division factor that applies when the XDIVEN bit is set (one). Please refer to the manual for details on the formulas. R/W 0 XDIV3 XTAl Divide Select Bit 3 These bits define the division factor that applies when the XDIVEN bit is set (one). Please refer to the manual for details on the formulas. R/W 0 XDIV2 XTAl Divide Select Bit 2 These bits define the division factor that applies when the XDIVEN bit is set (one). Please refer to the manual for details on the formulas. R/W 0 XDIV1 XTAl Divide Select Bit 1 These bits define the division factor that applies when the XDIVEN bit is set (one). Please refer to the manual for details on the formulas. R/W 0 XDIV0 XTAl Divide Select Bit 0 These bits define the division factor that applies when the XDIVEN bit is set (one). Please refer to the manual for details on the formulas. R/W 0 RAMPZ RAM Page Z Select Register $3B $5B io_cpu.bmp Y RAMPZ0 RAMPZ0 = 0: Program memory address $0000 - $7FFF. RAMPZ0 = 1, program memory address $8000 - $FFFF. R/W 0 [EICR:EIMSK:EIFR] io_ext.bmp The external interrupts are triggered by the INT7:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT7:0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The external inter-rupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the Exter-nal Interrupt Control Registers - EICRA (INT3:0) and EICRB (INT7:4). When the external interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT7:4 requires the presence of an I/O clock, described in “Clock Systems and their Distribution” on page 29. Low level interrupts and the edge interrupt on INT3:0 are detected asynchronously. This implies that these inter-rupts can be used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode. Note that if a level triggered interrupt is used for wake-up from Power Down Mode, the changed level must be held for some time to wake up the MCU. This makes the MCU less sensitive to noise. The changed level is sampled twice by the watchdog oscillator clock. The period of the watchdog oscillator is 1 µs (nominal) at 5.0V and 25°C. The frequency of the watchdog oscillator is voltage dependent as shown in the Electrical Characteristics section. The MCU will wake up if the input has the required level during this sampling or if it is held until the end of the start-up time. The start-up time is defined by the SUT fuses as described in “Clock Systems and their Distribution” on page 29. If the level is sampled twice by the watchdog oscillator clock but disappears before the end of the start-up time, the MCU will still wake up, but no interrupt will be generated. The required level must be held long enough for the MCU to complete the wake up to trigger the level interrupt EICRB External Interrupt Control Register B The External Interrupts 7 - 4 are activated by the external pins INT7:4 if the SREG I-flag and the corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that activate the interrupts are defined in Table 49. The value on the INT7:4 pins are sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL divider is enabled. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an interrupt request as long as the pin is held low $3A $5A io_flag.bmp Y ISC71 External Interrupt 7-4 Sense Control Bit RW 0 ISC70 External Interrupt 7-4 Sense Control Bit RW 0 ISC61 External Interrupt 7-4 Sense Control Bit RW 0 ISC60 External Interrupt 7-4 Sense Control Bit RW 0 ISC51 External Interrupt 7-4 Sense Control Bit RW 0 ISC50 External Interrupt 7-4 Sense Control Bit RW 0 ISC41 External Interrupt 7-4 Sense Control Bit RW 0 ISC40 External Interrupt 7-4 Sense Control Bit RW 0 EIMSK External Interrupt Mask Register When an INT7- INT4 bit is written to one and the I-bit in the Status Register (SREG) is set (one), the corresponding external pin interrupt is enabled. The Interrupt Sense Control bits in the External Interrupt Control Registers - EICRA and EICRB defines whether the external interrupt is activated on rising or falling edge or level sensed. Activity on any of these pins will trigger an interrupt request even if the pin is enabled as an output. This provides a way of generating a software interrupt. $39 $59 io_flag.bmp Y INT7 External Interrupt Request 7 Enable RW 0 INT6 External Interrupt Request 6 Enable RW 0 INT5 External Interrupt Request 5 Enable RW 0 INT4 External Interrupt Request 4 Enable RW 0 INT3 External Interrupt Request 3 Enable RW 0 INT2 External Interrupt Request 2 Enable RW 0 INT1 External Interrupt Request 1 Enable RW 0 INT0 External Interrupt Request 0 Enable RW 0 EIFR External Interrupt Flag Register When an event on the INT7 - INT0 pins triggers an interrupt request, the corresponding interrupt flag, INTF7 - INTF0 becomes set (one). If the I-bit in SREG and the corresponding interrupt enable bit, INT7 - INT0 in EIMSK, are set (one), the MCU will jump to the interrupt vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag is cleared by writing a logical one to it. Note that when entering some sleep modes with the INT3:0 interrupts disabled, the input buffers on these pin will be disabled. This may cause a logic change in internal signals which will set the INTF3:0 flags. See “Digital Input Enable and Sleep Modes” on page 54 for more informa $38 $58 io_flag.bmp Y INTF7 External Interrupt Flag 7 RW 0 INTF6 External Interrupt Flag 6 RW 0 INTF5 External Interrupt Flag 5 RW 0 INTF4 External Interrupt Flag 4 RW 0 [EEARH:EEARL:EEDR:EECR] [EEARH:EEARL] io_cpu.bmp EEPROM Read/Write Access. The EEPROM access registers are accessible in the I/O space. The write access time for the EEPROM is given in Table 1. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page 19. for details on how to avoid problems in these situations.In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When theEEPROM is written, the CPU is halted for two clock cycles before the next instruction is execute EEARH EEPROM Read/Write Access High Byte Bits 11..0 - EEAR11..0: EEPROM Address The EEPROM Address Registers - EEARH and EEARL specify the EEPROM address in the 4K bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 4096. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed. $1F $3F io_cpu.bmp N EEAR11 EEPROM Read/Write Access Bit 11 RW 0 EEAR10 EEPROM Read/Write Access Bit 10 RW 0 EEAR9 EEPROM Read/Write Access Bit 9 RW 0 EEAR8 EEPROM Read/Write Access Bit 8 RW 0 EEARL EEPROM Read/Write Access Low Byte Bits 11..0 - EEAR11..0: EEPROM Address The EEPROM Address Registers - EEARH and EEARL specify the EEPROM address in the 4K bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 4096. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed. $1E $3E io_cpu.bmp N EEARL7 EEPROM Read/Write Access Bit 7 RW 0 EEARL6 EEPROM Read/Write Access Bit 6 RW 0 EEARL5 EEPROM Read/Write Access Bit 5 RW 0 EEARL4 EEPROM Read/Write Access Bit 4 RW 0 EEARL3 EEPROM Read/Write Access Bit 3 RW 0 EEARL2 EEPROM Read/Write Access Bit 2 RW 0 EEARL1 EEPROM Read/Write Access Bit 1 RW 0 EEARL0 EEPROM Read/Write Access Bit 0 RW 0 EEDR EEPROM Data Register For the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR. $1D $3D io_cpu.bmp N EEDR7 EEPROM Data Register bit 7 RW 0 EEDR6 EEPROM Data Register bit 6 RW 0 EEDR5 EEPROM Data Register bit 5 RW 0 EEDR4 EEPROM Data Register bit 4 RW 0 EEDR3 EEPROM Data Register bit 3 RW 0 EEDR2 EEPROM Data Register bit 2 RW 0 EEDR1 EEPROM Data Register bit 1 RW 0 EEDR0 EEPROM Data Register bit 0 RW 0 EECR EEPROM Control Register $1C $3C io_flag.bmp Y EERIE EEPROM Ready Interrupt Enable EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared. RW 0 EEMWE EEPROM Master Write Enable The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is written to one, writing EEWE to one within 4 clock cycles will write data to the EEPROM at the selected address. If EEMWE is zero, writing EEWE to one will have no effect. When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure. RW 0 EEWE EEPROM Write Enable The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential): 1. Wait until EEWE becomes zero. 2. Wait until SPMEN in SPMCR becomes zero. 3. Write new EEPROM address to EEAR (optional). 4. Write new EEPROM data to EEDR (optional). 5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR. 6. Within four clock cycles after setting EEMWE, write a logical one to EEWE. The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a boot loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See “Boot Loader Support - Read While Write self-programming” on page 228 for details about boot programming. Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR regis-ter will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the 4 last steps to avoid these problems. When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruc-tion is executed RW X EERE EEPROM Read Enable The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR register. The calibrated oscillator is used to time the EEPROM accesses. Table 1 lists the typical programming time for EEPROM access from the CPU RW 0 [PORTA:DDRA:PINA] io_port.bmp AVRSimIOPort.SimIOPort PORTA Port A Data Register $1B $3B io_port.bmp N PORTA7 Port A Data Register bit 7 RW 0 PORTA6 Port A Data Register bit 6 RW 0 PORTA5 Port A Data Register bit 5 RW 0 PORTA4 Port A Data Register bit 4 RW 0 PORTA3 Port A Data Register bit 3 RW 0 PORTA2 Port A Data Register bit 2 RW 0 PORTA1 Port A Data Register bit 1 RW 0 PORTA0 Port A Data Register bit 0 RW 0 DDRA Port A Data Direction Register $1A $3A io_flag.bmp N DDA7 Data Direction Register, Port A, bit 7 RW 0 DDA6 Data Direction Register, Port A, bit 6 RW 0 DDA5 Data Direction Register, Port A, bit 5 RW 0 DDA4 Data Direction Register, Port A, bit 4 RW 0 DDA3 Data Direction Register, Port A, bit 3 RW 0 DDA2 Data Direction Register, Port A, bit 2 RW 0 DDA1 Data Direction Register, Port A, bit 1 RW 0 DDA0 Data Direction Register, Port A, bit 0 RW 0 PINA Port A Input Pins The Port A Input Pins address - PINA - is not a register, and this address enables access to the physical value on each Port A pin. When reading PORTA the Port A Data Latch is read, and when reading PINA, the logical values present on the pins are read. $19 $39 io_port.bmp N PINA7 Input Pins, Port A bit 7 RW Hi-Z PINA6 Input Pins, Port A bit 6 RW Hi-Z PINA5 Input Pins, Port A bit 5 RW Hi-Z PINA4 Input Pins, Port A bit 4 RW Hi-Z PINA3 Input Pins, Port A bit 3 RW Hi-Z PINA2 Input Pins, Port A bit 2 RW Hi-Z PINA1 Input Pins, Port A bit 1 RW Hi-Z PINA0 Input Pins, Port A bit 0 RW Hi-Z [PORTB:DDRB:PINB] io_port.bmp AVRSimIOPort.SimIOPort PORTB Port B Data Register $18 $38 io_port.bmp N PORTB7 Port B Data Register bit 7 RW 0 PORTB6 Port B Data Register bit 6 RW 0 PORTB5 Port B Data Register bit 5 RW 0 PORTB4 Port B Data Register bit 4 RW 0 PORTB3 Port B Data Register bit 3 RW 0 PORTB2 Port B Data Register bit 2 RW 0 PORTB1 Port B Data Register bit 1 RW 0 PORTB0 Port B Data Register bit 0 RW 0 DDRB Port B Data Direction Register $17 $37 io_flag.bmp N DDB7 Port B Data Direction Register bit 7 RW 0 DDB6 Port B Data Direction Register bit 6 RW 0 DDB5 Port B Data Direction Register bit 5 RW 0 DDB4 Port B Data Direction Register bit 4 RW 0 DDB3 Port B Data Direction Register bit 3 RW 0 DDB2 Port B Data Direction Register bit 2 RW 0 DDB1 Port B Data Direction Register bit 1 RW 0 DDB0 Port B Data Direction Register bit 0 RW 0 PINB Port B Input Pins The Port B Input Pins address - PINB - is not a register, and this address enables access to the physical value on each Port B pin. When reading PORTB, the Port B Data Latch is read, and when reading PINB, the logical values present on the pins are read. $16 $36 io_port.bmp N PINB7 Port B Input Pins bit 7 R 0 PINB6 Port B Input Pins bit 6 R 0 PINB5 Port B Input Pins bit 5 R 0 PINB4 Port B Input Pins bit 4 R 0 PINB3 Port B Input Pins bit 3 R 0 PINB2 Port B Input Pins bit 2 R 0 PINB1 Port B Input Pins bit 1 R 0 PINB0 Port B Input Pins bit 0 R 0 [PORTD:DDRD:PIND] io_port.bmp AVRSimIOPort.SimIOPort PORTD Port D Data Register $12 $32 io_port.bmp N PORTD7 Port D Data Register bit 7 RW 0 PORTD6 Port D Data Register bit 6 RW 0 PORTD5 Port D Data Register bit 5 RW 0 PORTD4 Port D Data Register bit 4 RW 0 PORTD3 Port D Data Register bit 3 RW 0 PORTD2 Port D Data Register bit 2 RW 0 PORTD1 Port D Data Register bit 1 RW 0 PORTD0 Port D Data Register bit 0 RW 0 DDRD Port D Data Direction Register $11 $31 io_flag.bmp N DDD7 Port D Data Direction Register bit 7 RW 0 DDD6 Port D Data Direction Register bit 6 RW 0 DDD5 Port D Data Direction Register bit 5 RW 0 DDD4 Port D Data Direction Register bit 4 RW 0 DDD3 Port D Data Direction Register bit 3 RW 0 DDD2 Port D Data Direction Register bit 2 RW 0 DDD1 Port D Data Direction Register bit 1 RW 0 DDD0 Port D Data Direction Register bit 0 RW 0 PIND Port D Input Pins The Port D Input Pins address - PIND - is not a register, and this address enables access to the physical value on each Port D pin. When reading PORTD, the Port D Data Latch is read, and when reading PIND, the logical values present on the pins are read. $10 $30 io_port.bmp N PIND7 Port D Input Pins bit 7 R 0 PIND6 Port D Input Pins bit 6 R 0 PIND5 Port D Input Pins bit 5 R 0 PIND4 Port D Input Pins bit 4 R 0 PIND3 Port D Input Pins bit 3 R 0 PIND2 Port D Input Pins bit 2 R 0 PIND1 Port D Input Pins bit 1 R 0 PIND0 Port D Input Pins bit 0 R 0 [PORTC] io_port.bmp AVRSimIOPort.SimIOPort PORTC Port C Data Register $15 $35 io_port.bmp N PORTC7 Port C Data Register bit 7 RW 0 PORTC6 Port C Data Register bit 6 RW 0 PORTC5 Port C Data Register bit 5 RW 0 PORTC4 Port C Data Register bit 4 RW 0 PORTC3 Port C Data Register bit 3 RW 0 PORTC2 Port C Data Register bit 2 RW 0 PORTC1 Port C Data Register bit 1 RW 0 PORTC0 Port C Data Register bit 0 RW 0 [PORTE:DDRE:PINE] io_port.bmp AVRSimIOPort.SimIOPort PORTE Data Register, Port E $03 $23 io_port.bmp N PORTE7 RW 0 PORTE6 RW 0 PORTE5 RW 0 PORTE4 RW 0 PORTE3 RW 0 PORTE2 RW 0 PORTE1 RW 0 PORTE0 RW 0 DDRE Data Direction Register, Port E $02 $22 io_flag.bmp N DDE7 RW 0 DDE6 RW 0 DDE5 RW 0 DDE4 RW 0 DDE3 RW 0 DDE2 RW 0 DDE1 RW 0 DDE0 RW 0 PINE Input Pins, Port E $01 $21 io_port.bmp N PINE7 R 0 PINE6 R 0 PINE5 R 0 PINE4 R 0 PINE3 R 0 PINE2 R 0 PINE1 R 0 PINE0 R 0 [PINF] io_port.bmp AVRSimIOPort.SimIOPort PINF Input Pins, Port F $00 $20 io_port.bmp N PINF7 R 0 PINF6 R 0 PINF5 R 0 PINF4 R 0 PINF3 R 0 PINF2 R 0 PINF1 R 0 PINF0 R 0 [TIMSK:TIFR:TCCR2:TCNT2:OCR2] io_timer.bmp At8pwm2_00 The 8-bit Timer/Counter2 can select clock source from CK, prescaled CK, or external crystal input TOSC1. It can also be stopped as described in the section “Timer/Counter2 Control Register - TCCR2”. The status flags (overflow and compare match) are found in the Timer/Counter Interrupt Flag Register - TIFR. Control signals are found in the Timer/Counter Control Register TCCR2. The interrupt enable/disable settings are found in “The Timer/Counter Interrupt Mask Register - TIMSK”. When Timer/Counter2 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. This module features a high resolution and a high accuracy usage with the lower prescaling opportunities. Similarly, the high prescaling opportunities make this unit useful for lower speed functions or exact timing functions with infrequent actions. Timer/Counter2 can also be used as an 8-bit Pulse Width Modulator. In this mode, Timer/Counter2 and the output compare register serve as a glitch-free, stand-alone PWM with centered puls TIMSK Timer/Counter Interrupt Mask register $37 $57 io_flag.bmp Y OCIE2 Timer/Counter2 Output Compare Match Interrupt Enable When the OCIE2 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match interrupt is enabled. The corresponding interrupt (at vector $006) is executed if a compare match in Timer/Counter2 occurs, i.e. when the OCF2 bit is set in the Timer/Counter Interrupt Flag Register - TIFR. RW 0 TOIE2 Timer/Counter2 Overflow Interrupt Enable When the TOIE2 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow interrupt is RW 0 TIFR Timer/Counter Interrupt Flag Register $36 $56 io_flag.bmp Y OCF2 Output Compare Flag 2 The OCF2 bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2 - Output Compare Register2. OCF2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF2 is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE2 (Timer/Counter2 Compare match Interrupt Enable), and the OCF2 are set (one), the Timer/Counter2 Compare match Interrupt is executed. RW 0 TOV2 Timer/Counter2 Overflow Flag The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, and TOIE2 (Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In up/down PWM mode, this bit is set when Timer/Counter2 changes counting direction at $00. RW 0 TCCR2 Timer/Counter2 Control Register $25 $45 io_flag.bmp Y PWM2 Pulse Width Modulator Enable When set (one) this bit enables PWM mode for Timer/Counter2. RW 0 COM21 Compare Output Mode bit 1 The COM21 and COM20 control bits determine any output pin action following a compare match in Timer/Counter2. Output pin actions affect pin PD7(OC2). This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. (COM21:COM20) description: (0:0) = Timer/Counter disconnected from output pin OC2. (0:1) = Toggle the OC2 output line. (1:0) = Clear the OC2 output line (to zero). (1:1) = Set the OC2 output line (to one). Note: In PWM mode, these bits have a different function. RW 0 COM20 Compare Output Mode bit 0 The COM21 and COM20 control bits determine any output pin action following a compare match in Timer/Counter2. Output pin actions affect pin PD7(OC2). This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. (COM21:COM20) description: (0:0) = Timer/Counter disconnected from output pin OC2. (0:1) = Toggle the OC2 output line. (1:0) = Clear the OC2 output line (to zero). (1:1) = Set the OC2 output line (to one). Note: In PWM mode, these bits have a different function. RW 0 CTC2 Clear Timer/Counter2 on Compare Match When the CTC2 control bit is set (one), Timer/Counter2 is reset to $00 in the CPU clock cycle following a compare match. If the control bit is cleared, the Timer/Counter2 continues counting and is unaffected by a compare match. When a prescal-ing of 1 is used, and the compare register is set to C, the timer will count as follows if CTC2 is set: ...|C-1|C|0|1|... When the prescaler is set to divide by 8, the timer will count like this: ...|C-1,C-1,C-1,C-1,C-1,C-1,C-1,C-1|C,C,C,C,C,C,C,C |0,0,0,0,0,0,0,0|1,1,1,... In PWM mode, this bit has a different function. If the CTC2 bit is cleared in PWM mode, the Timer/Counter acts as an up/down counter. If the CTC2 bit is set (one), the Timer/Counter wraps when it reaches $FF RW 0 CS22 Clock Select bit 2 The Clock Select bits 2,1, and 0 define the prescaling source of Timer/Counter2. (CS22:CS21:CS20) Description. (0:0:0) Timer/Counter2 is stopped. (0:0:1) PCK2. (0:1:0) PCK2/8. (0:1:1) PCK2/32. (1:0:0) PCK2/64. (1:0:1) PCK2/128. (1:1:0) PCK2/256. (1:1:1) PCK2/1024. The Stop condition provides a Timer Enable/Disable function. The prescaled modes are scaled directly from the PCK2 clock. RW 0 CS21 Clock Select bit 1 The Clock Select bits 2,1, and 0 define the prescaling source of Timer/Counter2. (CS22:CS21:CS20) Description. (0:0:0) Timer/Counter2 is stopped. (0:0:1) PCK2. (0:1:0) PCK2/8. (0:1:1) PCK2/32. (1:0:0) PCK2/64. (1:0:1) PCK2/128. (1:1:0) PCK2/256. (1:1:1) PCK2/1024. The Stop condition provides a Timer Enable/Disable function. The prescaled modes are scaled directly from the PCK2 clock. RW 0 CS20 Clock Select bit 0 The Clock Select bits 2,1, and 0 define the prescaling source of Timer/Counter2. (CS22:CS21:CS20) Description. (0:0:0) Timer/Counter2 is stopped. (0:0:1) PCK2. (0:1:0) PCK2/8. (0:1:1) PCK2/32. (1:0:0) PCK2/64. (1:0:1) PCK2/128. (1:1:0) PCK2/256. (1:1:1) PCK2/1024. The Stop condition provides a Timer Enable/Disable function. The prescaled modes are scaled directly from the PCK2 clock. RW 0 TCNT2 Timer/Counter2 This 8-bit register contains the value of Timer/Counter2. Timer/Counters2 is implemented as an up or up/down (in PWM mode) counter with read and write access. If the Timer/Counter2iswritten to and a clocksourceisselected,it continues counting in the timer clock cycle following the write operation. $24 $44 io_timer.bmp N TCNT2-7 Timer/Counter 2 bit 7 RW 0 TCNT2-6 Timer/Counter 2 bit 6 RW 0 TCNT2-5 Timer/Counter 2 bit 5 RW 0 TCNT2-4 Timer/Counter 2 bit 4 RW 0 TCNT2-3 Timer/Counter 2 bit 3 RW 0 TCNT2-2 Timer/Counter 2 bit 2 RW 0 TCNT2-1 Timer/Counter 2 bit 1 RW 0 TCNT2-0 Timer/Counter 2 bit 0 RW 0 OCR2 Timer/Counter2 Output Compare Register The output compare register is an 8-bit read/write register. The Timer/Counter Output Compare Register contains the data to be continuously compared with Timer/Counter2. Actions on compare matches are specified in TCCR2. A compare match does only occur if Timer/Counter2 counts to the OCR2 value. A software write that sets TCNT2 and OCR2 to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Timer/Counter2 in PWM Mode When PWM mode is selected, the Timer/Counter2 either wraps (overflows) when it reaches $FF or it acts as an up/down counter. If the up/down mode is selected, the Timer/Counter2 and the Output Compare Register - OCR2 form an 8-bit, free-running, glitch-free, and phase correct PWM with outputs on the PD7(OC2) pin. If the overflow mode is selected, the Timer/Counter2 and the Output Compare Register - OCR2 form an 8-bit, free-running, and glitch-free PWM, operating with twice the speed of the up/down counting mode. PWM Modes (Up/Down and Overflow). The two different PWM modes are selected by the CTC2 bit in the Timer/Counter Control Register - TCCR2. If CTC2 is cleared and PWM mode is selected, the Timer/Counter acts as an up/down counter, counting up from $00 to $FF, where it turns and counts down again to zero before the cycle is repeated. When the counter value matches the con-tents of the Output Compare Register, the PD7(OC2) pin is set or cleared according to the settings of the COM21/COM20 bits in the Timer/Counter Control Register TCCR2. If CTC2 is set and PWM mode is selected, the Timer/Counters will wrap and start counting from $00 after reaching $FF. The PD7(OC2) pin will be set or cleared according to the settings of COM21/COM20 on a Timer/Counter overflow or when the counter value matches the contents of the Output Compare Register. Note that in PWM mode, the value to be written to the Output Compare Register is first transferred to a temporary location, and then latched into OCR2 when the Timer/Counter reaches $FF. This prevents the occurrence of odd-length PWM pulses (glitches) in the event of an unsynchronized OCR2 write. (CTC2:COM21:COM20) Effect on Compare Pin Frequency: (0:0:0) = Not connected. (0:0:1) = Not connected. (0:1:0) = Cleared on compare match, up-counting. Set on compare match, down-counting (non-inverted PWM). f TCK0/2 /510. (0:1:1) = Cleared on compare match, down-counting. Set on compare match, up-counting (inverted PWM). f TCK0/2 /510. (1:0:0) = Not connected. (1:0:1) = Not connected. (1:1:0) = Cleared on compare match, set on overflow. f TCK0/2 /256. (1:1:1) = Set on compare match, cleared on overflow. f TCK0/2 / $23 $43 io_timer.bmp N OCR2-7 Timer/Counter2 Output Compare Register Bit 7 RW 0 OCR2-6 Timer/Counter2 Output Compare Register Bit 6 RW 0 OCR2-5 Timer/Counter2 Output Compare Register Bit 5 RW 0 OCR2-4 Timer/Counter2 Output Compare Register Bit 4 RW 0 OCR2-3 Timer/Counter2 Output Compare Register Bit 3 RW 0 OCR2-2 Timer/Counter2 Output Compare Register Bit 2 RW 0 OCR2-1 Timer/Counter2 Output Compare Register Bit 1 RW 0 OCR2-0 Timer/Counter2 Output Compare Register Bit 0 RW 0 [TCCR0:TCNT0:OCR0:ASSR:TIMSK:TIFR] io_timer.bmp At8pwm1 TCCR0 Timer/Counter Control Register $33 $53 io_flag.bmp Y PWM0 Pulse Width Modulator Enable Setting this bit to 1 will enable the Pulse Width Modulator for Timer/Counter 0. RW 0 COM01 Compare Match Output Mode 1 These bits control the output compare pin (OC0) behavior. If one or both of the COM01:0 bits are set, the OC0 output over-rides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to OC0 pin must be set in order to enable the output driver. When OC0 is connected to the pin, the function of the COM01:0 bits depends on the WGM01:0 bit setting. Table 52 shows the COM01:0 bit functionality when the WGM01:0 bits are set to a normal or CTC mode (non-PWM) RW 0 COM00 Compare match Output Mode 0 These bits control the output compare pin (OC0) behavior. If one or both of the COM01:0 bits are set, the OC0 output over-rides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to OC0 pin must be set in order to enable the output driver. When OC0 is connected to the pin, the function of the COM01:0 bits depends on the WGM01:0 bit setting. Table 52 shows the COM01:0 bit functionality when the WGM01:0 bits are set to a normal or CTC mode (non-PWM) RW 0 CTC0 CLear Timer/Counter on Compare Match RW 0 CS02 Clock Select 2 The three clock select bits select the clock source to be used by the Timer/Counter, RW 0 CS01 Clock Select 1 The three clock select bits select the clock source to be used by the Timer/Counter, RW 0 CS00 Clock Select 1 The three clock select bits select the clock source to be used by the Timer/Counter, RW 0 TCNT0 Timer/Counter Register The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT0 register blocks (removes) the compare match on the following timer clock. Modifying the counter (TCNT0) while the counter is running, introduces a risk of missing a compare match between TCNT0 the OCR0 register. $32 $52 io_timer.bmp Y TCNT0_7 RW 0 TCNT0_6 RW 0 TCNT0_5 RW 0 TCNT0_4 RW 0 TCNT0_3 RW 0 TCNT0_2 RW 0 TCNT0_1 RW 0 TCNT0_0 RW 0 OCR0 Output Compare Register The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC0 pin. $31 $51 io_timer.bmp N OCR0_7 RW 0 OCR0_6 RW 0 OCR0_5 RW 0 OCR0_4 RW 0 OCR0_3 RW 0 OCR0_2 RW 0 OCR0_1 RW 0 OCR0_0 RW 0 ASSR Asynchronus Status Register $30 $50 io_flag.bmp Y AS0 Asynchronus Timer/Counter 0 When AS0 is cleared, Timer/Counter 0 is clocked from the I/O clock, clk I/O . When AS0 is set, Timer/Counter 0 is clocked from a crystal oscillator connected to the Timer Oscillator 1 (TOSC1) pin. When the value of AS0 is changed, the contents of TCNT0, OCR0, and TCCR0 might be corrupted. RW 0 TCN0UB Timer/Couner0 Update Busy When Timer/Counter0 operates asynchronously and TCNT0 is written, this bit becomes set. When TCNT0 has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCNT0 is ready to be updated with a new value. RW 0 OCR0UB Output Compare register 0 Busy When Timer/Counter0 operates asynchronously and OCR0 is written, this bit becomes set. When OCR0 has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that OCR0 is ready to be updated with a new value. RW 0 TCR0UB Timer/Counter Control Register 0 Update Busy When Timer/Counter0 operates asynchronously and TCCR0 is written, this bit becomes set. When TCCR0 has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCCR0 is ready to be updated with a new value. If a write is performed to any of the three Timer/Counter0 registers while its update busy flag is set, the updated value might get corrupted and cause an unintentional interrupt to occur.The mechanisms for reading TCNT0, OCR0, and TCCR0 are different. When reading TCNT0, the actual timer value is read. When reading OCR0 or TCCR0, the value in the temporary storage register is read RW 0 TIMSK Timer/Counter Interrupt Mask Register $37 $57 io_flag.bmp Y OCIE0 Timer/Counter0 Output Compare Match Interrupt register When the OCIE0 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Compare Match interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter0 occurs, i.e. when the OCF0 bit is set in the Timer/Counter Interrupt Flag Register - TIFR. RW 0 TOIE0 Timer/Counter0 Overflow Interrupt Enable When the TOIE0 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, i.e. when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register - TIFR. RW 0 TIFR Timer/Counter Interrupt Flag register $36 $56 io_flag.bmp Y OCF0 Output Compare Flag 0 The OCF0 bit is set (one) when a compare match occurs between the Timer/Counter0 and the data in OCR0 - Output Compare Register0. OCF0 is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF0 is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0 (Timer/Counter0 Compare match Interrupt Enable), and OCF0 are set (one), the Timer/Counter0 Compare match Interrupt is executed. RW 0 TOV0 Timer/Counter0 Overflow Flag The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter0 changes counting direction at $00. RW 0 [TIMSK:TIFR:TCCR1A:TCCR1B:TCNT1H:TCNT1L:OCR1AH:OCR1AL:OCR1BH:OCR1BL:ICR1H:ICR1L] [TCNT1H:TCNT1L];[OCR1AH:OCR1AL];[OCR1BH:OCR1BL];[ICR1H:ICR1L] io_timer.bmp t16pwm1_2.xml The 16-bit Timer/Counter1 can select clock source from CK, prescaled CK, or an external pin. In addition it can be stopped as described in the specification for the Timer/Counter1 Control Registers - TCCR1A and TCCR1B. The different status flags (overflow, compare match and capture event) are found in the Timer/Counter Interrupt Flag Register - TIFR. Control signals are found in the Timer/Counter1 Control Registers - TCCR1A and TCCR1B. The interrupt enable/disable settings for Timer/Counter1 are found in the Timer/Counter Interrupt Mask Register - TIMS TIMSK Timer/Counter Interrupt Mask Register $37 $57 io_flag.bmp Y TICIE1 Timer/Counter1 Input Capture Interrupt Enable When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on pin 31, ICP, i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR. RW 0 OCIE1A Timer/Counter1 Output CompareA Match Interrupt Enable When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a CompareA match in Timer/Counter1 occurs, i.e., when the OCF1A bit is set in the Timer/Counter Interrupt Flag Register - TIFR. RW 0 OCIE1B Timer/Counter1 Output CompareB Match Interrupt Enable When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter1 occurs, i.e., when the OCF1B bit is set in the Timer/Counter Interrupt Flag Register - TIFR. R 0 TOIE1 Timer/Counter1 Overflow Interrupt Enable When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $006) is executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR. RW 0 TIFR Timer/Counter Interrupt Flag register $36 $56 io_flag.bmp Y ICF1 Input Capture Flag 1 The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to the input capture register - ICR1. ICF1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF1 is cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable), and ICF1 are set (one), the Timer/Counter1 Capture Interrupt is executed. RW 0 OCF1A Output Compare Flag 1A The OCF1A bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare match InterruptA Enable), and the OCF1A are set (one), the Timer/Counter1 Compare A match Interrupt is executed. RW 0 OCF1B Output Compare Flag 1B The OCF1B bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1B - Output Compare Register 1B. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1B (Timer/Counter1 Compare match InterruptB Enable), and the OCF1B are set (one), the Timer/Counter1 Compare B match Interrupt is executed. RW 0 TOV1 Timer/Counter1 Overflow Flag The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the cor-responding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter1 changes counting direction at $0000. RW 0 TCCR1A Timer/Counter1 Control Register A $2F $4F io_flag.bmp Y COM1A1 Compare Output Mode 1A, bit 1 The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA pin 1. This is an alternative function to an I/O port and the corresponding direction control bit must be set (one) to control the output pin. The control configuration is shown in Table 9. RW 0 COM1A0 Compare Ouput Mode 1A, bit 0 The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA pin 1. This is an alternative function to an I/O port and the corresponding direction control bit must be set (one) to control the output pin. The control configuration is shown in Table 9. RW 0 COM1B1 Compare Output Mode 1B, bit 1 The COM1B1 and COM1B0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B - Output CompareB. RW 0 COM1B0 Compare Output Mode 1B, bit 0 The COM1B1 and COM1B0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B - Output CompareB. RW 0 PWM11 Pulse Width Modulator Select Bit 1 RW 0 PWM10 Pulse Width Modulator Select Bit 0 RW 0 TCCR1B Timer/Counter1 Control Register B $2E $4E io_flag.bmp Y ICNC1 Input Capture 1 Noise Canceler When the ICNC1 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the ICP - input capture pin - as specified. When the ICNC1 bit is set (one), four successive samples are measures on the ICP - input capture pin, and all samples must be high/low according to the input capture trigger specification in the ICES1 bit. The actual sampling frequency is XTAL clock frequency. RW 0 ICES1 Input Capture 1 Edge Select While the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the falling edge of the input capture pin - ICP. While the ICES1 bit is set (one), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the rising edge of the input capture pin - ICP. RW 0 CTC1 Clear Timer/Counter1 on Compare Match When the CTC1 control bit is set (one), the Timer/Counter1 is reset to $0000 in the clock cycle after a compareA match. If the CTC1 control bit is cleared, Timer/Counter1 continues counting and is unaffected by a compare match. Since the compare match is detected in the CPU clock cycle following the match, this function will behave differently when a prescal-ing higher than 1 is used for the timer. When a prescaling of 1 is used, and the compareA register is set to C, the timer will count as follows if CTC1 is set: ...|C-2 |C-1 |C |0|1 |... When the prescaler is set to divide by 8, the timer will count like this: ... | C-2, C-2, C-2, C-2, C-2, C-2, C-2, C-2 | C-1, C-1, C-1, C-1, C-1, C-1, C-1, C-1 | C, 0, 0, 0, 0, 0, 0, 0 | ... In PWM mode, this bit has no effect RW 0 CS12 Clock Select1 bit 2 RW 0 CS11 Clock Select1 bit 1 RW 0 CS10 Clock Select1 bit 0 RW 0 TCNT1H Timer/Counter1 High Byte This 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR1A, OCR1B and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program. <Please refer to the datasheet $2D $4D io_timer.bmp N TCNT1H7 Timer/Counter1 High Byte bit 7 RW 0 TCNT1H6 Timer/Counter1 High Byte bit 6 RW 0 TCNT1H5 Timer/Counter1 High Byte bit 5 RW 0 TCNT1H4 Timer/Counter1 High Byte bit 4 RW 0 TCNT1H3 Timer/Counter1 High Byte bit 3 RW 0 TCNT1H2 Timer/Counter1 High Byte bit 2 RW 0 TCNT1H1 Timer/Counter1 High Byte bit 1 RW 0 TCNT1H0 Timer/Counter1 High Byte bit 0 RW 0 TCNT1L Timer/Counter1 Low Byte This 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR1A, OCR1B and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program.<Please refer to the datasheet $2C $4C io_timer.bmp N TCNT1L7 Timer/Counter1 Low Byte bit 7 RW 0 TCNT1L6 Timer/Counter1 Low Byte bit 6 RW 0 TCNT1L5 Timer/Counter1 Low Byte bit 5 RW 0 TCNT1L4 Timer/Counter1 Low Byte bit 4 RW 0 TCNT1L3 Timer/Counter1 Low Byte bit 3 RW 0 TCNT1L2 Timer/Counter1 Low Byte bit 2 RW 0 TCNT1L1 Timer/Counter1 Low Byte bit 1 RW 0 TCNT1L0 Timer/Counter1 Low Byte bit 0 RW 0 OCR1AH Timer/Counter1 Outbut Compare Register High Byte The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program. <Please refer to the datasheet $2B $4B io_timer.bmp N OCR1AH7 Timer/Counter1 Outbut Compare Register High Byte bit 7 RW 0 OCR1AH6 Timer/Counter1 Outbut Compare Register High Byte bit 6 RW 0 OCR1AH5 Timer/Counter1 Outbut Compare Register High Byte bit 5 RW 0 OCR1AH4 Timer/Counter1 Outbut Compare Register High Byte bit 4 RW 0 OCR1AH3 Timer/Counter1 Outbut Compare Register High Byte bit 3 RW 0 OCR1AH2 Timer/Counter1 Outbut Compare Register High Byte bit 2 RW 0 OCR1AH1 Timer/Counter1 Outbut Compare Register High Byte bit 1 RW 0 OCR1AH0 Timer/Counter1 Outbut Compare Register High Byte bit 0 RW 0 OCR1AL Timer/Counter1 Output Compare Register Low Byte The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program .<Please refer to the datasheet $2A $4A io_timer.bmp N OCR1AL7 Timer/Counter1 Output Compare Register Low Byte Bit 7 RW 0 OCR1AL6 Timer/Counter1 Output Compare Register Low Byte Bit 6 RW 0 OCR1AL5 Timer/Counter1 Output Compare Register Low Byte Bit 5 RW 0 OCR1AL4 Timer/Counter1 Output Compare Register Low Byte Bit 4 RW 0 OCR1AL3 Timer/Counter1 Output Compare Register Low Byte Bit 3 RW 0 OCR1AL2 Timer/Counter1 Output Compare Register Low Byte Bit 2 RW 0 OCR1AL1 Timer/Counter1 Output Compare Register Low Byte Bit 1 RW 0 OCR1AL0 Timer/Counter1 Output Compare Register Low Byte Bit 0 RW 0 OCR1BH Timer/Counter1 Output Compare Register High Byte The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program. <Please refer to the datasheet $29 $49 io_timer.bmp N OCR1BH7 Timer/Counter1 Output Compare Register High Byte bit 7 RW 0 OCR1BH6 Timer/Counter1 Output Compare Register High Byte bit 6 RW 0 OCR1BH5 Timer/Counter1 Output Compare Register High Byte bit 5 RW 0 OCR1BH4 Timer/Counter1 Output Compare Register High Byte bit 4 RW 0 OCR1BH3 Timer/Counter1 Output Compare Register High Byte bit 3 RW 0 OCR1BH2 Timer/Counter1 Output Compare Register High Byte bit 2 RW 0 OCR1BH1 Timer/Counter1 Output Compare Register High Byte bit 1 RW 0 OCR1BH0 Timer/Counter1 Output Compare Register High Byte bit 0 RW 0 OCR1BL Timer/Counter1 Output Compare Register Low Byte The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program.<Please refer to the datasheet $28 $48 io_timer.bmp N OCR1BL7 Timer/Counter1 Output Compare Register Low Byte bit 7 R 0 OCR1BL6 Timer/Counter1 Output Compare Register Low Byte bit 6 RW 0 OCR1BL5 Timer/Counter1 Output Compare Register Low Byte bit 5 RW 0 OCR1BL4 Timer/Counter1 Output Compare Register Low Byte bit 4 RW 0 OCR1BL3 Timer/Counter1 Output Compare Register Low Byte bit 3 RW 0 OCR1BL2 Timer/Counter1 Output Compare Register Low Byte bit 2 RW 0 OCR1BL1 Timer/Counter1 Output Compare Register Low Byte bit 1 RW 0 OCR1BL0 Timer/Counter1 Output Compare Register Low Byte bit 0 RW 0 ICR1H Timer/Counter1 Input Capture Register High Byte The input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES1) of the signal at the input capture pin -ICP - is detected, the current value of the Timer/Counter1 is transferred to the Input Capture Register - ICR1. At the same time, the input capture flag - ICF1 - is set (one). Since the Input Capture Register - ICR1 - is a 16-bit register, a temporary register TEMP is used when ICR1 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR1L, the data is sent to the CPU and the data of the high byte ICR1H is placed in the TEMP register. When the CPU reads the data in the high byte ICR1H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR1L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT1, OCR1A and OCR1B. <Please refer to the datashee $27 $47 io_timer.bmp N ICR1H7 Timer/Counter1 Input Capture Register High Byte bit 7 RW 0 ICR1H6 Timer/Counter1 Input Capture Register High Byte bit 6 R 0 ICR1H5 Timer/Counter1 Input Capture Register High Byte bit 5 R 0 ICR1H4 Timer/Counter1 Input Capture Register High Byte bit 4 R 0 ICR1H3 Timer/Counter1 Input Capture Register High Byte bit 3 R 0 ICR1H2 Timer/Counter1 Input Capture Register High Byte bit 2 R 0 ICR1H1 Timer/Counter1 Input Capture Register High Byte bit 1 R 0 ICR1H0 Timer/Counter1 Input Capture Register High Byte bit 0 R 0 ICR1L Timer/Counter1 Input Capture Register Low Byte The input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES1) of the signal at the input capture pin -ICP - is detected, the current value of the Timer/Counter1 is transferred to the Input Capture Register - ICR1. At the same time, the input capture flag - ICF1 - is set (one). Since the Input Capture Register - ICR1 - is a 16-bit register, a temporary register TEMP is used when ICR1 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR1L, the data is sent to the CPU and the data of the high byte ICR1H is placed in the TEMP register. When the CPU reads the data in the high byte ICR1H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR1L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT1, OCR1A and OCR1B. <Please refer to the datasheet $26 $46 io_timer.bmp N ICR1L7 Timer/Counter1 Input Capture Register Low Byte bit 7 R 0 ICR1L6 Timer/Counter1 Input Capture Register Low Byte bit 6 R 0 ICR1L5 Timer/Counter1 Input Capture Register Low Byte bit 5 R 0 ICR1L4 Timer/Counter1 Input Capture Register Low Byte bit 4 R 0 ICR1L3 Timer/Counter1 Input Capture Register Low Byte bit 3 R 0 ICR1L2 Timer/Counter1 Input Capture Register Low Byte bit 2 R 0 ICR1L1 Timer/Counter1 Input Capture Register Low Byte bit 1 R 0 ICR1L0 Timer/Counter1 Input Capture Register Low Byte bit 0 R 0 [WDTCR] io_watch.bmp WDTCR Watchdog Timer Control Register $21 $41 io_flag.bmp Y WDTOE WDDE RW This bit must be set (one) when the WDE bit is cleared. Otherwise, the watchdog will not be disabled. Once set, hardware will clear this bit to zero after four clock cycles. Refer to the description of the WDE bit for a watchdog disable procedure. RW 0 WDE Watch Dog Enable When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog RW 0 WDP2 Watch Dog Timer Prescaler bit 2 RW 0 WDP1 Watch Dog Timer Prescaler bit 1 RW 0 WDP0 Watch Dog Timer Prescaler bit 0 RW 0 [SIMULATOR:STK500:STK500_2] AVRSimCoreV2.SimCoreV2 AVRSimMemory8bit.SimMemory8bit AVRSimInterrupt.SimInterrupt 0x2c 0 20 AVRSimIOPort.SimIOPort N AVRSimIOPort.SimIOPort N AVRSimIOPort.SimIOPort N AVRSimIOPort.SimIOPort N AVRSimIOPort.SimIOPort N AVRSimIOPort.SimIOPort N AVRSimIOExtInterrupt.SimIOExtInterrupt 0x02 0x39 0x01 0x38 0x01 0x10 0x01 0x0 0x0 AVRSimIOExtInterrupt.SimIOExtInterrupt 0x02 0x39 0x01 0x38 0x01 0x10 0x01 0x0 0x0 AVRSimIOExtInterrupt.SimIOExtInterrupt 0x04 0x39 0x02 0x38 0x02 0x10 0x02 0x0 0x0 AVRSimIOExtInterrupt.SimIOExtInterrupt 0x06 0x39 0x04 0x38 0x04 0x10 0x04 0x0 0x0 AVRSimIOExtInterrupt.SimIOExtInterrupt 0x08 0x39 0x08 0x38 0x08 0x10 0x08 0x0 0x0 AVRSimIOExtInterrupt.SimIOExtInterrupt 0x0A 0x39 0x10 0x38 0x10 0x10 0x10 0x3a 0x03 AVRSimIOExtInterrupt.SimIOExtInterrupt 0x0C 0x39 0x20 0x38 0x20 0x10 0x20 0x3a 0x0C AVRSimIOExtInterrupt.SimIOExtInterrupt 0x0E 0x39 0x40 0x38 0x40 0x10 0x40 0x3a 0x30 AVRSimIOExtInterrupt.SimIOExtInterrupt 0x10 0x39 0x80 0x38 0x80 0x10 0x80 0x3a 0xC0 AVRSimIOTimert8pwm1.SimIOTimert8pwm1 0x1E 0x20 0x18 0x10 AVRSimIOTimert16pwm1.SimIOTimert16pwm1 0x16 0x18 0x1A 0x1C 0x10 0x40 0x10 0x10 0x16 0x20 0x16 0x40 AVRSimIOTimert8pwm2.SimIOTimert8pwm2 0x12 0x14 0x18 0x80 0x10 0x80 AVRSimIOSpi.SimIOSpi 0x22 0x16 0x02 0x16 0x08 0x16 0x04 0x16 0x17 0x01 AVRSimIOUart.SimIOUart 0x24 0x28 0x26 0x01 0x02 0x01 0x01 0x99 0xff 0xe1 0xff AVRSimAC.SimIOAC 0x2e 0xB1 0 1 0 0x00 0x00 0x00 0 0xA0 0xD7 2001002532030x53112500x11256700x400x4C0x000x000x000x0464120xC00x000xA00x800x7F25625644440x0E 0x1E 0x8E 0x9E 0x2E 0x3E 0xAE 0xBE 0x4E 0x5E 0xCE 0xDE 0x6E 0x7E 0xEE 0xDE 0x66 0x76 0xE6 0xF6 0x6A 0x7A 0xEA 0x7A 0x7F 0xFD 0x00 0x01 0x00 0x00 0x00 0x001000000001515150100x0125625650x0025625620010