[CORE:INTERRUPT_VECTOR:PACKAGE:POWER:PROGVOLT:LOCKBIT:ADMIN:MEMORY:IO_MODULE:ICE_SETTINGS:FUSE]V2EAVRSimCoreV2.SimCoreV2[][][]32$00$1B$1A$1D$1C$1F$1E35AVRSimInterrupt.SimInterrupt$0000External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset and JTAG AVR Reset$0002External Interrupt Request 0$0004External Interrupt Request 1$0006External Interrupt Request 2$0008External Interrupt Request 3$000AExternal Interrupt Request 4$000CExternal Interrupt Request 5$000EExternal Interrupt Request 6$0010External Interrupt Request 7$0012Timer/Counter2 Compare Match$0014Timer/Counter2 Overflow$0016Timer/Counter1 Capture Event$0018Timer/Counter1 Compare Match A$001ATimer/Counter Compare Match B$001CTimer/Counter1 Overflow$001ETimer/Counter0 Compare Match$0020Timer/Counter0 Overflow$0022SPI Serial Transfer Complete$0024USART0, Rx Complete$0026USART0 Data Register Empty$0028USART0, Tx Complete$002AADC Conversion Complete$002CEEPROM Ready$002EAnalog Comparator$0030Timer/Counter1 Compare Match C$0032Timer/Counter3 Capture Event$0034Timer/Counter3 Compare Match A$0036Timer/Counter3 Compare Match B$0038Timer/Counter3 Compare Match C$003ATimer/Counter3 Overflow$003CUSART1, Rx Complete$003EUSART1, Data Register Empty$0040USART1, Tx Complete$00422-wire Serial Interface$0044Store Program Memory Read[TQFP]64['PEN][PE0:RXD0:PDI]PDI, Serial Programming Data Input. During Serial Program Downloading, this pin is used as data input line for the ATmega104. RXD0, USART0 Receive Pin. Receive Data (Data input pin for the USART0). When the USART0 receiver is enabled this pin is configured as an input regardless of the value of DDRE0. When the USART0 forces this pin to be an input, a logical one in PORTE0 will turn on the internal pull-up.[PE1:TXD0:PDO]PDO, Serial Programming Data Output. During Serial Program Downloading, this pin is used as data output line for the ATmega104. TXD0, UART0 Transmit Pin.[PE2:XCK0:AIN0]AIN0 - Analog Comparator Positive Input. This pin is directly connected to the positive input of the analog comparator. XCK0, USART0 external clock. The Data Direction Register (DDE2) controls whether the clock is output (DDE2 set) or input (DDE2 cleared). The XCK0 pin is active only when the USART0 operates in synchronous mode.[PE3:OC3A:AIN1]AIN1 - Analog Comparator Negative Input. This pin is directly connected to the negative input of the analog comparator. OC3A, Output Compare matchA output: The PE3 pin can serve as an external output for the Timer/Counter3 output com-pareA. The pin has to be configured as an output (DDE3 set (one)) to serve this function. The OC3A pin is also the output pin for the PWM mode timer function.[PE4:OC3B:INT4]INT4, External Interrupt source 4: The PE4 pin can serve as an external interrupt source. OC3B, Output Compare matchB output: The PE4 pin can serve as an external output for the Timer/Counter3 output com-pareB. The pin has to be configured as an output (DDE4 set (one)) to serve this function. The OC3B pin is also the output pin for the PWM mode timer function.[PE5:OC3C:INT5]INT5, External Interrupt source 5: The PE5 pin can serve as an external interrupt source. OC3C, Output Compare matchC output: The PE5 pin can serve as an external output for the Timer/Counter3 output com-pareC. The pin has to be configured as an output (DDE5 set (one)) to serve this function. The OC3C pin is also the output pin for the PWM mode timer function.[PE6:T3:INT6]INT6, External Interrupt source 6: The PE6 pin can serve as an external interrupt source. T3, Timer/Counter3 counter source.[PE7:IC3:INT7]INT7, External Interrupt source 7: The PE7 pin can serve as an external interrupt source. IC3 - Input Capture Pin3: The PE7 pin can act as an input capture pin for Timer/Counter3.[PB0:'SS]SS: Slave port select input. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB0. As a slave, the SPI is activated when this pin is driven low. When the SPI is enabled as a master, the data direc-tion of this pin is controlled by DDB0. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB0 bit.[PB1:SCK]SCK: Master clock output, slave clock input pin for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB1. When the SPI is enabled as a master, the data direction of this pin is con-trolled by DDB1. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB1 bit.[PB2:MOSI]MOSI: SPI Master data output, slave data input for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB2. When the SPI is enabled as a master, the data direction of this pin is con-trolled by DDB2. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB2 bit.[PB3:MISO]MISO: Master data input, slave data output pin for SPI channel. When the SPI is enabled as a master, this pin is configured as an input regardless of the setting of DDB3. When the SPI is enabled as a slave, the data direction of this pin is controlled by DDB3. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB3 bit.[PB4:OC0:PWM0]OC0, Output Compare match output: The PB4 pin can serve as an external output for the Timer/Counter0 output compare. The pin has to be configured as an output (DDB4 set (one)) to serve this function. The OC0 pin is also the output pin for the PWM mode timer function.[PB5:OC1A:PWM1A]OC1A, Output Compare matchA output: The PB5 pin can serve as an external output for the Timer/Counter1 output com-pareA. The pin has to be configured as an output (DDB5 set (one)) to serve this function. The OC1A pin is also the output pin for the PWM mode timer function.[PB6:OC1B:PWM1B]OC1B, Output Compare matchB output: The PB6 pin can serve as an external output for the Timer/Counter1 output compare B. The pin has to be configured as an output (DDB6 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM mode timer function.[PB7:OC2:PWM2:OC1C]OC2, Output Compare match output: The PB7 pin can serve as an external output for the Timer/Counter2 output compare. The pin has to be configured as an output (DDB7 set (one)) to serve this function. The OC2 pin is also the output pin for the PWM mode timer function.[PG3:TOSC2]TOSC2, Timer Oscillator pin 2: When the AS0 bit in ASSR is set (one) to enable asynchronous clocking of Timer/Counter0, pin PG3 is disconnected from the port, and becomes the input of the inverting oscillator amplifier. In this mode, a crystal oscillator is connected to this pin, and the pin can not be used as an I/O pin.[PG4:TOSC1]TOSC1, Timer Oscillator pin 1: When the AS0 bit in ASSR is set (one) to enable asynchronous clocking of Timer/Counter0, pin PG4 is disconnected from the port, and becomes the inverting output of the oscillator amplifier. In this mode, a crystal oscillator is connected to this pin, and the pin can not be used as an I/O pin.['RESET][VCC][GND][XTAL2][XTAL1][PD0:SCL:INT0]INT0, External Interrupt source 0. The PD0 pin can serve as external active low interrupt source to the MCU. The internal pull up MOS resistors can be activated as described above. See the interrupt description for further details, and how to enable the source. SCL, 2-wire Serial Interface Clock: When the TWEN bit in TWCR is set (one) to enable the 2-wire Serial Interface, pin PD0 is disconnected from the port and becomes the Serial Clock I/O pin for the 2-wire Serial Interface. In this mode, there is a spike filter on the pin to suppress spikes shorter than 50 ns on the input signal, and the pin is driven by an open drain driver with slew-rate limitation[PD1:SDA:INT1]INT1, External Interrupt source 1. The PD1 pin can serve as external active low interrupt source to the MCU. The internal pull up MOS resistors can be activated as described above. See the interrupt description for further details, and how to enable the source. SDA, 2-wire Serial Interface Data: When the TWEN bit in TWCR is set (one) to enable the 2-wire Serial Interface, pin PD1 is disconnected from the port and becomes the Serial Data I/O pin for the 2-wire Serial Interface. In this mode, there is aspike filter on the pin to suppress spikes shorter than 50 ns on the input signal, and the pin is driven by an open drain driver with slew-rate limitati[PD2:RXD1:INT2]INT2, External Interrupt source 2. The PD2 pin can serve as external active low interrupt source to the MCU. The internal pull up MOS resistors can be activated as described above. See the interrupt description for further details, and how to enable the source. RXD1, Receive Data (Data input pin for the USART1). When the USART1 receiver is enabled this pin is configured as an input regardless of the value of DDD2. When the USART forces this pin to be an input, the pull-up can still be controlled by the PORTD2 bi[PD3:TXD1:INT3]INT3, External Interrupt source 3. The PD3 pin can serve as external active low interrupt source to the MCU. The internal pull up MOS resistors can be activated as described above. See the interrupt description for further details, and how to enable the source. TXD1, Transmit Data (Data output pin for the USART1). When the USART1 transmitter is enabled, this pin is configured as an output regardless of the value of DDD3.[PD4:IC1]IC1 - Input Capture Pin1: The PD4 pin can act as an input capture pin for Timer/Counter1.[PD5:XCK1]XCK1, USART1 external clock. The Data Direction Register (DDD4) controls whether the clock is output (DDD4 set) or input (DDD4 cleared). The XCK1 pin is active only when the USART1 operates in synchronous mode.[PD6:T1]T1, Timer/Counter1 counter source.[PD7:T2]T2, Timer/Counter2 counter source.[PG0:'WR]WR is the external data memory write control strobe.[PG1:'RD]RD is the external data memory read control strobe.[PC0:A8][PC1:A9][PC2:A10][PC3:A11][PC4:A12][PC5:A13][PC6:A14][PC7:A15][PG2:ALE]ALE is the external data memory Address Latch Enable signal.[PA7:AD7][PA6:AD6][PA5:AD5][PA4:AD4][PA3:AD3][PA2:AD2][PA1:AD1][PA0:AD0][VCC][GND][PF7:ADC7:TDI]ADC7, Analog to Digital Converter, channel 7. TDI, JTAG Test Data In: Serial input data to be shifted in to the Instruction Register or Data Register (scan chains). When the JTAG interface is enabled, this pin can not be used as an I/O pin.[PF6:ADC6:TD0]ADC6, Analog to Digital Converter, channel 6. TDO, JTAG Test Data Out: Serial output data from Instruction register or Data Register. When the JTAG interface is enabled, this pin can not be used as an I/O pin.[PF5:ADC5:TMS]ADC5, Analog to Digital Converter, channel 5. TMS, JTAG Test Mode Select: This pin is used for navigating through the TAP-controller state machine. When the JTAG interface is enabled, this pin can not be used as an I/O pin.[PF4:ADC4:TCK]ADC4, Analog to Digital Converter, channel 4. TCK, JTAG Test Clock: JTAG operation is synchronous to TCK. When the JTAG interface is enabled, this pin can not be used as an I/O pin.[PF3:ADC3]Analog to Digital Converter, Channel 3[PF2:ADC2]Analog to Digital Converter, Channel 2[PF1:ADC1]Analog to Digital Converter, Channel 1[PF0:ADC0]Analog to Digital Converter, Channel 0[AREF][GND][AVCC]4MHz25C3.0mA1.0mA<1uA2.76.04.55.5[LB1 = 1 : LB2 = 1] No memory lock features enabled. [LB1 = 0 : LB2 = 1] Further programming of Flash and EEPROM is enabled. [LB1 = 0 : LB2 = 0] Same as previous, but verify is also disabled6110x030x03Mode 1: No memory lock features enabled0x030x02Mode 2: Further programming disabled0x030x00Mode 3: Further programming and verification disabled0x0C0x0CApplication Protection Mode 1: No lock on SPM and LPM in Application Section0x0C0x08Application Protection Mode 2: SPM prohibited in Application Section0x0C0x00Application Protection Mode 3: LPM and SPM prohibited in Application Section0x0C0x04Application Protection Mode 4: LPM prohibited in Application Section0x300x30Boot Loader Protection Mode 1: No lock on SPM and LPM in Boot Loader Section0x300x20Boot Loader Protection Mode 2: SPM prohibited in Boot Loader Section0x300x00Boot Loader Protection Mode 3: LPM and SPM prohibited in Boot Loader Section0x300x10Boot Loader Protection Mode 4: LPM prohibited in Boot Loader SectionLB1Lock bitLB2Lock bitBLB01Boot Lock bitBLB02Boot Lock bitBLB11Boot lock bitBLB12Boot lock bitATmega103comp6MHz169RELEASEDY$1E$97$01ATmega103compATmega12813107240964000$006065536$1000$0000$003FNANA$0020$005F0x3F0x5F0x010x020x040x080x100x200x400x800x3E0x5E0x010x020x040x080x100x200x400x800x3D0x5D0x010x020x040x080x100x200x400x800x3C0x5C0x010x020x040x080x100x200x400x800x3B0x5B0x010x3A0x5A0x010x020x040x080x100x200x400x800x390x590x010x020x040x080x100x200x400x800x380x580x010x020x040x080x100x200x400x800x370x570x400x800x010x020x040x080x100x200x360x560x400x800x010x020x040x080x100x200x350x550x010x020x040x080x100x200x400x800x340x540x010x020x330x530x010x020x040x080x100x200x400x320x520x010x020x040x080x100x200x400x800x310x510x010x020x040x080x100x200x400x800x300x500x010x020x040x080x2F0x4F0x010x020x100x200x400x800x2E0x4E0x010x020x040x080x400x800x2D0x4D0x010x020x040x080x100x200x400x800x2C0x4C0x010x020x040x080x100x200x400x800x2B0x4B0x010x020x040x080x100x200x400x800x2A0x4A0x010x020x040x080x100x200x400x800x290x490x010x020x040x080x100x200x400x800x280x480x010x020x040x080x100x200x400x800x270x470x010x020x040x080x100x200x400x800x260x460x010x020x040x080x100x200x400x800x250x450x010x020x040x080x100x200x400x240x440x010x020x040x080x100x200x400x800x230x430x010x020x040x080x100x200x400x800x220x420x210x410x010x020x040x080x100x200x400x080x010x020x040x800x1F0x3F0x010x020x040x080x1E0x3E0x010x020x040x080x100x200x400x800x1D0x3D0x010x020x040x080x100x200x400x800x1C0x3C0x010x020x040x080x1B0x3B0x010x020x040x080x100x200x400x800x1A0x3A0x010x020x040x080x100x200x400x800x190x390x010x020x040x080x100x200x400x800x180x380x010x020x040x080x100x200x400x800x170x370x010x020x040x080x100x200x400x800x160x360x010x020x040x080x100x200x400x800x150x350x010x020x040x080x100x200x400x800x140x340x130x330x120x320x010x020x040x080x100x200x400x800x110x310x010x020x040x080x100x200x400x800x100x300x010x020x040x080x100x200x400x800x0F0x2F0x010x020x040x080x100x200x400x800x0E0x2E0x010x400x800x0D0x2D0x010x020x040x080x100x200x400x800x0C0x2C0x010x020x040x080x100x200x400x800x0B0x2B0x010x020x040x080x100x200x400x800x0A0x2A0x010x020x040x080x100x200x400x800x090x290x010x020x040x080x100x200x400x800x080x280x010x020x040x080x100x200x400x800x070x270x010x020x040x080x100x200x400x800x060x260x010x020x040x080x100x200x400x800x050x250x010x020x040x080x100x200x400x800x040x240x010x020x040x080x100x200x400x800x030x230x010x020x040x080x100x200x400x800x020x220x010x020x040x080x100x200x400x800x010x210x010x020x040x080x100x200x400x800x000x200x010x020x040x080x100x200x400x80[LOW:HIGH:EXTENDED]8BODLEVELBrown out detector trigger level1BODENBrown out detector enable1SUT1Select start-up time0SUT0Select start-up time0CKSEL3Select Clock Source0CKSEL2Select Clock Source0CKSEL1Select Clock Source0CKSEL0Select Clock Source1610x800x00Brown-out detection level at VCC=4.0 V; [BODLEVEL=0]0x800x80Brown-out detection level at VCC=2.7 V; [BODLEVEL=1]0x400x00Brown-out detection enabled; [BODEN=0]0x3F0x00Ext. Clock; Start-up time: 6 CK + 0 ms; [CKSEL=0000 SUT=00]0x3F0x10Ext. Clock; Start-up time: 6 CK + 4 ms; [CKSEL=0000 SUT=01]0x3F0x20Ext. Clock; Start-up time: 6 CK + 64 ms; [CKSEL=0000 SUT=10]0x3F0x01Int. RC Osc. 1 MHz; Start-up time: 6 CK + 0 ms; [CKSEL=0001 SUT=00]0x3F0x11Int. RC Osc. 1 MHz; Start-up time: 6 CK + 4 ms; [CKSEL=0001 SUT=01]0x3F0x21Int. RC Osc. 1 MHz; Start-up time: 6 CK + 64 ms; [CKSEL=0001 SUT=10]; default value0x3F0x02Int. RC Osc. 2 MHz; Start-up time: 6 CK + 0 ms; [CKSEL=0010 SUT=00]0x3F0x12Int. RC Osc. 2 MHz; Start-up time: 6 CK + 4 ms; [CKSEL=0010 SUT=01]0x3F0x22Int. RC Osc. 2 MHz; Start-up time: 6 CK + 64 ms; [CKSEL=0010 SUT=10]0x3F0x03Int. RC Osc. 4 MHz; Start-up time: 6 CK + 0 ms; [CKSEL=0011 SUT=00]0x3F0x13Int. RC Osc. 4 MHz; Start-up time: 6 CK + 4 ms; [CKSEL=0011 SUT=01]0x3F0x23Int. RC Osc. 4 MHz; Start-up time: 6 CK + 64 ms; [CKSEL=0011 SUT=10]0x3F0x04Int. RC Osc. 8 MHz; Start-up time: 6 CK + 0 ms; [CKSEL=0100 SUT=00]0x3F0x14Int. RC Osc. 8 MHz; Start-up time: 6 CK + 4 ms; [CKSEL=0100 SUT=01]0x3F0x24Int. RC Osc. 8 MHz; Start-up time: 6 CK + 64 ms; [CKSEL=0100 SUT=10]0x3F0x05Ext. RC Osc. - 0.9 MHz; Start-up time: 18 CK + 0 ms; [CKSEL=0101 SUT=00]0x3F0x15Ext. RC Osc. - 0.9 MHz; Start-up time: 18 CK + 4 ms; [CKSEL=0101 SUT=01]0x3F0x25Ext. RC Osc. - 0.9 MHz; Start-up time: 18 CK + 64 ms; [CKSEL=0101 SUT=10]0x3F0x35Ext. RC Osc. - 0.9 MHz; Start-up time: 6 CK + 4 ms; [CKSEL=0101 SUT=11]0x3F0x06Ext. RC Osc. 0.9 MHz - 3.0 MHz; Start-up time: 18 CK + 0 ms; [CKSEL=0110 SUT=00]0x3F0x16Ext. RC Osc. 0.9 MHz - 3.0 MHz; Start-up time: 18 CK + 4 ms; [CKSEL=0110 SUT=01]0x3F0x26Ext. RC Osc. 0.9 MHz - 3.0 MHz; Start-up time: 18 CK + 64 ms; [CKSEL=0110 SUT=10]0x3F0x36Ext. RC Osc. 0.9 MHz - 3.0 MHz; Start-up time: 6 CK + 4 ms; [CKSEL=0110 SUT=11]0x3F0x07Ext. RC Osc. 3.0 MHz - 8.0 MHz; Start-up time: 18 CK + 0 ms; [CKSEL=0111 SUT=00]0x3F0x17Ext. RC Osc. 3.0 MHz - 8.0 MHz; Start-up time: 18 CK + 4 ms; [CKSEL=0111 SUT=01]0x3F0x27Ext. RC Osc. 3.0 MHz - 8.0 MHz; Start-up time: 18 CK + 64 ms; [CKSEL=0111 SUT=10]0x3F0x37Ext. RC Osc. 3.0 MHz - 8.0 MHz; Start-up time: 6 CK + 4 ms; [CKSEL=0111 SUT=11]0x3F0x08Ext. RC Osc. 8.0 MHz - 12.0 MHz; Start-up time: 18 CK + 0 ms; [CKSEL=1000 SUT=00]0x3F0x18Ext. RC Osc. 8.0 MHz - 12.0 MHz; Start-up time: 18 CK + 4 ms; [CKSEL=1000 SUT=01]0x3F0x28Ext. RC Osc. 8.0 MHz - 12.0 MHz; Start-up time: 18 CK + 64 ms; [CKSEL=1000 SUT=10]0x3F0x38Ext. RC Osc. 8.0 MHz - 12.0 MHz; Start-up time: 6 CK + 4 ms; [CKSEL=1000 SUT=11]0x3F0x09Ext. Low-Freq. Crystal; Start-up time: 1K CK + 4 ms; [CKSEL=1001 SUT=00]0x3F0x19Ext. Low-Freq. Crystal; Start-up time: 1K CK + 64 ms; [CKSEL=1001 SUT=01]0x3F0x29Ext. Low-Freq. Crystal; Start-up time: 32K CK + 64 ms; [CKSEL=1001 SUT=10]0x3F0x0AExt. Crystal/Resonator Low Freq.; Start-up time: 258 CK + 4 ms; [CKSEL=1010 SUT=00]0x3F0x1AExt. Crystal/Resonator Low Freq.; Start-up time: 258 CK + 64 ms; [CKSEL=1010 SUT=01]0x3F0x2AExt. Crystal/Resonator Low Freq.; Start-up time: 1K CK + 0 ms; [CKSEL=1010 SUT=10]0x3F0x3AExt. Crystal/Resonator Low Freq.; Start-up time: 1K CK + 4 ms; [CKSEL=1010 SUT=11]0x3F0x0BExt. Crystal/Resonator Low Freq.; Start-up time: 1K CK + 64 ms; [CKSEL=1011 SUT=00]0x3F0x1BExt. Crystal/Resonator Low Freq.; Start-up time: 16K CK + 0 ms; [CKSEL=1011 SUT=01]0x3F0x2BExt. Crystal/Resonator Low Freq.; Start-up time: 16K CK + 4 ms; [CKSEL=1011 SUT=10]0x3F0x3BExt. Crystal/Resonator Low Freq.; Start-up time: 16K CK + 64 ms; [CKSEL=1011 SUT=11]0x3F0x0CExt. Crystal/Resonator Medium Freq.; Start-up time: 258 CK + 4 ms; [CKSEL=1100 SUT=00]0x3F0x1CExt. Crystal/Resonator Medium Freq.; Start-up time: 258 CK + 64 ms; [CKSEL=1100 SUT=01]0x3F0x2CExt. Crystal/Resonator Medium Freq.; Start-up time: 1K CK + 0 ms; [CKSEL=1100 SUT=10]0x3F0x3CExt. Crystal/Resonator Medium Freq.; Start-up time: 1K CK + 4 ms; [CKSEL=1100 SUT=11]0x3F0x0DExt. Crystal/Resonator Medium Freq.; Start-up time: 1K CK + 64 ms; [CKSEL=1101 SUT=00]0x3F0x1DExt. Crystal/Resonator Medium Freq.; Start-up time: 16K CK + 0 ms; [CKSEL=1101 SUT=01]0x3F0x2DExt. Crystal/Resonator Medium Freq.; Start-up time: 16K CK + 4 ms; [CKSEL=1101 SUT=10]0x3F0x3DExt. Crystal/Resonator Medium Freq.; Start-up time: 16K CK + 64 ms; [CKSEL=1101 SUT=11]0x3F0x0EExt. Crystal/Resonator High Freq.; Start-up time: 258 CK + 4 ms; [CKSEL=1110 SUT=00]0x3F0x1EExt. Crystal/Resonator High Freq.; Start-up time: 258 CK + 64 ms; [CKSEL=1110 SUT=01]0x3F0x2EExt. Crystal/Resonator High Freq.; Start-up time: 1K CK + 0 ms; [CKSEL=1110 SUT=10]0x3F0x3EExt. Crystal/Resonator High Freq.; Start-up time: 1K CK + 4 ms; [CKSEL=1110 SUT=11]0x3F0x0FExt. Crystal/Resonator High Freq.; Start-up time: 1K CK + 64 ms; [CKSEL=1111 SUT=00]0x3F0x1FExt. Crystal/Resonator High Freq.; Start-up time: 16K CK + 0 ms; [CKSEL=1111 SUT=01]0x3F0x2FExt. Crystal/Resonator High Freq.; Start-up time: 16K CK + 4 ms; [CKSEL=1111 SUT=10]0x3F0x3FExt. Crystal/Resonator High Freq.; Start-up time: 16K CK + 64 ms; [CKSEL=1111 SUT=11]8OCDENEnable OCD1JTAGENEnable JTAG0SPIENEnable Serial programming and Data Downloading0CKOPTOscillator Options1EESAVEEEPROM memory is preserved through chip erase1BOOTSZ1Select Boot Size0BOOTSZ0Select Boot Size0BOOTRSTSelect Reset Vector1100x800x00On-Chip Debug Enabled; [OCDEN=0]0x400x00JTAG Interface Enabled; [JTAGEN=0]0x200x00Serial program downloading (SPI) enabled; [SPIEN=0]0x080x00Preserve EEPROM memory through the Chip Erase cycle; [EESAVE=0]0x060x06Boot Flash section size=512 words Boot start address=$FE00; [BOOTSZ=11]0x060x04Boot Flash section size=1024 words Boot start address=$FC00; [BOOTSZ=10]0x060x02Boot Flash section size=2048 words Boot start address=$F800; [BOOTSZ=01]0x060x00Boot Flash section size=4096 words Boot start address=$F000; [BOOTSZ=00] ; default value0x010x00Boot Reset vector Enabled (default address=$0000); [BOOTRST=0]0x100x00CKOPT fuse (operation dependent of CKSEL fuses); [CKOPT=0]2M103CATmega103 compatibility mode0WDTONWatchdog timer always on120x020x00ATmega103 Compatibility Mode [M103C=0]0x010x00Watchdog Timer always on; [WDTON=0][ANALOG_COMPARATOR:AD_CONVERTER:SPI:MISC:EEPROM:PORTA:PORTB:PORTD:PORTE:WATCHDOG:PORTC:PORTF:TIMER_COUNTER_2:TIMER_COUNTER_0:TIMER_COUNTER_1:USART0:EXTERNAL_INTERRUPT:CPU][SFIOR:ACSR]io_analo.bmpAlgComp_01SFIORSpecial Function IO Register0x200x40io_flag.bmpYACMEAnalog Comparator Multiplexer EnableWhen this bit is written logic one and the ADC is switched off (ADEN in ADCSR is zero), the ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed description of this bit, see “Analog Comparator Multiplexed Input” on page 186.RW0ACSRAnalog Comparator Control And Status Register0x080x28io_analo.bmpYACDAnalog Comparator DisableWhen this bit is written logic one, the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.RW0ACBGAnalog Comparator Bandgap SelectWhen this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. See “Internal Voltage Reference” on page 42.RW0ACOAnalog Compare OutputThe output of the analog comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1-2 clock cycles.RNAACIAnalog Comparator Interrupt FlagThis bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hard-ware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.RW0ACIEAnalog Comparator Interrupt EnableWhen the ACIE bit is written logic one and the I-bit in the Status Register is set, the analog comparator interrupt is acti-vated. When written logic zero, the interrupt is disabled.RW0ACICAnalog Comparator Input Capture EnableWhen written logic one, this bit enables the Input Capture function in Timer/Counter1 to be triggered by the analog comparator. The comparator output is in this case directly connected to the Input Capture front-end logic, making the comparator utilize the noise canceler and edge select features of the Timer/Counter1 Input Capture interrupt. When written logic zero, no connection between the analog comparator and the Input Capture function exists. To make the comparator trigger the Timer/Counter1 Input Capture interrupt, the TICIE1 bit in the Timer Interrupt Mask Register (TIMSK) must be setRW0ACIS1Analog Comparator Interrupt Mode Select bit 1These bits determine which comparator events that trigger the Analog Comparator interrupt.RW0ACIS0Analog Comparator Interrupt Mode Select bit 0These bits determine which comparator events that trigger the Analog Comparator interrupt.RW0[ADMUX:ADCSR:ADCH:ADCL]((IF ADMUX.ADLAR = 1) LINK [ADCH(1:0):ADCL(7:0)]); (IF ADMUX.ADLAR = 0) LINK [ADCH(7:0):ADCL(7:6)]);io_analo.bmpAD Converter Feature list: 10-bit Resolution. 0.5 LSB Integral Non-Linearity. +-2 LSB Absolute Accuracy. TBD - 260 µs Conversion Time. Up to TBD kSPS at maximum resolution. 8 Multiplexed Single Ended Input Channels. 7 Differential input channels (TQFP package only). 2 Differential input channels with optional gain of 10x and 200x (TQFP package only). Optional left adjustment for ADC result readout. 0 - VCC ADC Input Voltage Range. Selectable 2.56 V ADC reference voltage. Free Running or Single Conversion Mode. Interrupt on ADC Conversion Complete. Sleep Mode NoiseADMUXThe ADC multiplexer Selection Register0x070x27io_analo.bmpYREFS1Reference Selection Bit 1These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin.RW0REFS0Reference Selection Bit 0These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin.RW0ADLARLeft Adjust ResultThe ADLAR bit affects the presentation of the ADC conversion result in the ADC data register. If ADLAR is cleared, the result is right adjusted. If ADLAR is set, the result is left adjusted. Changing the ADLAR bit will affect the ADC data register immediately, regardless of any ongoing conversions. For a complete description of this bit, see “The ADC Data Register -ADCL and ADCH” on page 198. RW0MUX4Analog Channel and Gain Selection BitsThe value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).RW0MUX3Analog Channel and Gain Selection BitsThe value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).RW0MUX2Analog Channel and Gain Selection BitsThe value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).RW0MUX1Analog Channel and Gain Selection BitsThe value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).RW0MUX0Analog Channel and Gain Selection BitsThe value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).RW0ADCSRADCSRAThe ADC Control and Status register0x060x26io_flag.bmpYADENADC EnableWriting a logical ‘1’ to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.RW0ADSCADC Start ConversionIn Single Conversion Mode, a logical ‘1’ must be written to this bit to start each conversion. In Free Running Mode, a logical ‘1’ must be written to this bit to start the first conversion. The first time ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, an extended conversion will result. This extended conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. When a dummy conversion precedes a real conversion, ADSC will stay high until the real conversion completes. Writing a 0 to this bit has no effectRW0ADFRADC Free Running SelectWhen this bit is set (one) the ADC operates in Free Running Mode. In this mode, the ADC samples and updates the data registers continuously. Clearing this bit (zero) will terminate Free Running Mode.RW0ADIFADC Interrupt FlagThis bit is set (one) when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set (one). ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a read-modify-write on ADCSR, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used.RW0ADIEADC Interrupt EnableWhen this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Complete Interrupt is activated.RW0ADPS2ADC Prescaler Select BitsThese bits determine the division factor between the XTAL frequency and the input clock to the ADC.RW0ADPS1ADC Prescaler Select BitsThese bits determine the division factor between the XTAL frequency and the input clock to the ADC.RW0ADPS0ADC Prescaler Select BitsThese bits determine the division factor between the XTAL frequency and the input clock to the ADC.RW0ADCHADC Data Register High ByteWhen an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. The selected channel is differential if MUX4..0 are between ‘01000’ and ‘11101’, otherwise the selected channel is single ended. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8 bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUX4..0 bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adju0x050x25io_analo.bmpNADCH7ADC Data Register High Byte Bit 7RW0ADCH6ADC Data Register High Byte Bit 6RW0ADCH5ADC Data Register High Byte Bit 5RW0ADCH4ADC Data Register High Byte Bit 4RW0ADCH3ADC Data Register High Byte Bit 3RW0ADCH2ADC Data Register High Byte Bit 2RW0ADCH1ADC Data Register High Byte Bit 1RW0ADCH0ADC Data Register High Byte Bit 0RW0ADCLADC Data Register Low ByteWhen an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. The selected channel is differential if MUX4..0 are between ‘01000’ and ‘11101’, otherwise the selected channel is single ended. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8 bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUX4..0 bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right ad0x040x24io_analo.bmpNADCL7ADC Data Register Low Byte Bit 7RW0ADCL6ADC Data Register Low Byte Bit 6RW0ADCL5ADC Data Register Low Byte Bit 5RW0ADCL4ADC Data Register Low Byte Bit 4RW0ADCL3ADC Data Register Low Byte Bit 3RW0ADCL2ADC Data Register Low Byte Bit 2RW0ADCL1ADC Data Register Low Byte Bit 1RW0ADCL0ADC Data Register Low Byte Bit 0RW0[SPDR:SPSR:SPCR]io_com.bmpSPI_01The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the device and peripheral devices or between several AVR devices. The SPI includes the following features: • Full-duplex, 3-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Seven Programmable Bit Rates • End of Transmission Interrupt Flag • Write Collision Flag Protection • Wake-up from Idle Mode • Double Speed (CK/2) Master SPI ModeSPDRSPI Data RegisterThe SPI Data Register is a read/write register used for data transfer between the register file and the SPI Shift register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read.0x0F0x2Fio_com.bmpNSPDR7SPI Data Register bit 7RWXSPDR6SPI Data Register bit 6RWXSPDR5SPI Data Register bit 5RWXSPDR4SPI Data Register bit 4RWXSPDR3SPI Data Register bit 3RWXSPDR2SPI Data Register bit 2RWXSPDR1SPI Data Register bit 1R0SPDR0SPI Data Register bit 0R0SPSRSPI Status Register0x0E0x2Eio_flag.bmpYSPIFSPI Interrupt FlagWhen a serial transfer is complete, the SPIF bit is set (one) and an interrupt is generated if SPIE in SPCR is set (one) and global interrupts are enabled. If SS is an input and is driven low when the SPI is in master mode, this will also set the SPIF flag. SPIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the SPI status register when SPIF is set (one), then accessing the SPI Data Register (SPDR).R0WCOLWrite Collision FlagThe WCOL bit is set if the SPI data register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Register when WCOL is set (one), and then accessing the SPI Data Register.R0SPI2XDouble SPI Speed BitWhen this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in master mode (see Table 71). This means that the minimum SCK period will be 2 CPU clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at f ck / 4 or lower. The SPI interface on the ATmega104 is also used for program memory and EEPROM downloading or uploading. See page 253 for serial programming and verification.RW0SPCRSPI Control Register0x0D0x2Dio_flag.bmpYSPIESPI Interrupt EnableThis bit causes the SPI interrupt to be executed if SPIF bit in the SPSR register is set and the global interrupts are enabled.RW0SPESPI EnableWhen the SPE bit is set (one), the SPI is enabled. This bit must be set to enable any SPI operations.RW0DORDData OrderWhen the DORD bit is set (one), the LSB of the data word is transmitted first. When the DORD bit is cleared (zero), the MSB of the data word is transmitted first.RW0MSTRMaster/Slave SelectThis bit selects Master SPI mode when set (one), and Slave SPI mode when cleared (zero). If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI master mode.RW0CPOLClock polarityWhen this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is low when idle. Refer to Figure 36 and Figure 37 for additional information.RW0CPHAClock PhaseRefer to Figure 36 or Figure 37 for the functionality of this bit.RW0SPR1SPI Clock Rate Select 1RW0SPR0SPI Clock Rate Select 0RW0[SFIOR]io_cpu.bmpSFIORSpecial Function IO Register0x200x40io_flag.bmpYTSMTimer/Counter Synchronization ModeRW0ACMEAnalog Comparator Multiplexer EnableRW0PUDPull Up DisableWhen this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn registers are config-ured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See “Configuring the Pin” on page 52 for more details about this fea-ture.RW0PSR0Prescaler Reset Timer/Counter0RW0PSR321PSR1PSR2PSR3Prescaler Reset Timer/Counter3, Timer/Counter2, and Timer/Counter1RW0[EEARH:EEARL:EEDR:EECR]
[EEARH:EEARL]
io_cpu.bmpEEPROM Read/Write Access. The EEPROM access registers are accessible in the I/O space. The write access time for the EEPROM is given in Table 1. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page 19. for details on how to avoid problems in these situations.In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When theEEPROM is written, the CPU is halted for two clock cycles before the next instruction is executeEEARHEEPROM Read/Write Access High ByteBits 11..0 - EEAR11..0: EEPROM Address The EEPROM Address Registers - EEARH and EEARL specify the EEPROM address in the 4K bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 4096. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed. 0x1F0x3Fio_cpu.bmpNEEAR11EEPROM Read/Write Access Bit 11RW0EEAR10EEPROM Read/Write Access Bit 10RW0EEAR9EEPROM Read/Write Access Bit 9RW0EEAR8EEPROM Read/Write Access Bit 8RW0EEARLEEPROM Read/Write Access Low ByteBits 11..0 - EEAR11..0: EEPROM Address The EEPROM Address Registers - EEARH and EEARL specify the EEPROM address in the 4K bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 4096. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed. 0x1E0x3Eio_cpu.bmpNEEARL7EEPROM Read/Write Access Bit 7RW0EEARL6EEPROM Read/Write Access Bit 6RW0EEARL5EEPROM Read/Write Access Bit 5RW0EEARL4EEPROM Read/Write Access Bit 4RW0EEARL3EEPROM Read/Write Access Bit 3RW0EEARL2EEPROM Read/Write Access Bit 2RW0EEARL1EEPROM Read/Write Access Bit 1RW0EEARL0EEPROM Read/Write Access Bit 0RW0EEDREEPROM Data RegisterFor the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.0x1D0x3Dio_cpu.bmpNEEDR7EEPROM Data Register bit 7RW0EEDR6EEPROM Data Register bit 6RW0EEDR5EEPROM Data Register bit 5RW0EEDR4EEPROM Data Register bit 4RW0EEDR3EEPROM Data Register bit 3RW0EEDR2EEPROM Data Register bit 2RW0EEDR1EEPROM Data Register bit 1RW0EEDR0EEPROM Data Register bit 0RW0EECREEPROM Control Register0x1C0x3Cio_flag.bmpYEERIEEEPROM Ready Interrupt EnableEEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared.RW0EEMWEEEPROM Master Write EnableThe EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is written to one, writing EEWE to one within 4 clock cycles will write data to the EEPROM at the selected address. If EEMWE is zero, writing EEWE to one will have no effect. When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure.RW0EEWEEEPROM Write EnableThe EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential): 1. Wait until EEWE becomes zero. 2. Wait until SPMEN in SPMCR becomes zero. 3. Write new EEPROM address to EEAR (optional). 4. Write new EEPROM data to EEDR (optional). 5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR. 6. Within four clock cycles after setting EEMWE, write a logical one to EEWE. The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a boot loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See “Boot Loader Support - Read While Write self-programming” on page 228 for details about boot programming. Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR regis-ter will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the 4 last steps to avoid these problems. When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruc-tion is executedRWXEEREEEPROM Read EnableThe EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR register. The calibrated oscillator is used to time the EEPROM accesses. Table 1 lists the typical programming time for EEPROM access from the CPURW0[PORTA:DDRA:PINA]io_port.bmpAVRSimIOPort.SimIOPortPORTAPort A Data Register0x1B0x3Bio_port.bmpNPORTA7Port A Data Register bit 7RW0PORTA6Port A Data Register bit 6RW0PORTA5Port A Data Register bit 5RW0PORTA4Port A Data Register bit 4RW0PORTA3Port A Data Register bit 3RW0PORTA2Port A Data Register bit 2RW0PORTA1Port A Data Register bit 1RW0PORTA0Port A Data Register bit 0RW0DDRAPort A Data Direction Register0x1A0x3Aio_flag.bmpNDDA7Data Direction Register, Port A, bit 7RW0DDA6Data Direction Register, Port A, bit 6RW0DDA5Data Direction Register, Port A, bit 5RW0DDA4Data Direction Register, Port A, bit 4RW0DDA3Data Direction Register, Port A, bit 3RW0DDA2Data Direction Register, Port A, bit 2RW0DDA1Data Direction Register, Port A, bit 1RW0DDA0Data Direction Register, Port A, bit 0RW0PINAPort A Input PinsThe Port A Input Pins address - PINA - is not a register, and this address enables access to the physical value on each Port A pin. When reading PORTA the Port A Data Latch is read, and when reading PINA, the logical values present on the pins are read.0x190x39io_port.bmpNPINA7Input Pins, Port A bit 7RWHi-ZPINA6Input Pins, Port A bit 6RWHi-ZPINA5Input Pins, Port A bit 5RWHi-ZPINA4Input Pins, Port A bit 4RWHi-ZPINA3Input Pins, Port A bit 3RWHi-ZPINA2Input Pins, Port A bit 2RWHi-ZPINA1Input Pins, Port A bit 1RWHi-ZPINA0Input Pins, Port A bit 0RWHi-Z[PORTB:DDRB:PINB]io_port.bmpAVRSimIOPort.SimIOPortPORTBPort B Data Register0x180x38io_port.bmpNPORTB7Port B Data Register bit 7RW0PORTB6Port B Data Register bit 6RW0PORTB5Port B Data Register bit 5RW0PORTB4Port B Data Register bit 4RW0PORTB3Port B Data Register bit 3RW0PORTB2Port B Data Register bit 2RW0PORTB1Port B Data Register bit 1RW0PORTB0Port B Data Register bit 0RW0DDRBPort B Data Direction Register0x170x37io_flag.bmpNDDB7Port B Data Direction Register bit 7RW0DDB6Port B Data Direction Register bit 6RW0DDB5Port B Data Direction Register bit 5RW0DDB4Port B Data Direction Register bit 4RW0DDB3Port B Data Direction Register bit 3RW0DDB2Port B Data Direction Register bit 2RW0DDB1Port B Data Direction Register bit 1RW0DDB0Port B Data Direction Register bit 0RW0PINBPort B Input PinsThe Port B Input Pins address - PINB - is not a register, and this address enables access to the physical value on each Port B pin. When reading PORTB, the Port B Data Latch is read, and when reading PINB, the logical values present on the pins are read.0x160x36io_port.bmpNPINB7Port B Input Pins bit 7R0PINB6Port B Input Pins bit 6R0PINB5Port B Input Pins bit 5R0PINB4Port B Input Pins bit 4R0PINB3Port B Input Pins bit 3R0PINB2Port B Input Pins bit 2R0PINB1Port B Input Pins bit 1R0PINB0Port B Input Pins bit 0R0[PORTD:DDRD:PIND]io_port.bmpAVRSimIOPort.SimIOPortPORTDPort D Data Register0x120x32io_port.bmpNPORTD7Port D Data Register bit 7RW0PORTD6Port D Data Register bit 6RW0PORTD5Port D Data Register bit 5RW0PORTD4Port D Data Register bit 4RW0PORTD3Port D Data Register bit 3RW0PORTD2Port D Data Register bit 2RW0PORTD1Port D Data Register bit 1RW0PORTD0Port D Data Register bit 0RW0DDRDPort D Data Direction Register0x110x31io_flag.bmpNDDD7Port D Data Direction Register bit 7RW0DDD6Port D Data Direction Register bit 6RW0DDD5Port D Data Direction Register bit 5RW0DDD4Port D Data Direction Register bit 4RW0DDD3Port D Data Direction Register bit 3RW0DDD2Port D Data Direction Register bit 2RW0DDD1Port D Data Direction Register bit 1RW0DDD0Port D Data Direction Register bit 0RW0PINDPort D Input PinsThe Port D Input Pins address - PIND - is not a register, and this address enables access to the physical value on each Port D pin. When reading PORTD, the Port D Data Latch is read, and when reading PIND, the logical values present on the pins are read.0x100x30io_port.bmpNPIND7Port D Input Pins bit 7R0PIND6Port D Input Pins bit 6R0PIND5Port D Input Pins bit 5R0PIND4Port D Input Pins bit 4R0PIND3Port D Input Pins bit 3R0PIND2Port D Input Pins bit 2R0PIND1Port D Input Pins bit 1R0PIND0Port D Input Pins bit 0R0[PORTE:DDRE:PINE]io_port.bmpAVRSimIOPort.SimIOPortPORTEData Register, Port E0x030x23io_port.bmpNPORTE7RW0PORTE6RW0PORTE5RW0PORTE4RW0PORTE3RW0PORTE2RW0PORTE1RW0PORTE0RW0DDREData Direction Register, Port E0x020x22io_flag.bmpNDDE7RW0DDE6RW0DDE5RW0DDE4RW0DDE3RW0DDE2RW0DDE1RW0DDE0RW0PINEInput Pins, Port E0x010x21io_port.bmpNPINE7R0PINE6R0PINE5R0PINE4R0PINE3R0PINE2R0PINE1R0PINE0R0[WDTCR]io_watch.bmpWDTCRWDTCSRWatchdog Timer Control Register0x210x41io_flag.bmpYWDCEWDTOEWatchdog Change EnableThis bit must be set when the WDE bit is written to logic zero.Otherwise,the watchdog will not be disabled.Once written to one,hardware will clear this bit after four clock cycles.Refer to the description of the WDE bit for a watchdog disable procedure.This bit must also be set when changing the prescaler bits. RW0WDEWatch Dog EnableWhen the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdogRW0WDP2Watch Dog Timer Prescaler bit 2The WDP2,WDP1,and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled.RW0WDP1Watch Dog Timer Prescaler bit 1The WDP2,WDP1,and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled.RW0WDP0Watch Dog Timer Prescaler bit 0The WDP2,WDP1,and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled.RW0[PORTC]io_port.bmpAVRSimIOPort.SimIOPortPORTCPort C Data Register0x150x35io_port.bmpNPORTC7Port C Data Register bit 7RW0PORTC6Port C Data Register bit 6RW0PORTC5Port C Data Register bit 5RW0PORTC4Port C Data Register bit 4RW0PORTC3Port C Data Register bit 3RW0PORTC2Port C Data Register bit 2RW0PORTC1Port C Data Register bit 1RW0PORTC0Port C Data Register bit 0RW0[PINF]io_port.bmpAVRSimIOPort.SimIOPortPINFInput Pins, Port F0x000x20io_port.bmpNPINF7R0PINF6R0PINF5R0PINF4R0PINF3R0PINF2R0PINF1R0PINF0R0[TIMSK:TIFR:TCCR2:TCNT2:OCR2]io_timer.bmpAt8pwm2_00The 8-bit Timer/Counter2 can select clock source from CK, prescaled CK, or external crystal input TOSC1. It can also be stopped as described in the section “Timer/Counter2 Control Register - TCCR2”. The status flags (overflow and compare match) are found in the Timer/Counter Interrupt Flag Register - TIFR. Control signals are found in the Timer/Counter Control Register TCCR2. The interrupt enable/disable settings are found in “The Timer/Counter Interrupt Mask Register - TIMSK”. When Timer/Counter2 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. This module features a high resolution and a high accuracy usage with the lower prescaling opportunities. Similarly, the high prescaling opportunities make this unit useful for lower speed functions or exact timing functions with infrequent actions. Timer/Counter2 can also be used as an 8-bit Pulse Width Modulator. In this mode, Timer/Counter2 and the output compare register serve as a glitch-free, stand-alone PWM with centered pulsTIMSKTimer/Counter Interrupt Mask register0x370x57io_flag.bmpYOCIE2Timer/Counter2 Output Compare Match Interrupt EnableWhen the OCIE2 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match interrupt is enabled. The corresponding interrupt (at vector $006) is executed if a compare match in Timer/Counter2 occurs, i.e. when the OCF2 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.RW0TOIE2Timer/Counter2 Overflow Interrupt EnableWhen the TOIE2 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow interrupt isRW0TIFRTimer/Counter Interrupt Flag Register0x360x56io_flag.bmpYOCF2Output Compare Flag 2The OCF2 bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2 - Output Compare Register2. OCF2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF2 is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE2 (Timer/Counter2 Compare match Interrupt Enable), and the OCF2 are set (one), the Timer/Counter2 Compare match Interrupt is executed.RW0TOV2Timer/Counter2 Overflow FlagThe TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, and TOIE2 (Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In up/down PWM mode, this bit is set when Timer/Counter2 changes counting direction at $00.RW0TCCR2Timer/Counter2 Control Register0x250x45io_flag.bmpYPWM2Pulse Width Modulator EnableWhen set (one) this bit enables PWM mode for Timer/Counter2.RW0COM21Compare Output Mode bit 1The COM21 and COM20 control bits determine any output pin action following a compare match in Timer/Counter2. Output pin actions affect pin PD7(OC2). This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. (COM21:COM20) description: (0:0) = Timer/Counter disconnected from output pin OC2. (0:1) = Toggle the OC2 output line. (1:0) = Clear the OC2 output line (to zero). (1:1) = Set the OC2 output line (to one). Note: In PWM mode, these bits have a different function.RW0COM20Compare Output Mode bit 0The COM21 and COM20 control bits determine any output pin action following a compare match in Timer/Counter2. Output pin actions affect pin PD7(OC2). This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. (COM21:COM20) description: (0:0) = Timer/Counter disconnected from output pin OC2. (0:1) = Toggle the OC2 output line. (1:0) = Clear the OC2 output line (to zero). (1:1) = Set the OC2 output line (to one). Note: In PWM mode, these bits have a different function.RW0CTC2Clear Timer/Counter2 on Compare MatchWhen the CTC2 control bit is set (one), Timer/Counter2 is reset to $00 in the CPU clock cycle following a compare match. If the control bit is cleared, the Timer/Counter2 continues counting and is unaffected by a compare match. When a prescal-ing of 1 is used, and the compare register is set to C, the timer will count as follows if CTC2 is set: ...|C-1|C|0|1|... When the prescaler is set to divide by 8, the timer will count like this: ...|C-1,C-1,C-1,C-1,C-1,C-1,C-1,C-1|C,C,C,C,C,C,C,C |0,0,0,0,0,0,0,0|1,1,1,... In PWM mode, this bit has a different function. If the CTC2 bit is cleared in PWM mode, the Timer/Counter acts as an up/down counter. If the CTC2 bit is set (one), the Timer/Counter wraps when it reaches $FFRW0CS22Clock Select bit 2The Clock Select bits 2,1, and 0 define the prescaling source of Timer/Counter2. (CS22:CS21:CS20) Description. (0:0:0) Timer/Counter2 is stopped. (0:0:1) PCK2. (0:1:0) PCK2/8. (0:1:1) PCK2/32. (1:0:0) PCK2/64. (1:0:1) PCK2/128. (1:1:0) PCK2/256. (1:1:1) PCK2/1024. The Stop condition provides a Timer Enable/Disable function. The prescaled modes are scaled directly from the PCK2 clock.RW0CS21Clock Select bit 1The Clock Select bits 2,1, and 0 define the prescaling source of Timer/Counter2. (CS22:CS21:CS20) Description. (0:0:0) Timer/Counter2 is stopped. (0:0:1) PCK2. (0:1:0) PCK2/8. (0:1:1) PCK2/32. (1:0:0) PCK2/64. (1:0:1) PCK2/128. (1:1:0) PCK2/256. (1:1:1) PCK2/1024. The Stop condition provides a Timer Enable/Disable function. The prescaled modes are scaled directly from the PCK2 clock.RW0CS20Clock Select bit 0The Clock Select bits 2,1, and 0 define the prescaling source of Timer/Counter2. (CS22:CS21:CS20) Description. (0:0:0) Timer/Counter2 is stopped. (0:0:1) PCK2. (0:1:0) PCK2/8. (0:1:1) PCK2/32. (1:0:0) PCK2/64. (1:0:1) PCK2/128. (1:1:0) PCK2/256. (1:1:1) PCK2/1024. The Stop condition provides a Timer Enable/Disable function. The prescaled modes are scaled directly from the PCK2 clock.RW0TCNT2Timer/Counter2This 8-bit register contains the value of Timer/Counter2. Timer/Counters2 is implemented as an up or up/down (in PWM mode) counter with read and write access. If the Timer/Counter2iswritten to and a clocksourceisselected,it continues counting in the timer clock cycle following the write operation.0x240x44io_timer.bmpNTCNT2-7Timer/Counter 2 bit 7RW0TCNT2-6Timer/Counter 2 bit 6RW0TCNT2-5Timer/Counter 2 bit 5RW0TCNT2-4Timer/Counter 2 bit 4RW0TCNT2-3Timer/Counter 2 bit 3RW0TCNT2-2Timer/Counter 2 bit 2RW0TCNT2-1Timer/Counter 2 bit 1RW0TCNT2-0Timer/Counter 2 bit 0RW0OCR2Timer/Counter2 Output Compare RegisterThe output compare register is an 8-bit read/write register. The Timer/Counter Output Compare Register contains the data to be continuously compared with Timer/Counter2. Actions on compare matches are specified in TCCR2. A compare match does only occur if Timer/Counter2 counts to the OCR2 value. A software write that sets TCNT2 and OCR2 to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Timer/Counter2 in PWM Mode When PWM mode is selected, the Timer/Counter2 either wraps (overflows) when it reaches $FF or it acts as an up/down counter. If the up/down mode is selected, the Timer/Counter2 and the Output Compare Register - OCR2 form an 8-bit, free-running, glitch-free, and phase correct PWM with outputs on the PD7(OC2) pin. If the overflow mode is selected, the Timer/Counter2 and the Output Compare Register - OCR2 form an 8-bit, free-running, and glitch-free PWM, operating with twice the speed of the up/down counting mode. PWM Modes (Up/Down and Overflow). The two different PWM modes are selected by the CTC2 bit in the Timer/Counter Control Register - TCCR2. If CTC2 is cleared and PWM mode is selected, the Timer/Counter acts as an up/down counter, counting up from $00 to $FF, where it turns and counts down again to zero before the cycle is repeated. When the counter value matches the con-tents of the Output Compare Register, the PD7(OC2) pin is set or cleared according to the settings of the COM21/COM20 bits in the Timer/Counter Control Register TCCR2. If CTC2 is set and PWM mode is selected, the Timer/Counters will wrap and start counting from $00 after reaching $FF. The PD7(OC2) pin will be set or cleared according to the settings of COM21/COM20 on a Timer/Counter overflow or when the counter value matches the contents of the Output Compare Register. Note that in PWM mode, the value to be written to the Output Compare Register is first transferred to a temporary location, and then latched into OCR2 when the Timer/Counter reaches $FF. This prevents the occurrence of odd-length PWM pulses (glitches) in the event of an unsynchronized OCR2 write. (CTC2:COM21:COM20) Effect on Compare Pin Frequency: (0:0:0) = Not connected. (0:0:1) = Not connected. (0:1:0) = Cleared on compare match, up-counting. Set on compare match, down-counting (non-inverted PWM). f TCK0/2 /510. (0:1:1) = Cleared on compare match, down-counting. Set on compare match, up-counting (inverted PWM). f TCK0/2 /510. (1:0:0) = Not connected. (1:0:1) = Not connected. (1:1:0) = Cleared on compare match, set on overflow. f TCK0/2 /256. (1:1:1) = Set on compare match, cleared on overflow. f TCK0/2 /0x230x43io_timer.bmpNOCR2-7Timer/Counter2 Output Compare Register Bit 7RW0OCR2-6Timer/Counter2 Output Compare Register Bit 6RW0OCR2-5Timer/Counter2 Output Compare Register Bit 5RW0OCR2-4Timer/Counter2 Output Compare Register Bit 4RW0OCR2-3Timer/Counter2 Output Compare Register Bit 3RW0OCR2-2Timer/Counter2 Output Compare Register Bit 2RW0OCR2-1Timer/Counter2 Output Compare Register Bit 1RW0OCR2-0Timer/Counter2 Output Compare Register Bit 0RW0[TCCR0:TCNT0:OCR0:ASSR:TIMSK:TIFR]io_timer.bmpAt8pwm1TCCR0Timer/Counter Control Register0x330x53io_flag.bmpYPWM0Pulse Width Modulator EnableSetting this bit to 1 will enable the Pulse Width Modulator for Timer/Counter 0.RW0COM01Compare Match Output Mode 1These bits control the output compare pin (OC0) behavior. If one or both of the COM01:0 bits are set, the OC0 output over-rides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to OC0 pin must be set in order to enable the output driver. When OC0 is connected to the pin, the function of the COM01:0 bits depends on the WGM01:0 bit setting. Table 52 shows the COM01:0 bit functionality when the WGM01:0 bits are set to a normal or CTC mode (non-PWM)RW0COM00Compare match Output Mode 0These bits control the output compare pin (OC0) behavior. If one or both of the COM01:0 bits are set, the OC0 output over-rides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to OC0 pin must be set in order to enable the output driver. When OC0 is connected to the pin, the function of the COM01:0 bits depends on the WGM01:0 bit setting. Table 52 shows the COM01:0 bit functionality when the WGM01:0 bits are set to a normal or CTC mode (non-PWM)RW0CTC0CLear Timer/Counter on Compare MatchRW0CS02Clock Select 2The three clock select bits select the clock source to be used by the Timer/Counter,RW0CS01Clock Select 1The three clock select bits select the clock source to be used by the Timer/Counter,RW0CS00Clock Select 1The three clock select bits select the clock source to be used by the Timer/Counter,RW0TCNT0Timer/Counter Register The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT0 register blocks (removes) the compare match on the following timer clock. Modifying the counter (TCNT0) while the counter is running, introduces a risk of missing a compare match between TCNT0 the OCR0 register.0x320x52io_timer.bmpYTCNT0_7RW0TCNT0_6RW0TCNT0_5RW0TCNT0_4RW0TCNT0_3RW0TCNT0_2RW0TCNT0_1RW0TCNT0_0RW0OCR0Output Compare RegisterThe Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC0 pin.0x310x51io_timer.bmpNOCR0_7RW0OCR0_6RW0OCR0_5RW0OCR0_4RW0OCR0_3RW0OCR0_2RW0OCR0_1RW0OCR0_0RW0ASSRAsynchronus Status Register0x300x50io_flag.bmpYAS0Asynchronus Timer/Counter 0When AS0 is cleared, Timer/Counter 0 is clocked from the I/O clock, clk I/O . When AS0 is set, Timer/Counter 0 is clocked from a crystal oscillator connected to the Timer Oscillator 1 (TOSC1) pin. When the value of AS0 is changed, the contents of TCNT0, OCR0, and TCCR0 might be corrupted.RW0TCN0UBTimer/Couner0 Update BusyWhen Timer/Counter0 operates asynchronously and TCNT0 is written, this bit becomes set. When TCNT0 has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCNT0 is ready to be updated with a new value.RW0OCR0UBOutput Compare register 0 BusyWhen Timer/Counter0 operates asynchronously and OCR0 is written, this bit becomes set. When OCR0 has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that OCR0 is ready to be updated with a new value.RW0TCR0UBTimer/Counter Control Register 0 Update BusyWhen Timer/Counter0 operates asynchronously and TCCR0 is written, this bit becomes set. When TCCR0 has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCCR0 is ready to be updated with a new value. If a write is performed to any of the three Timer/Counter0 registers while its update busy flag is set, the updated value might get corrupted and cause an unintentional interrupt to occur.The mechanisms for reading TCNT0, OCR0, and TCCR0 are different. When reading TCNT0, the actual timer value is read. When reading OCR0 or TCCR0, the value in the temporary storage register is readRW0TIMSKTimer/Counter Interrupt Mask Register0x370x57io_flag.bmpYOCIE0Timer/Counter0 Output Compare Match Interrupt registerWhen the OCIE0 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Compare Match interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter0 occurs, i.e. when the OCF0 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.RW0TOIE0Timer/Counter0 Overflow Interrupt EnableWhen the TOIE0 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, i.e. when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.RW0TIFRTimer/Counter Interrupt Flag register0x360x56io_flag.bmpYOCF0Output Compare Flag 0The OCF0 bit is set (one) when a compare match occurs between the Timer/Counter0 and the data in OCR0 - Output Compare Register0. OCF0 is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF0 is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0 (Timer/Counter0 Compare match Interrupt Enable), and OCF0 are set (one), the Timer/Counter0 Compare match Interrupt is executed.RW0TOV0Timer/Counter0 Overflow FlagThe bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter0 changes counting direction at $00.RW0[TIMSK:TIFR:TCCR1A:TCCR1B:TCNT1H:TCNT1L:OCR1AH:OCR1AL:OCR1BH:OCR1BL:ICR1H:ICR1L]
[TCNT1H:TCNT1L];[OCR1AH:OCR1AL];[OCR1BH:OCR1BL];[ICR1H:ICR1L]
io_timer.bmpt16pwm1_2.xmlThe 16-bit Timer/Counter1 can select clock source from CK, prescaled CK, or an external pin. In addition it can be stopped as described in the specification for the Timer/Counter1 Control Registers - TCCR1A and TCCR1B. The different status flags (overflow, compare match and capture event) are found in the Timer/Counter Interrupt Flag Register - TIFR. Control signals are found in the Timer/Counter1 Control Registers - TCCR1A and TCCR1B. The interrupt enable/disable settings for Timer/Counter1 are found in the Timer/Counter Interrupt Mask Register - TIMSTIMSKTimer/Counter Interrupt Mask Register0x370x57io_flag.bmpYTICIE1Timer/Counter1 Input Capture Interrupt EnableWhen the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on pin 31, ICP, i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.RW0OCIE1ATimer/Counter1 Output CompareA Match Interrupt EnableWhen the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a CompareA match in Timer/Counter1 occurs, i.e., when the OCF1A bit is set in the Timer/Counter Interrupt Flag Register - TIFR.RW0OCIE1BTimer/Counter1 Output CompareB Match Interrupt EnableWhen the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter1 occurs, i.e., when the OCF1B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.R0TOIE1Timer/Counter1 Overflow Interrupt EnableWhen the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $006) is executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.RW0TIFRTimer/Counter Interrupt Flag register0x360x56io_flag.bmpYICF1Input Capture Flag 1The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to the input capture register - ICR1. ICF1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF1 is cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable), and ICF1 are set (one), the Timer/Counter1 Capture Interrupt is executed. RW0OCF1AOutput Compare Flag 1AThe OCF1A bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare match InterruptA Enable), and the OCF1A are set (one), the Timer/Counter1 Compare A match Interrupt is executed. RW0OCF1BOutput Compare Flag 1BThe OCF1B bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1B - Output Compare Register 1B. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1B (Timer/Counter1 Compare match InterruptB Enable), and the OCF1B are set (one), the Timer/Counter1 Compare B match Interrupt is executed.RW0TOV1Timer/Counter1 Overflow FlagThe TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the cor-responding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter1 changes counting direction at $0000.RW0TCCR1ATimer/Counter1 Control Register A0x2F0x4Fio_flag.bmpYCOM1A1Compare Output Mode 1A, bit 1The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA pin 1. This is an alternative function to an I/O port and the corresponding direction control bit must be set (one) to control the output pin. The control configuration is shown in Table 9. RW0COM1A0Compare Ouput Mode 1A, bit 0The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA pin 1. This is an alternative function to an I/O port and the corresponding direction control bit must be set (one) to control the output pin. The control configuration is shown in Table 9. RW0COM1B1Compare Output Mode 1B, bit 1The COM1B1 and COM1B0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B - Output CompareB.RW0COM1B0Compare Output Mode 1B, bit 0The COM1B1 and COM1B0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B - Output CompareB.RW0PWM11Pulse Width Modulator Select Bit 1RW0PWM10Pulse Width Modulator Select Bit 0RW0TCCR1BTimer/Counter1 Control Register B0x2E0x4Eio_flag.bmpYICNC1Input Capture 1 Noise CancelerWhen the ICNC1 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the ICP - input capture pin - as specified. When the ICNC1 bit is set (one), four successive samples are measures on the ICP - input capture pin, and all samples must be high/low according to the input capture trigger specification in the ICES1 bit. The actual sampling frequency is XTAL clock frequency.RW0ICES1Input Capture 1 Edge SelectWhile the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the falling edge of the input capture pin - ICP. While the ICES1 bit is set (one), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the rising edge of the input capture pin - ICP.RW0CTC1Clear Timer/Counter1 on Compare MatchWhen the CTC1 control bit is set (one), the Timer/Counter1 is reset to $0000 in the clock cycle after a compareA match. If the CTC1 control bit is cleared, Timer/Counter1 continues counting and is unaffected by a compare match. Since the compare match is detected in the CPU clock cycle following the match, this function will behave differently when a prescal-ing higher than 1 is used for the timer. When a prescaling of 1 is used, and the compareA register is set to C, the timer will count as follows if CTC1 is set: ...|C-2 |C-1 |C |0|1 |... When the prescaler is set to divide by 8, the timer will count like this: ... | C-2, C-2, C-2, C-2, C-2, C-2, C-2, C-2 | C-1, C-1, C-1, C-1, C-1, C-1, C-1, C-1 | C, 0, 0, 0, 0, 0, 0, 0 | ... In PWM mode, this bit has no effectRW0CS12Clock Select1 bit 2RW0CS11Clock Select1 bit 1RW0CS10Clock Select1 bit 0RW0TCNT1HTimer/Counter1 High ByteThis 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR1A, OCR1B and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program. <Please refer to the datasheet0x2D0x4Dio_timer.bmpNTCNT1H7Timer/Counter1 High Byte bit 7RW0TCNT1H6Timer/Counter1 High Byte bit 6RW0TCNT1H5Timer/Counter1 High Byte bit 5RW0TCNT1H4Timer/Counter1 High Byte bit 4RW0TCNT1H3Timer/Counter1 High Byte bit 3RW0TCNT1H2Timer/Counter1 High Byte bit 2RW0TCNT1H1Timer/Counter1 High Byte bit 1RW0TCNT1H0Timer/Counter1 High Byte bit 0RW0TCNT1LTimer/Counter1 Low ByteThis 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR1A, OCR1B and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program.<Please refer to the datasheet0x2C0x4Cio_timer.bmpNTCNT1L7Timer/Counter1 Low Byte bit 7RW0TCNT1L6Timer/Counter1 Low Byte bit 6RW0TCNT1L5Timer/Counter1 Low Byte bit 5RW0TCNT1L4Timer/Counter1 Low Byte bit 4RW0TCNT1L3Timer/Counter1 Low Byte bit 3RW0TCNT1L2Timer/Counter1 Low Byte bit 2RW0TCNT1L1Timer/Counter1 Low Byte bit 1RW0TCNT1L0Timer/Counter1 Low Byte bit 0RW0OCR1AHTimer/Counter1 Outbut Compare Register High ByteThe output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program. <Please refer to the datasheet0x2B0x4Bio_timer.bmpNOCR1AH7Timer/Counter1 Outbut Compare Register High Byte bit 7RW0OCR1AH6Timer/Counter1 Outbut Compare Register High Byte bit 6RW0OCR1AH5Timer/Counter1 Outbut Compare Register High Byte bit 5RW0OCR1AH4Timer/Counter1 Outbut Compare Register High Byte bit 4RW0OCR1AH3Timer/Counter1 Outbut Compare Register High Byte bit 3RW0OCR1AH2Timer/Counter1 Outbut Compare Register High Byte bit 2RW0OCR1AH1Timer/Counter1 Outbut Compare Register High Byte bit 1RW0OCR1AH0Timer/Counter1 Outbut Compare Register High Byte bit 0RW0OCR1ALTimer/Counter1 Output Compare Register Low ByteThe output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program .<Please refer to the datasheet0x2A0x4Aio_timer.bmpNOCR1AL7Timer/Counter1 Output Compare Register Low Byte Bit 7RW0OCR1AL6Timer/Counter1 Output Compare Register Low Byte Bit 6RW0OCR1AL5Timer/Counter1 Output Compare Register Low Byte Bit 5RW0OCR1AL4Timer/Counter1 Output Compare Register Low Byte Bit 4RW0OCR1AL3Timer/Counter1 Output Compare Register Low Byte Bit 3RW0OCR1AL2Timer/Counter1 Output Compare Register Low Byte Bit 2RW0OCR1AL1Timer/Counter1 Output Compare Register Low Byte Bit 1RW0OCR1AL0Timer/Counter1 Output Compare Register Low Byte Bit 0RW0OCR1BHTimer/Counter1 Output Compare Register High ByteThe output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program. <Please refer to the datasheet0x290x49io_timer.bmpNOCR1BH7Timer/Counter1 Output Compare Register High Byte bit 7RW0OCR1BH6Timer/Counter1 Output Compare Register High Byte bit 6RW0OCR1BH5Timer/Counter1 Output Compare Register High Byte bit 5RW0OCR1BH4Timer/Counter1 Output Compare Register High Byte bit 4RW0OCR1BH3Timer/Counter1 Output Compare Register High Byte bit 3RW0OCR1BH2Timer/Counter1 Output Compare Register High Byte bit 2RW0OCR1BH1Timer/Counter1 Output Compare Register High Byte bit 1RW0OCR1BH0Timer/Counter1 Output Compare Register High Byte bit 0RW0OCR1BLTimer/Counter1 Output Compare Register Low ByteThe output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program.<Please refer to the datasheet0x280x48io_timer.bmpNOCR1BL7Timer/Counter1 Output Compare Register Low Byte bit 7R0OCR1BL6Timer/Counter1 Output Compare Register Low Byte bit 6RW0OCR1BL5Timer/Counter1 Output Compare Register Low Byte bit 5RW0OCR1BL4Timer/Counter1 Output Compare Register Low Byte bit 4RW0OCR1BL3Timer/Counter1 Output Compare Register Low Byte bit 3RW0OCR1BL2Timer/Counter1 Output Compare Register Low Byte bit 2RW0OCR1BL1Timer/Counter1 Output Compare Register Low Byte bit 1RW0OCR1BL0Timer/Counter1 Output Compare Register Low Byte bit 0RW0ICR1HTimer/Counter1 Input Capture Register High ByteThe input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES1) of the signal at the input capture pin -ICP - is detected, the current value of the Timer/Counter1 is transferred to the Input Capture Register - ICR1. At the same time, the input capture flag - ICF1 - is set (one). Since the Input Capture Register - ICR1 - is a 16-bit register, a temporary register TEMP is used when ICR1 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR1L, the data is sent to the CPU and the data of the high byte ICR1H is placed in the TEMP register. When the CPU reads the data in the high byte ICR1H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR1L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT1, OCR1A and OCR1B. <Please refer to the datashee0x270x47io_timer.bmpNICR1H7Timer/Counter1 Input Capture Register High Byte bit 7RW0ICR1H6Timer/Counter1 Input Capture Register High Byte bit 6R0ICR1H5Timer/Counter1 Input Capture Register High Byte bit 5R0ICR1H4Timer/Counter1 Input Capture Register High Byte bit 4R0ICR1H3Timer/Counter1 Input Capture Register High Byte bit 3R0ICR1H2Timer/Counter1 Input Capture Register High Byte bit 2R0ICR1H1Timer/Counter1 Input Capture Register High Byte bit 1R0ICR1H0Timer/Counter1 Input Capture Register High Byte bit 0R0ICR1LTimer/Counter1 Input Capture Register Low ByteThe input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES1) of the signal at the input capture pin -ICP - is detected, the current value of the Timer/Counter1 is transferred to the Input Capture Register - ICR1. At the same time, the input capture flag - ICF1 - is set (one). Since the Input Capture Register - ICR1 - is a 16-bit register, a temporary register TEMP is used when ICR1 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR1L, the data is sent to the CPU and the data of the high byte ICR1H is placed in the TEMP register. When the CPU reads the data in the high byte ICR1H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR1L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT1, OCR1A and OCR1B. <Please refer to the datasheet0x260x46io_timer.bmpNICR1L7Timer/Counter1 Input Capture Register Low Byte bit 7R0ICR1L6Timer/Counter1 Input Capture Register Low Byte bit 6R0ICR1L5Timer/Counter1 Input Capture Register Low Byte bit 5R0ICR1L4Timer/Counter1 Input Capture Register Low Byte bit 4R0ICR1L3Timer/Counter1 Input Capture Register Low Byte bit 3R0ICR1L2Timer/Counter1 Input Capture Register Low Byte bit 2R0ICR1L1Timer/Counter1 Input Capture Register Low Byte bit 1R0ICR1L0Timer/Counter1 Input Capture Register Low Byte bit 0R0[UDR0:UCSR0A:UCSR0B:UBRR0L]
[UBRR0H:UBRR0L]
io_com.bmpThe Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. The main features are: • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • High Resolution Baud Rate Generator • Supports Serial Frames with 5, 6, 7, 8 or 9 Data Bits and 1 or 2 Stop Bits • Odd or Even Parity Generation and Parity Check Supported by Hardware • Data OverRun Detection • Framing Error Detection • Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter • Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete • Multi-processor Communication Mode • Double Speed Asynchronous CommuUDR0USART I/O Data RegisterThe UDR0 register is actually two physically separate registers sharing the same I/O address. When writing to the register, the USART Transmit Data register is written. When reading from UDR0, the USART Receive Data register is read.0x0C0x2Cio_com.bmpNUDR07USART I/O Data Register bit 7RW0UDR06USART I/O Data Register bit 6RW0UDR05USART I/O Data Register bit 5RW0UDR04USART I/O Data Register bit 4RW0UDR03USART I/O Data Register bit 3RW0UDR02USART I/O Data Register bit 2RW0UDR01USART I/O Data Register bit 1RW0UDR00USART I/O Data Register bit 0RW0UCSR0AUSART Control and Status Register A0x0B0x2Bio_flag.bmpYRXC0USART Receive CompleteThis bit is set (one) when a received character is transferred from the Receiver Shift register to UDR0. The bit is set regard-less of any detected framing errors. When the RXCIE bit in UCR is set, the USART Receive Complete interrupt will be executed when RXC is set(one). RXC is cleared by reading UDR0. When interrupt-driven data reception is used, the USART Receive Complete Interrupt routine must read UDR0 in order to clear RXC, otherwise a new interrupt will occur once the interrupt routine terminates.R0TXC0USART Transmitt CompleteThis bit is set (one) when the entire character (including the stop bit) in the Transmit Shift register has been shifted out and no new data has been written to UDR0. This flag is especially useful in half-duplex communications interfaces, where a transmitting application must enter receive mode and free the communications bus immediately after completing the transmission. When the TXCIE bit in UCR is set, setting of TXC causes the USART Transmit Complete interrupt to be executed. TXC is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the TXC bit is cleared (zero) by writing a logical one to thRW0UDRE0USART Data Register EmptyThis bit is set (one) when a character written to UDR0 is transferred to the Transmit shift register. Setting of this bit indicates that the transmitter is ready to receive a new character for transmission. When the UDR0IE bit in UCR is set, the USART Transmit Complete interrupt to be executed as long as UDR0E is set. UDR0E is cleared by writing UDR0. When interrupt-driven data transmittal is used, the USART Data Register Empty Interrupt routine must write UDR0 in order to clear UDR0E, otherwise a new interrupt will occur once the interrupt routine terminates. UDR0E is set (one) during reset to indicate that the transmitter is reR1FE0Framing ErrorThis bit is set if a Framing Error condition is detected, i.e. when the stop bit of an incoming character is zero. The FE bit is cleared when the stop bit of received data is one.R0DOR0Data overRunThis bit is set if an Overrun condition is detected, i.e. when a character already present in the UDR0 register is not read before the next character has been shifted into the Receiver Shift register. The OR bit is buffered, which means that it will be set once the valid data still in UDR0E is read. The OR bit is cleared (zero) when data is received and transferred to UDR0. R0UPE0Parity ErrorThis bit is set if the next character in the receive buffer had a Parity Error when received and the parity checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer (UDR0) is read. Always set this bit to zero when writing to UCSR0A.R0U2X0Double the USART transmission speedThis bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation. Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous communication.RW0MPCM0Multi-processor Communication ModeThis bit enables the Multi-processor Communication Mode. When the MPCM bit is written to one, all the incoming frames received by the USART receiver that do not contain address information will be ignored. The transmitter is unaffected by the MPCM setting. For more detailed information see “Multi-processor Communication Mode” on page 152.RW0UCSR0BUSART Control and Status Register B0x0A0x2Aio_flag.bmpYRXCIE0RX Complete Interrupt EnableWriting this bit to one enables interrupt on the RXC flag. A USART Receive Complete interrupt will be generated only if the RXCIE bit is written to one, the global interrupt flag in SREG is written to one and the RXC bit in UCSR0A is set.RW0TXCIE0TX Complete Interrupt EnableWriting this bit to one enables interrupt on the TXC flag. A USART Transmit Complete interrupt will be generated only if the TXCIE bit is written to one, the global interrupt flag in SREG is written to one and the TXC bit in UCSR0A is set.RW0UDRIE0USART Data register Empty Interrupt EnableWriting this bit to one enables interrupt on the UDR0E flag. A Data Register Empty interrupt will be generated only if the UDR0IE bit is written to one, the global interrupt flag in SREG is written to one and the UDR0E bit in UCSR0A is set.RW1RXEN0Receiver EnableWriting this bit to one enables the USART receiver. The receiver will override normal port operation for the RxD pin when enabled. Disabling the receiver will flush the receive buffer invalidating the FE, DOR and PE flags.RW0TXEN0Transmitter EnableWriting this bit to one enables the USART transmitter. The transmitter will override normal port operation for the TxD pin when enabled. The disabling of the transmitter (writing TXEN to zero) will not become effective until ongoing and pending transmissions are completed, i.e. when the transmit shift register and transmit buffer register does not contain data to be transmitted. When disabled, the transmitter will no longer override the TxD port.RW0UCSZ02Character SizeThe UCSZ2 bits combined with the UCSZ1:0 bit in UCSR0C sets the number of data bits (character size) in a frame the receiver and transmitter use.RW0RXB80Receive Data Bit 8RXB8 is the 9th data bit of the received character when operating with serial frames with 9 data bits. Must be read before reading the low bits from UDR0.R0TXB80Transmit Data Bit 8TXB8 is the 9th data bit in the character to be transmitted when operating with serial frames with 9 data bits. Must be writ-ten before writing the low bits to UDR0.W0UBRR0LUSART Baud Rate Register Low ByteThis is a 12-bit register which contains the USART baud rate. The UBRR0H contains the 4 most significant bits, and the UBRR0L contains the 8 least significant bits of the USART baud rate. Ongoing transmissions by the transmitter and receiver will be corrupted if the baud rate is changed. Writing UBRR0L will trigger an immediate update of the baud rate prescaler.0x090x29io_com.bmpNUBRR7USART Baud Rate Register bit 7RW0UBRR6USART Baud Rate Register bit 6RW0UBRR5USART Baud Rate Register bit 5RW0UBRR4USART Baud Rate Register bit 4RW0UBRR3USART Baud Rate Register bit 3RW0UBRR2USART Baud Rate Register bit 2RW0UBRR1USART Baud Rate Register bit 1RW0UBRR0USART Baud Rate Register bit 0RW0[EICRB:EIMSK:EIFR]io_ext.bmpThe external interrupts are triggered by the INT7:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT7:0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The external inter-rupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the Exter-nal Interrupt Control Registers - EICRA (INT3:0) and EICRB (INT7:4). When the external interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT7:4 requires the presence of an I/O clock, described in “Clock Systems and their Distribution” on page 29. Low level interrupts and the edge interrupt on INT3:0 are detected asynchronously. This implies that these inter-rupts can be used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode. Note that if a level triggered interrupt is used for wake-up from Power Down Mode, the changed level must be held for some time to wake up the MCU. This makes the MCU less sensitive to noise. The changed level is sampled twice by the watchdog oscillator clock. The period of the watchdog oscillator is 1 µs (nominal) at 5.0V and 25°C. The frequency of the watchdog oscillator is voltage dependent as shown in the Electrical Characteristics section. The MCU will wake up if the input has the required level during this sampling or if it is held until the end of the start-up time. The start-up time is defined by the SUT fuses as described in “Clock Systems and their Distribution” on page 29. If the level is sampled twice by the watchdog oscillator clock but disappears before the end of the start-up time, the MCU will still wake up, but no interrupt will be generated. The required level must be held long enough for the MCU to complete the wake up to trigger the level interruptEICRBExternal Interrupt Control Register BThe External Interrupts 7 - 4 are activated by the external pins INT7:4 if the SREG I-flag and the corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that activate the interrupts are defined in Table 49. The value on the INT7:4 pins are sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL divider is enabled. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an interrupt request as long as the pin is held low0x3A0x5Aio_flag.bmpYISC71External Interrupt 7-4 Sense Control BitRW0ISC70External Interrupt 7-4 Sense Control BitRW0ISC61External Interrupt 7-4 Sense Control BitRW0ISC60External Interrupt 7-4 Sense Control BitRW0ISC51External Interrupt 7-4 Sense Control BitRW0ISC50External Interrupt 7-4 Sense Control BitRW0ISC41External Interrupt 7-4 Sense Control BitRW0ISC40External Interrupt 7-4 Sense Control BitRW0EIMSKExternal Interrupt Mask RegisterWhen an INT7- INT4 bit is written to one and the I-bit in the Status Register (SREG) is set (one), the corresponding external pin interrupt is enabled. The Interrupt Sense Control bits in the External Interrupt Control Registers - EICRA and EICRB defines whether the external interrupt is activated on rising or falling edge or level sensed. Activity on any of these pins will trigger an interrupt request even if the pin is enabled as an output. This provides a way of generating a software interrupt. 0x390x59io_flag.bmpYINT7External Interrupt Request 7 EnableRW0INT6External Interrupt Request 6 EnableRW0INT5External Interrupt Request 5 EnableRW0INT4External Interrupt Request 4 EnableRW0INT3External Interrupt Request 3 EnableRW0INT2External Interrupt Request 2 EnableRW0INT1External Interrupt Request 1 EnableRW0INT0External Interrupt Request 0 EnableRW0EIFRExternal Interrupt Flag RegisterWhen an event on the INT7 - INT0 pins triggers an interrupt request, the corresponding interrupt flag, INTF7 - INTF0 becomes set (one). If the I-bit in SREG and the corresponding interrupt enable bit, INT7 - INT0 in EIMSK, are set (one), the MCU will jump to the interrupt vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag is cleared by writing a logical one to it. Note that when entering some sleep modes with the INT3:0 interrupts disabled, the input buffers on these pin will be disabled. This may cause a logic change in internal signals which will set the INTF3:0 flags. See “Digital Input Enable and Sleep Modes” on page 54 for more informa0x380x58io_flag.bmpYINTF7External Interrupt Flag 7RW0INTF6External Interrupt Flag 6RW0INTF5External Interrupt Flag 5RW0INTF4External Interrupt Flag 4RW0INTF3External Interrupt Flag 3RW0INTF2External Interrupt Flag 2RW0INTF1External Interrupt Flag 1RW0INTF0External Interrupt Flag 0RW0[SREG:SPH:SPL:MCUCR:XDIV:MCUCSR:RAMPZ]
[SPH:SPL]
io_cpu.bmpSREGStatus Register0x3F0x5Fio_sreg.bmpYIGlobal Interrupt EnableThe global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable bit is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts.RW0TBit Copy StorageThe bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction.RW0HHalf Carry FlagThe half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed information.RW0SSign BitThe S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruc-tion Set Description for detailed information.RW0VTwo's Complement Overflow FlagThe two’s complement overflow flag V supports two’s complement arithmetics. See the Instruction Set Description for detailed information.RW0NNegative FlagThe negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.RW0ZZero FlagThe zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.RW0CCarry FlagThe carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software.RW0SPHStack Pointer HighThe general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the AT90S4414/8515 supports up to 64 kB external SRAM, all 16-bits are used. The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or return from interrupt R0x3E0x5Eio_sph.bmpNSP15Stack pointer bit 15RW0SP14Stack pointer bit 14RW0SP13Stack pointer bit 13RW0SP12Stack pointer bit 12RW0SP11Stack pointer bit 11RW0SP10Stack pointer bit 10RW0SP9Stack pointer bit 9RW0SP8Stack pointer bit 8RW0SPLStack Pointer LowThe general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the AT90S4414/8515 supports up to 64 kB external SRAM, all 16-bits are used. The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or return from interrupt 0x3D0x5Dio_sph.bmpNSP7Stack pointer bit 7RW0SP6Stack pointer bit 6RW0SP5Stack pointer bit 5RW0SP4Stack pointer bit 4RW0SP3Stack pointer bit 3RW0SP2Stack pointer bit 2RW0SP1Stack pointer bit 1RW0SP0Stack pointer bit 0RW0MCUCRMCU Control RegisterThe MCU Control Register contains control bits for general MCU functions.0x350x55io_flag.bmpYSREExternal SRAM EnableWriting SRE to one enables the External Memory Interface.The pin functions AD7:0, A15:8, ALE, WR, and RD are acti-vated as the alternate pin functions. The SRE bit overrides any pin direction settings in the respective data direction regis-ters. Writing SRE to zero, disables the External Memory Interface and the normal pin and data direction settings are used.RW0SRW10External SRAM Wait State SelectFor a detailed description in non ATmega103 Compatibility mode, see common description for the SRWn bits below (XMRA description). In ATmega103 Compatibility mode, writing SRW10 to one enables the wait state and one extra cycle is added during read/write strobe as shown in Figure 14.RW0SESleep EnableRW0SM1Sleep Mode SelectThe description is to long for the tooltip help, please refer to the manualRW0SM0Sleep Mode SelectThe description is to long for the tooltip help, please refer to the manualRW0SM2Sleep Mode SelectThe description is to long for the tooltip help, please refer to the manualRW0IVSELInterrupt Vector SelectWhen the IVSEL bit is cleared (zero), the interrupt vectors are placed at the start of the Flash memory. When this bit is set (one), the interrupt vectors are moved to the beginning of the Boot Loader section of the flash. The actual address of the start of the boot flash section is determined by the BOOTSZ fuses. Refer to the section “Boot Loader Support - Read While Write self-programming” on page 228 for details. To avoid unintentional changes of interrupt vector tables, a special write procedure must be followed to change the IVSEL bit: 1. Write the Interrupt Vector Change Enable (IVCE) bit to one. 2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE. Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts remain dis-abled for four cycles. The I-bit in the Status Register is unaffected by the automatic disabling. Note: Note: If interrupt vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed, interrupts are disabled while executing from the Application section. If interrupt vectors are placed in the Application section and Boot Lock bit BLB01 is pro-gramed, interrupts are disabled while executing from the Boot Loader section. Refer to the section “Boot Loader Support - Read While Write self-programming” on page 228 for details on Boot Lock bitsRW0IVCEInterrupt Vector Change EnableThe IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above.RW0MCUCSRMCU Control And Status RegisterThe MCU Control And Status Register provides information on which reset source caused a MCU reset.0x340x54io_flag.bmpYEXTRFExternal Reset FlagThis bit is set if an external reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.R/W0PORFPower-on reset flagThis bit is set if a power-on reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the reset flags to identify a reset condition, the user should read and then reset the MCUCSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags.R/W0XDIVXTAL Divide Control RegisterThe XTAL Divide Control Register is used to divide the Source clock frequency by a number in the range 1 - 129. This fea-ture can be used to decrease power consumption when the requirement for processing power is low.0x3C0x5Cio_cpu.bmpNXDIVENXTAL Divide EnableWhen the XDIVEN bit is written one, the clock frequency of the CPU and all peripherals (clk I/O , clk ADC , clk CPU , clk FLASH ) is divided by the factor defined by the setting of XDIV6 - XDIV0. This bit can be written run-time to vary the clock frequency as suitable to the application.R/W0XDIV6XTAl Divide Select Bit 6These bits define the division factor that applies when the XDIVEN bit is set (one). Please refer to the manual for details on the formulas.R/W0XDIV5XTAl Divide Select Bit 5These bits define the division factor that applies when the XDIVEN bit is set (one). Please refer to the manual for details on the formulas.R/W0XDIV4XTAl Divide Select Bit 4These bits define the division factor that applies when the XDIVEN bit is set (one). Please refer to the manual for details on the formulas.R/W0XDIV3XTAl Divide Select Bit 3These bits define the division factor that applies when the XDIVEN bit is set (one). Please refer to the manual for details on the formulas.R/W0XDIV2XTAl Divide Select Bit 2These bits define the division factor that applies when the XDIVEN bit is set (one). Please refer to the manual for details on the formulas.R/W0XDIV1XTAl Divide Select Bit 1These bits define the division factor that applies when the XDIVEN bit is set (one). Please refer to the manual for details on the formulas.R/W0XDIV0XTAl Divide Select Bit 0These bits define the division factor that applies when the XDIVEN bit is set (one). Please refer to the manual for details on the formulas.R/W0RAMPZRAM Page Z Select Register0x3B0x5Bio_cpu.bmpYRAMPZ0RAM Page Z Select Register Bit 0The RAMPZ register is normally used to select which 64K RAM Page is accessed by the Z pointer. As the ATmega104 does not support more than 64K of SRAM memory, this register is used only to select which page in the program memory is accessed when the ELPM/SPM instruction is used. The different settings of the RAMPZ0 bit have the following effects: Note that LPM is not affected by the RAMPZ setting. RAMPZ0 = 0: Program memory address $0000- $7FFF (lower 64K bytes) is accessed by ELPM/SPM RAMPZ0 = 1: Program memory address $8000- $FFFF (higher 64K bytes) is accessed by ELPM/RW0[ICE50]0x050x0F0x0F0x0F0x050x050x050x050x050x050x050x050x050x0F0x0F0x0F0x150x140x140x00000FFF0x000000000x000000000x000000000x00000FFF0x0001FFFF0x0000FFFF0x0000FFFF0x0000FFFF0x0000FFFF0x0000FFFF0x0000FFFF0x00000FFF0x000000000x000000000x000000000x0023FFFF0x00000FFF0x000000FF0x0000FFFF0x000000000x000000000x000000000x00000FFF0x0001FFFF0x0000FFFF0x0000FFFF0x0000FFFF0x0000FFFF0x0000FFFF0x0000FFFF0x00000FFF0x000000000x000000000x000000000x0023FFFF0x00000FFF0x000000FF0x00000FFF0x000000000x000000000x000000000x00000FFF0x0001FFFF0x0000FFFF0x0000FFFF0x0000FFFF0x0000FFFF0x0000FFFF0x0000FFFF0x00000FFF0x000000000x000000000x000000000x0023FFFF0x00000FFF0x0000FFFF0xF90xfd0xE10xff0x6f0xc7ATmega128.bin0x020x0010000004000000072 ; INTOSC = 1, INTRC=2;EXTCLK=41 ;NOTUSE = 1, EXTERNAL = 4, INTERNAL = 2 1 00x000x010x000000310x00000000258 CK, 4 ms 0x000000310x00000010258 CK, 64 ms0x000000310x000000201K CK0x000000310x000000301K CK, 4 ms0x000000310x000000011K CK, 64 ms0x000000310x0000001116K CK0x000000310x0000002116K CK, 4 ms0x000000310x0000003116K CK, 64 ms0x000000300x000000006 CK0x000000300x000000106 CK, 4 ms0x000000300x000000206 CK, 64 ms0x000000300x000000006 CK0x000000300x000000106 CK0x000000300x000000206 CK, 64 ms0x0000103f0x0000002b0x0000103f0x000010211.00x0000103f0x000010222.00x0000103f0x000010234.00x0000103f0x000010248.00x0000103f0x000010200x000000C00x000000C0BOD disabled0x000000C00x00000080BOD enabled, 2.7 V0x000000C00x00000000BOD enabled, 4.0 V