[ADMIN:CORE:FUSE:INTERRUPT_VECTOR:MEMORY:PACKAGE:POWER:PROGVOLT:LOCKBIT:PROGRAMMING:IO_MODULE:ICE_SETTINGS] ATmega128 16MHz 243 RELEASED $1E $97 $02 ATmega103comp ATmega128 V2E AVRSimCoreV2.SimCoreV2 [] [] [] 32 $00 $1B $1A $1D $1C $1F $1E [LOW:HIGH:EXTENDED] 8 BODLEVEL Brown out detector trigger level 1 BODEN Brown out detector enable 1 SUT1 Select start-up time 0 SUT0 Select start-up time 0 CKSEL3 Select Clock Source 0 CKSEL2 Select Clock Source 0 CKSEL1 Select Clock Source 0 CKSEL0 Select Clock Source 1 61 0x80 0x00 Brown-out detection level at VCC=4.0 V; [BODLEVEL=0] 0x80 0x80 Brown-out detection level at VCC=2.7 V; [BODLEVEL=1] 0x40 0x00 Brown-out detection enabled; [BODEN=0] 0x3F 0x00 Ext. Clock; Start-up time: 6 CK + 0 ms; [CKSEL=0000 SUT=00] 0x3F 0x10 Ext. Clock; Start-up time: 6 CK + 4 ms; [CKSEL=0000 SUT=01] 0x3F 0x20 Ext. Clock; Start-up time: 6 CK + 64 ms; [CKSEL=0000 SUT=10] 0x3F 0x01 Int. RC Osc. 1 MHz; Start-up time: 6 CK + 0 ms; [CKSEL=0001 SUT=00] 0x3F 0x11 Int. RC Osc. 1 MHz; Start-up time: 6 CK + 4 ms; [CKSEL=0001 SUT=01] 0x3F 0x21 Int. RC Osc. 1 MHz; Start-up time: 6 CK + 64 ms; [CKSEL=0001 SUT=10]; default value 0x3F 0x02 Int. RC Osc. 2 MHz; Start-up time: 6 CK + 0 ms; [CKSEL=0010 SUT=00] 0x3F 0x12 Int. RC Osc. 2 MHz; Start-up time: 6 CK + 4 ms; [CKSEL=0010 SUT=01] 0x3F 0x22 Int. RC Osc. 2 MHz; Start-up time: 6 CK + 64 ms; [CKSEL=0010 SUT=10] 0x3F 0x03 Int. RC Osc. 4 MHz; Start-up time: 6 CK + 0 ms; [CKSEL=0011 SUT=00] 0x3F 0x13 Int. RC Osc. 4 MHz; Start-up time: 6 CK + 4 ms; [CKSEL=0011 SUT=01] 0x3F 0x23 Int. RC Osc. 4 MHz; Start-up time: 6 CK + 64 ms; [CKSEL=0011 SUT=10] 0x3F 0x04 Int. RC Osc. 8 MHz; Start-up time: 6 CK + 0 ms; [CKSEL=0100 SUT=00] 0x3F 0x14 Int. RC Osc. 8 MHz; Start-up time: 6 CK + 4 ms; [CKSEL=0100 SUT=01] 0x3F 0x24 Int. RC Osc. 8 MHz; Start-up time: 6 CK + 64 ms; [CKSEL=0100 SUT=10] 0x3F 0x05 Ext. RC Osc. - 0.9 MHz; Start-up time: 18 CK + 0 ms; [CKSEL=0101 SUT=00] 0x3F 0x15 Ext. RC Osc. - 0.9 MHz; Start-up time: 18 CK + 4 ms; [CKSEL=0101 SUT=01] 0x3F 0x25 Ext. RC Osc. - 0.9 MHz; Start-up time: 18 CK + 64 ms; [CKSEL=0101 SUT=10] 0x3F 0x35 Ext. RC Osc. - 0.9 MHz; Start-up time: 6 CK + 4 ms; [CKSEL=0101 SUT=11] 0x3F 0x06 Ext. RC Osc. 0.9 MHz - 3.0 MHz; Start-up time: 18 CK + 0 ms; [CKSEL=0110 SUT=00] 0x3F 0x16 Ext. RC Osc. 0.9 MHz - 3.0 MHz; Start-up time: 18 CK + 4 ms; [CKSEL=0110 SUT=01] 0x3F 0x26 Ext. RC Osc. 0.9 MHz - 3.0 MHz; Start-up time: 18 CK + 64 ms; [CKSEL=0110 SUT=10] 0x3F 0x36 Ext. RC Osc. 0.9 MHz - 3.0 MHz; Start-up time: 6 CK + 4 ms; [CKSEL=0110 SUT=11] 0x3F 0x07 Ext. RC Osc. 3.0 MHz - 8.0 MHz; Start-up time: 18 CK + 0 ms; [CKSEL=0111 SUT=00] 0x3F 0x17 Ext. RC Osc. 3.0 MHz - 8.0 MHz; Start-up time: 18 CK + 4 ms; [CKSEL=0111 SUT=01] 0x3F 0x27 Ext. RC Osc. 3.0 MHz - 8.0 MHz; Start-up time: 18 CK + 64 ms; [CKSEL=0111 SUT=10] 0x3F 0x37 Ext. RC Osc. 3.0 MHz - 8.0 MHz; Start-up time: 6 CK + 4 ms; [CKSEL=0111 SUT=11] 0x3F 0x08 Ext. RC Osc. 8.0 MHz - 12.0 MHz; Start-up time: 18 CK + 0 ms; [CKSEL=1000 SUT=00] 0x3F 0x18 Ext. RC Osc. 8.0 MHz - 12.0 MHz; Start-up time: 18 CK + 4 ms; [CKSEL=1000 SUT=01] 0x3F 0x28 Ext. RC Osc. 8.0 MHz - 12.0 MHz; Start-up time: 18 CK + 64 ms; [CKSEL=1000 SUT=10] 0x3F 0x38 Ext. RC Osc. 8.0 MHz - 12.0 MHz; Start-up time: 6 CK + 4 ms; [CKSEL=1000 SUT=11] 0x3F 0x09 Ext. Low-Freq. Crystal; Start-up time: 1K CK + 4 ms; [CKSEL=1001 SUT=00] 0x3F 0x19 Ext. Low-Freq. Crystal; Start-up time: 1K CK + 64 ms; [CKSEL=1001 SUT=01] 0x3F 0x29 Ext. Low-Freq. Crystal; Start-up time: 32K CK + 64 ms; [CKSEL=1001 SUT=10] 0x3F 0x0A Ext. Crystal/Resonator Low Freq.; Start-up time: 258 CK + 4 ms; [CKSEL=1010 SUT=00] 0x3F 0x1A Ext. Crystal/Resonator Low Freq.; Start-up time: 258 CK + 64 ms; [CKSEL=1010 SUT=01] 0x3F 0x2A Ext. Crystal/Resonator Low Freq.; Start-up time: 1K CK + 0 ms; [CKSEL=1010 SUT=10] 0x3F 0x3A Ext. Crystal/Resonator Low Freq.; Start-up time: 1K CK + 4 ms; [CKSEL=1010 SUT=11] 0x3F 0x0B Ext. Crystal/Resonator Low Freq.; Start-up time: 1K CK + 64 ms; [CKSEL=1011 SUT=00] 0x3F 0x1B Ext. Crystal/Resonator Low Freq.; Start-up time: 16K CK + 0 ms; [CKSEL=1011 SUT=01] 0x3F 0x2B Ext. Crystal/Resonator Low Freq.; Start-up time: 16K CK + 4 ms; [CKSEL=1011 SUT=10] 0x3F 0x3B Ext. Crystal/Resonator Low Freq.; Start-up time: 16K CK + 64 ms; [CKSEL=1011 SUT=11] 0x3F 0x0C Ext. Crystal/Resonator Medium Freq.; Start-up time: 258 CK + 4 ms; [CKSEL=1100 SUT=00] 0x3F 0x1C Ext. Crystal/Resonator Medium Freq.; Start-up time: 258 CK + 64 ms; [CKSEL=1100 SUT=01] 0x3F 0x2C Ext. Crystal/Resonator Medium Freq.; Start-up time: 1K CK + 0 ms; [CKSEL=1100 SUT=10] 0x3F 0x3C Ext. Crystal/Resonator Medium Freq.; Start-up time: 1K CK + 4 ms; [CKSEL=1100 SUT=11] 0x3F 0x0D Ext. Crystal/Resonator Medium Freq.; Start-up time: 1K CK + 64 ms; [CKSEL=1101 SUT=00] 0x3F 0x1D Ext. Crystal/Resonator Medium Freq.; Start-up time: 16K CK + 0 ms; [CKSEL=1101 SUT=01] 0x3F 0x2D Ext. Crystal/Resonator Medium Freq.; Start-up time: 16K CK + 4 ms; [CKSEL=1101 SUT=10] 0x3F 0x3D Ext. Crystal/Resonator Medium Freq.; Start-up time: 16K CK + 64 ms; [CKSEL=1101 SUT=11] 0x3F 0x0E Ext. Crystal/Resonator High Freq.; Start-up time: 258 CK + 4 ms; [CKSEL=1110 SUT=00] 0x3F 0x1E Ext. Crystal/Resonator High Freq.; Start-up time: 258 CK + 64 ms; [CKSEL=1110 SUT=01] 0x3F 0x2E Ext. Crystal/Resonator High Freq.; Start-up time: 1K CK + 0 ms; [CKSEL=1110 SUT=10] 0x3F 0x3E Ext. Crystal/Resonator High Freq.; Start-up time: 1K CK + 4 ms; [CKSEL=1110 SUT=11] 0x3F 0x0F Ext. Crystal/Resonator High Freq.; Start-up time: 1K CK + 64 ms; [CKSEL=1111 SUT=00] 0x3F 0x1F Ext. Crystal/Resonator High Freq.; Start-up time: 16K CK + 0 ms; [CKSEL=1111 SUT=01] 0x3F 0x2F Ext. Crystal/Resonator High Freq.; Start-up time: 16K CK + 4 ms; [CKSEL=1111 SUT=10] 0x3F 0x3F Ext. Crystal/Resonator High Freq.; Start-up time: 16K CK + 64 ms; [CKSEL=1111 SUT=11] 8 OCDEN Enable OCD 1 JTAGEN Enable JTAG 0 SPIEN Enable Serial programming and Data Downloading 0 CKOPT Oscillator Options 1 EESAVE EEPROM memory is preserved through chip erase 1 BOOTSZ1 Select Boot Size 0 BOOTSZ0 Select Boot Size 0 BOOTRST Select Reset Vector 1 10 0x80 0x00 On-Chip Debug Enabled; [OCDEN=0] 0x40 0x00 JTAG Interface Enabled; [JTAGEN=0] 0x20 0x00 Serial program downloading (SPI) enabled; [SPIEN=0] 0x08 0x00 Preserve EEPROM memory through the Chip Erase cycle; [EESAVE=0] 0x06 0x06 Boot Flash section size=512 words Boot start address=$FE00; [BOOTSZ=11] 0x06 0x04 Boot Flash section size=1024 words Boot start address=$FC00; [BOOTSZ=10] 0x06 0x02 Boot Flash section size=2048 words Boot start address=$F800; [BOOTSZ=01] 0x06 0x00 Boot Flash section size=4096 words Boot start address=$F000; [BOOTSZ=00] ; default value 0x01 0x00 Boot Reset vector Enabled (default address=$0000); [BOOTRST=0] 0x10 0x00 CKOPT fuse (operation dependent of CKSEL fuses); [CKOPT=0] 2 M103C ATmega103 compatibility mode 0 WDTON Watchdog timer always on 1 2 0x02 0x00 ATmega103 Compatibility Mode [M103C=0] 0x01 0x00 Watchdog Timer always on; [WDTON=0] 35 AVRSimInterrupt.SimInterrupt $0000 RESET External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset and JTAG AVR Reset $0002 INT0 External Interrupt Request 0 $0004 INT1 External Interrupt Request 1 $0006 INT2 External Interrupt Request 2 $0008 INT3 External Interrupt Request 3 $000A INT4 External Interrupt Request 4 $000C INT5 External Interrupt Request 5 $000E INT6 External Interrupt Request 6 $0010 INT7 External Interrupt Request 7 $0012 TIMER2 COMP Timer/Counter2 Compare Match $0014 TIMER2 OVF Timer/Counter2 Overflow $0016 TIMER1 CAPT Timer/Counter1 Capture Event $0018 TIMER1 COMPA Timer/Counter1 Compare Match A $001A TIMER1 COMPB Timer/Counter Compare Match B $001C TIMER1 OVF Timer/Counter1 Overflow $001E TIMER0 COMP Timer/Counter0 Compare Match $0020 TIMER0 OVF Timer/Counter0 Overflow $0022 SPI, STC SPI Serial Transfer Complete $0024 USART0, RX USART0, Rx Complete $0026 USART0, UDRE USART0 Data Register Empty $0028 USART0, TX USART0, Tx Complete $002A ADC ADC Conversion Complete $002C EE READY EEPROM Ready $002E ANALOG COMP Analog Comparator $0030 TIMER1 COMPC Timer/Counter1 Compare Match C $0032 TIMER3 CAPT Timer/Counter3 Capture Event $0034 TIMER3 COMPA Timer/Counter3 Compare Match A $0036 TIMER3 COMPB Timer/Counter3 Compare Match B $0038 TIMER3 COMPC Timer/Counter3 Compare Match C $003A TIMER3 OVF Timer/Counter3 Overflow $003C USART1, RX USART1, Rx Complete $003E USART1, UDRE USART1, Data Register Empty $0040 USART1, TX USART1, Tx Complete $0042 TWI 2-wire Serial Interface $0044 SPM READY Store Program Memory Read 131072 4096 4096 $0100 4000 $0060 65536 $1100 65536 $1000 $0000 $003F $0060 $00FF $0020 $00FF NA 0x9D 0x010x020x040x080x100x200x40 NA 0x9C 0x010x020x040x080x100x200x400x80 NA 0x9B 0x010x020x040x080x100x200x400x80 NA 0x9A 0x010x020x040x080x100x200x400x80 NA 0x99 0x010x020x040x080x100x200x400x80 NA 0x98 0x010x020x040x08 NA 0x95 0x010x020x040x080x100x200x40 NA 0x90 0x010x020x040x08 NA 0x8C 0x200x400x80 NA 0x8B 0x010x020x040x080x100x200x400x80 NA 0x8A 0x010x020x040x080x100x400x80 NA 0x89 0x010x020x040x080x100x200x400x80 NA 0x88 0x010x020x040x080x100x200x400x80 NA 0x87 0x010x020x040x080x100x200x400x80 NA 0x86 0x010x020x040x080x100x200x400x80 NA 0x85 0x010x020x040x080x100x200x400x80 NA 0x84 0x010x020x040x080x100x200x400x80 NA 0x83 0x010x020x040x080x100x200x400x80 NA 0x82 0x010x020x040x080x100x200x400x80 NA 0x81 0x010x020x040x080x100x200x400x80 NA 0x80 0x010x020x040x080x100x200x400x80 NA 0x7D 0x010x020x040x080x100x20 NA 0x7C 0x010x020x040x080x100x20 NA 0x7A 0x200x400x80 NA 0x79 0x010x020x040x080x100x200x400x80 NA 0x78 0x010x020x040x080x100x200x400x80 NA 0x74 0x010x040x080x100x200x400x80 NA 0x73 0x010x020x040x080x100x200x400x80 NA 0x72 0x010x020x040x080x100x200x400x80 NA 0x71 0x010x020x080x100x200x400x80 NA 0x70 0x010x020x040x080x100x200x400x80 NA 0x6F 0x010x020x040x080x100x200x400x80 NA 0x6D 0x020x040x080x100x200x40 NA 0x6C 0x010x020x040x80 NA 0x6A 0x010x020x040x080x100x200x400x80 NA 0x68 0x010x020x040x080x100x400x80 NA 0x65 0x010x020x040x080x10 NA 0x64 0x010x020x040x080x10 NA 0x63 0x010x020x040x080x10 NA 0x62 0x010x020x040x080x100x200x400x80 NA 0x61 0x010x020x040x080x100x200x400x80 0x3F 0x5F 0x010x020x040x080x100x200x400x80 0x3E 0x5E 0x010x020x040x080x100x200x400x80 0x3D 0x5D 0x010x020x040x080x100x200x400x80 0x3C 0x5C 0x010x020x040x080x100x200x400x80 0x3B 0x5B 0x01 0x3A 0x5A 0x010x020x040x080x100x200x400x80 0x39 0x59 0x010x020x040x080x100x200x400x80 0x38 0x58 0x010x020x040x080x100x200x400x80 0x37 0x57 0x010x020x040x080x100x200x400x80 0x36 0x56 0x010x020x040x080x100x200x400x80 0x35 0x55 0x010x020x040x080x100x200x400x80 0x34 0x54 0x010x020x040x080x100x80 0x33 0x53 0x010x020x040x080x100x200x400x80 0x32 0x52 0x010x020x040x080x100x200x400x80 0x31 0x51 0x010x020x040x080x100x200x400x80 0x30 0x50 0x010x020x040x08 0x2F 0x4F 0x010x020x040x080x100x200x400x80 0x2E 0x4E 0x010x020x040x080x100x400x80 0x2D 0x4D 0x010x020x040x080x100x200x400x80 0x2C 0x4C 0x010x020x040x080x100x200x400x80 0x2B 0x4B 0x010x020x040x080x100x200x400x80 0x2A 0x4A 0x010x020x040x080x100x200x400x80 0x29 0x49 0x010x020x040x080x100x200x400x80 0x28 0x48 0x010x020x040x080x100x200x400x80 0x27 0x47 0x010x020x040x080x100x200x400x80 0x26 0x46 0x010x020x040x080x100x200x400x80 0x25 0x45 0x010x020x040x080x100x200x400x80 0x24 0x44 0x010x020x040x080x100x200x400x80 0x23 0x43 0x010x020x040x080x100x200x400x80 0x22 0x42 0x010x020x040x080x100x200x400x80 0x21 0x41 0x010x020x040x080x10 0x20 0x40 0x080x010x020x040x80 0x1F 0x3F 0x010x020x040x08 0x1E 0x3E 0x010x020x040x080x100x200x400x80 0x1D 0x3D 0x010x020x040x080x100x200x400x80 0x1C 0x3C 0x010x020x040x08 0x1B 0x3B 0x010x020x040x080x100x200x400x80 0x1A 0x3A 0x010x020x040x080x100x200x400x80 0x19 0x39 0x010x020x040x080x100x200x400x80 0x18 0x38 0x010x020x040x080x100x200x400x80 0x17 0x37 0x010x020x040x080x100x200x400x80 0x16 0x36 0x010x020x040x080x100x200x400x80 0x15 0x35 0x010x020x040x080x100x200x400x80 0x14 0x34 0x010x020x040x080x100x200x400x80 0x13 0x33 0x010x020x040x080x100x200x400x80 0x12 0x32 0x010x020x040x080x100x200x400x80 0x11 0x31 0x010x020x040x080x100x200x400x80 0x10 0x30 0x010x020x040x080x100x200x400x80 0x0F 0x2F 0x010x020x040x080x100x200x400x80 0x0E 0x2E 0x010x400x80 0x0D 0x2D 0x010x020x040x080x100x200x400x80 0x0C 0x2C 0x010x020x040x080x100x200x400x80 0x0B 0x2B 0x010x020x040x080x100x200x400x80 0x0A 0x2A 0x010x020x040x080x100x200x400x80 0x09 0x29 0x010x020x040x080x100x200x400x80 0x08 0x28 0x010x020x040x080x100x200x400x80 0x07 0x27 0x010x020x040x080x100x200x400x80 0x06 0x26 0x010x020x040x080x100x200x400x80 0x05 0x25 0x010x020x040x080x100x200x400x80 0x04 0x24 0x010x020x040x080x100x200x400x80 0x03 0x23 0x010x020x040x080x100x200x400x80 0x02 0x22 0x010x020x040x080x100x200x400x80 0x01 0x21 0x010x020x040x080x100x200x400x80 0x00 0x20 0x010x020x040x080x100x200x400x80 $F000 $FFFF $0 $EFFF 128 512 4 $0 $FE00 $FE00 1024 8 $0 $FC00 $FC00 2048 16 0 $F800 $F800 4096 32 0 $F000 $F000 [TQFP] 64 ['PEN] [PE0:RXD0:PDI] PDI, Serial Programming Data Input. During Serial Program Downloading, this pin is used as data input line for the ATmega104. RXD0, USART0 Receive Pin. Receive Data (Data input pin for the USART0). When the USART0 receiver is enabled this pin is configured as an input regardless of the value of DDRE0. When the USART0 forces this pin to be an input, a logical one in PORTE0 will turn on the internal pull-up. [PE1:TXD0:PDO] PDO, Serial Programming Data Output. During Serial Program Downloading, this pin is used as data output line for the ATmega104. TXD0, UART0 Transmit Pin. [PE2:XCK0:AIN0] AIN0 - Analog Comparator Positive Input. This pin is directly connected to the positive input of the analog comparator. XCK0, USART0 external clock. The Data Direction Register (DDE2) controls whether the clock is output (DDE2 set) or input (DDE2 cleared). The XCK0 pin is active only when the USART0 operates in synchronous mode. [PE3:OC3A:AIN1] AIN1 - Analog Comparator Negative Input. This pin is directly connected to the negative input of the analog comparator. OC3A, Output Compare matchA output: The PE3 pin can serve as an external output for the Timer/Counter3 output com-pareA. The pin has to be configured as an output (DDE3 set (one)) to serve this function. The OC3A pin is also the output pin for the PWM mode timer function. [PE4:OC3B:INT4] INT4, External Interrupt source 4: The PE4 pin can serve as an external interrupt source. OC3B, Output Compare matchB output: The PE4 pin can serve as an external output for the Timer/Counter3 output com-pareB. The pin has to be configured as an output (DDE4 set (one)) to serve this function. The OC3B pin is also the output pin for the PWM mode timer function. [PE5:OC3C:INT5] INT5, External Interrupt source 5: The PE5 pin can serve as an external interrupt source. OC3C, Output Compare matchC output: The PE5 pin can serve as an external output for the Timer/Counter3 output com-pareC. The pin has to be configured as an output (DDE5 set (one)) to serve this function. The OC3C pin is also the output pin for the PWM mode timer function. [PE6:T3:INT6] INT6, External Interrupt source 6: The PE6 pin can serve as an external interrupt source. T3, Timer/Counter3 counter source. [PE7:IC3:INT7] INT7, External Interrupt source 7: The PE7 pin can serve as an external interrupt source. IC3 - Input Capture Pin3: The PE7 pin can act as an input capture pin for Timer/Counter3. [PB0:'SS] SS: Slave port select input. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB0. As a slave, the SPI is activated when this pin is driven low. When the SPI is enabled as a master, the data direc-tion of this pin is controlled by DDB0. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB0 bit. [PB1:SCK] SCK: Master clock output, slave clock input pin for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB1. When the SPI is enabled as a master, the data direction of this pin is con-trolled by DDB1. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB1 bit. [PB2:MOSI] MOSI: SPI Master data output, slave data input for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB2. When the SPI is enabled as a master, the data direction of this pin is con-trolled by DDB2. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB2 bit. [PB3:MISO] MISO: Master data input, slave data output pin for SPI channel. When the SPI is enabled as a master, this pin is configured as an input regardless of the setting of DDB3. When the SPI is enabled as a slave, the data direction of this pin is controlled by DDB3. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB3 bit. [PB4:OC0:PWM0] OC0, Output Compare match output: The PB4 pin can serve as an external output for the Timer/Counter0 output compare. The pin has to be configured as an output (DDB4 set (one)) to serve this function. The OC0 pin is also the output pin for the PWM mode timer function. [PB5:OC1A:PWM1A] OC1A, Output Compare matchA output: The PB5 pin can serve as an external output for the Timer/Counter1 output com-pareA. The pin has to be configured as an output (DDB5 set (one)) to serve this function. The OC1A pin is also the output pin for the PWM mode timer function. [PB6:OC1B:PWM1B] OC1B, Output Compare matchB output: The PB6 pin can serve as an external output for the Timer/Counter1 output compare B. The pin has to be configured as an output (DDB6 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM mode timer function. [PB7:OC2:PWM2:OC1C] OC2, Output Compare match output: The PB7 pin can serve as an external output for the Timer/Counter2 output compare. The pin has to be configured as an output (DDB7 set (one)) to serve this function. The OC2 pin is also the output pin for the PWM mode timer function. [PG3:TOSC2] TOSC2, Timer Oscillator pin 2: When the AS0 bit in ASSR is set (one) to enable asynchronous clocking of Timer/Counter0, pin PG3 is disconnected from the port, and becomes the input of the inverting oscillator amplifier. In this mode, a crystal oscillator is connected to this pin, and the pin can not be used as an I/O pin. [PG4:TOSC1] TOSC1, Timer Oscillator pin 1: When the AS0 bit in ASSR is set (one) to enable asynchronous clocking of Timer/Counter0, pin PG4 is disconnected from the port, and becomes the inverting output of the oscillator amplifier. In this mode, a crystal oscillator is connected to this pin, and the pin can not be used as an I/O pin. ['RESET] [VCC] [GND] [XTAL2] [XTAL1] [PD0:SCL:INT0] INT0, External Interrupt source 0. The PD0 pin can serve as external active low interrupt source to the MCU. The internal pull up MOS resistors can be activated as described above. See the interrupt description for further details, and how to enable the source. SCL, 2-wire Serial Interface Clock: When the TWEN bit in TWCR is set (one) to enable the 2-wire Serial Interface, pin PD0 is disconnected from the port and becomes the Serial Clock I/O pin for the 2-wire Serial Interface. In this mode, there is a spike filter on the pin to suppress spikes shorter than 50 ns on the input signal, and the pin is driven by an open drain driver with slew-rate limitation [PD1:SDA:INT1] INT1, External Interrupt source 1. The PD1 pin can serve as external active low interrupt source to the MCU. The internal pull up MOS resistors can be activated as described above. See the interrupt description for further details, and how to enable the source. SDA, 2-wire Serial Interface Data: When the TWEN bit in TWCR is set (one) to enable the 2-wire Serial Interface, pin PD1 is disconnected from the port and becomes the Serial Data I/O pin for the 2-wire Serial Interface. In this mode, there is aspike filter on the pin to suppress spikes shorter than 50 ns on the input signal, and the pin is driven by an open drain driver with slew-rate limitati [PD2:RXD1:INT2] INT2, External Interrupt source 2. The PD2 pin can serve as external active low interrupt source to the MCU. The internal pull up MOS resistors can be activated as described above. See the interrupt description for further details, and how to enable the source. RXD1, Receive Data (Data input pin for the USART1). When the USART1 receiver is enabled this pin is configured as an input regardless of the value of DDD2. When the USART forces this pin to be an input, the pull-up can still be controlled by the PORTD2 bi [PD3:TXD1:INT3] INT3, External Interrupt source 3. The PD3 pin can serve as external active low interrupt source to the MCU. The internal pull up MOS resistors can be activated as described above. See the interrupt description for further details, and how to enable the source. TXD1, Transmit Data (Data output pin for the USART1). When the USART1 transmitter is enabled, this pin is configured as an output regardless of the value of DDD3. [PD4:IC1] IC1 - Input Capture Pin1: The PD4 pin can act as an input capture pin for Timer/Counter1. [PD5:XCK1] XCK1, USART1 external clock. The Data Direction Register (DDD4) controls whether the clock is output (DDD4 set) or input (DDD4 cleared). The XCK1 pin is active only when the USART1 operates in synchronous mode. [PD6:T1] T1, Timer/Counter1 counter source. [PD7:T2] T2, Timer/Counter2 counter source. [PG0:'WR] WR is the external data memory write control strobe. [PG1:'RD] RD is the external data memory read control strobe. [PC0:A8] [PC1:A9] [PC2:A10] [PC3:A11] [PC4:A12] [PC5:A13] [PC6:A14] [PC7:A15] [PG2:ALE] ALE is the external data memory Address Latch Enable signal. [PA7:AD7] [PA6:AD6] [PA5:AD5] [PA4:AD4] [PA3:AD3] [PA2:AD2] [PA1:AD1] [PA0:AD0] [VCC] [GND] [PF7:ADC7:TDI] ADC7, Analog to Digital Converter, channel 7. TDI, JTAG Test Data In: Serial input data to be shifted in to the Instruction Register or Data Register (scan chains). When the JTAG interface is enabled, this pin can not be used as an I/O pin. [PF6:ADC6:TD0] ADC6, Analog to Digital Converter, channel 6. TDO, JTAG Test Data Out: Serial output data from Instruction register or Data Register. When the JTAG interface is enabled, this pin can not be used as an I/O pin. [PF5:ADC5:TMS] ADC5, Analog to Digital Converter, channel 5. TMS, JTAG Test Mode Select: This pin is used for navigating through the TAP-controller state machine. When the JTAG interface is enabled, this pin can not be used as an I/O pin. [PF4:ADC4:TCK] ADC4, Analog to Digital Converter, channel 4. TCK, JTAG Test Clock: JTAG operation is synchronous to TCK. When the JTAG interface is enabled, this pin can not be used as an I/O pin. [PF3:ADC3] Analog to Digital Converter, Channel 3 [PF2:ADC2] Analog to Digital Converter, Channel 2 [PF1:ADC1] Analog to Digital Converter, Channel 1 [PF0:ADC0] Analog to Digital Converter, Channel 0 [AREF] [GND] [AVCC] 4MHz 25C 3.0mA 1.0mA <1uA 2.7 6.0 4.5 5.5 [LB1 = 1 : LB2 = 1] No memory lock features enabled. [LB1 = 0 : LB2 = 1] Further programming of Flash and EEPROM is enabled. [LB1 = 0 : LB2 = 0] Same as previous, but verify is also disabled 6 11 0x03 0x03 Mode 1: No memory lock features enabled 0x03 0x02 Mode 2: Further programming disabled 0x03 0x00 Mode 3: Further programming and verification disabled 0x0C 0x0C Application Protection Mode 1: No lock on SPM and LPM in Application Section 0x0C 0x08 Application Protection Mode 2: SPM prohibited in Application Section 0x0C 0x00 Application Protection Mode 3: LPM and SPM prohibited in Application Section 0x0C 0x04 Application Protection Mode 4: LPM prohibited in Application Section 0x30 0x30 Boot Loader Protection Mode 1: No lock on SPM and LPM in Boot Loader Section 0x30 0x20 Boot Loader Protection Mode 2: SPM prohibited in Boot Loader Section 0x30 0x00 Boot Loader Protection Mode 3: LPM and SPM prohibited in Boot Loader Section 0x30 0x10 Boot Loader Protection Mode 4: LPM prohibited in Boot Loader Section LB1 Lock bit LB2 Lock bit BLB01 Boot Lock bit BLB02 Boot Lock bit BLB11 Boot lock bit BLB12 Boot lock bit 0xff,0xdf,0xff 0xff,0xdf,0xff 1,0x40,0x40,WARNING! These fuse settings will disable the JTAG interface! 1,0x20,0x20,WARNING! These fuse settings will disable the ISP interface! 1,0x40,0x40,WARNING! These fuse settings will disable the JTAG interface! 1,0x20,0x20,WARNING! These fuse settings will disable the ISP interface! 1,0x40,0x40,WARNING! These fuse settings will disable the JTAG interface! 1,0x20,0x20,WARNING! These fuse settings will disable the ISP interface! 0x00,1.0 MHz 0x01,2.0 MHz 0x02,4.0 MHz 0x03,8.0 MHz 256 8 [ANALOG_COMPARATOR:SPI:TWI:USART0:USART1:CPU:BOOT_LOAD:JTAG:MISC:EXTERNAL_INTERRUPT:EEPROM:PORTA:PORTB:PORTC:PORTD:PORTE:PORTF:PORTG:TIMER_COUNTER_0:TIMER_COUNTER_1:TIMER_COUNTER_2:TIMER_COUNTER_3:WATCHDOG:AD_CONVERTER] [SFIOR:ACSR] io_analo.bmp AlgComp_01 SFIOR Special Function IO Register 0x20 0x40 io_flag.bmp Y ACME Analog Comparator Multiplexer Enable When this bit is written logic one and the ADC is switched off (ADEN in ADCSR is zero), the ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed description of this bit, see “Analog Comparator Multiplexed Input” on page 186. RW 0 ACSR Analog Comparator Control And Status Register 0x08 0x28 io_analo.bmp Y ACD Analog Comparator Disable When this bit is written logic one, the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed. RW 0 ACBG Analog Comparator Bandgap Select When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. See “Internal Voltage Reference” on page 42. RW 0 ACO Analog Compare Output The output of the analog comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1-2 clock cycles. R NA ACI Analog Comparator Interrupt Flag This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hard-ware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag. RW 0 ACIE Analog Comparator Interrupt Enable When the ACIE bit is written logic one and the I-bit in the Status Register is set, the analog comparator interrupt is acti-vated. When written logic zero, the interrupt is disabled. RW 0 ACIC Analog Comparator Input Capture Enable When written logic one, this bit enables the Input Capture function in Timer/Counter1 to be triggered by the analog comparator. The comparator output is in this case directly connected to the Input Capture front-end logic, making the comparator utilize the noise canceler and edge select features of the Timer/Counter1 Input Capture interrupt. When written logic zero, no connection between the analog comparator and the Input Capture function exists. To make the comparator trigger the Timer/Counter1 Input Capture interrupt, the TICIE1 bit in the Timer Interrupt Mask Register (TIMSK) must be set RW 0 ACIS1 Analog Comparator Interrupt Mode Select bit 1 These bits determine which comparator events that trigger the Analog Comparator interrupt. RW 0 ACIS0 Analog Comparator Interrupt Mode Select bit 0 These bits determine which comparator events that trigger the Analog Comparator interrupt. RW 0 [SPDR:SPSR:SPCR] io_com.bmp SPI_01 The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the device and peripheral devices or between several AVR devices. The SPI includes the following features: • Full-duplex, 3-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Seven Programmable Bit Rates • End of Transmission Interrupt Flag • Write Collision Flag Protection • Wake-up from Idle Mode • Double Speed (CK/2) Master SPI Mode SPDR SPI Data Register The SPI Data Register is a read/write register used for data transfer between the register file and the SPI Shift register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read. 0x0F 0x2F io_com.bmp N SPDR7 SPI Data Register bit 7 RW X SPDR6 SPI Data Register bit 6 RW X SPDR5 SPI Data Register bit 5 RW X SPDR4 SPI Data Register bit 4 RW X SPDR3 SPI Data Register bit 3 RW X SPDR2 SPI Data Register bit 2 RW X SPDR1 SPI Data Register bit 1 R 0 SPDR0 SPI Data Register bit 0 R 0 SPSR SPI Status Register 0x0E 0x2E io_flag.bmp Y SPIF SPI Interrupt Flag When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is generated if SPIE in SPCR is set (one) and global interrupts are enabled. If SS is an input and is driven low when the SPI is in master mode, this will also set the SPIF flag. SPIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the SPI status register when SPIF is set (one), then accessing the SPI Data Register (SPDR). R 0 WCOL Write Collision Flag The WCOL bit is set if the SPI data register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Register when WCOL is set (one), and then accessing the SPI Data Register. R 0 SPI2X Double SPI Speed Bit When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in master mode (see Table 71). This means that the minimum SCK period will be 2 CPU clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at f ck / 4 or lower. The SPI interface on the ATmega104 is also used for program memory and EEPROM downloading or uploading. See page 253 for serial programming and verification. RW 0 SPCR SPI Control Register 0x0D 0x2D io_flag.bmp Y SPIE SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR register is set and the global interrupts are enabled. RW 0 SPE SPI Enable When the SPE bit is set (one), the SPI is enabled. This bit must be set to enable any SPI operations. RW 0 DORD Data Order When the DORD bit is set (one), the LSB of the data word is transmitted first. When the DORD bit is cleared (zero), the MSB of the data word is transmitted first. RW 0 MSTR Master/Slave Select This bit selects Master SPI mode when set (one), and Slave SPI mode when cleared (zero). If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI master mode. RW 0 CPOL Clock polarity When this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is low when idle. Refer to Figure 36 and Figure 37 for additional information. RW 0 CPHA Clock Phase Refer to Figure 36 or Figure 37 for the functionality of this bit. RW 0 SPR1 SPI Clock Rate Select 1 RW 0 SPR0 SPI Clock Rate Select 0 RW 0 [TWBR:TWCR:TWSR:TWDR:TWAR] io_com.bmp TWI: Simple yet powerful and flexible communications interface, only two bus lines needed. Both master and slave operation supported. Device can operate as transmitter or receiver. 7-bit address space allows up to 128 different slave addresses. Multi-master arbitration support Up to 400 kHz data transfer speed Slew-rate limited output drivers Noise suppression circuitry rejects spikes on bus lines Fully programmable slave address with general call support Address recognition causes wake-up when AVR is in sleep mode The Two-Wire Serial Interface (TWI) is ideally suited to typical microcontroller applications. The TWI protocol allows the systems designer to interconnect up to 128 different devices using only two bidirectional bus lines, one for clock (SCL) andone for data (SDA). The only external hardware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines. All devices connected to the bus have individual addresses, and mechanisms for resolving bus contention are inherent in the TWI pr TWBR I2BR TWI Bit Rate register TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency divider which generates the SCL clock frequency in the master modes. See “Bit Rate Generator Unit” on page 165 for calculating bit rates. NA 0x70 io_com.bmp N TWBR7 RW 0 TWBR6 RW 0 TWBR5 RW 0 TWBR4 RW 0 TWBR3 RW 0 TWBR2 RW 0 TWBR1 RW 0 TWBR0 RW 0 TWCR I2CR TWI Control Register The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate a master access by applying a START condition to the bus, to generate a receiver acknowledge, to generate a stop condition, and to control halting of the bus while the data to be written to the bus are written to the TWDR. It also indicates a write collision if data is attempted written to TWDR while the register is inaccessible. NA 0x74 io_flag.bmp Y TWINT I2INT TWI Interrupt Flag This bit is set by hardware when the TWI has finished its current job and expects application software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the TWI interrupt vector. While the TWINT flag is set, the SCL low period is stretched. The TWINT flag must be cleared by software by writing a logic one to it. Note that this flag is not automatically cleared by hardware when executing the interrupt routine. Also note that clearing this flag starts the operation of the TWI, so all accesses to the TWI Address Register (TWAR), TWI Status Register (TWSR), and TWI Data Register (TWDR) must be complete before clearing this flag RW 0 TWEA I2EA TWI Enable Acknowledge Bit The TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is written to one, the ACK pulse is gener-ated on the TWI bus if the following conditions are met: 1. The device’s own slave address has been received. 2. A general call has been received, while the TWGCE bit in the TWAR is set. 3. A data byte has been received in master receiver or slave receiver mode. By writing the TWEA bit to zero, the device can be virtually disconnected from the 2-wire Serial Bus temporarily. Address recognition can then be resumed by writing the TWEA bit to one again RW 0 TWSTA I2STA TWI Start Condition Bit The application writes the TWSTA bit to one when it desires to become a master on the 2-wire Serial Bus. The TWI hard-ware checks if the bus is available, and generates a START condition on the bus if it is free. However, if the bus is not free, the TWI waits until a STOP condition is detected, and then generates a new START condition to claim the bus Master sta-tus. TWSTA is cleared by the TWI hardware when the START condition has been transmitted. RW 0 TWSTO I2STO TWI Stop Condition Bit Writing the TWSTO bit to one in master mode will generate a STOP condition on the 2-wire Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit is cleared automatically. In slave mode, setting the TWSTO bit can be used to recover from an error condition. This will not generate a STOP condition, but the TWI returns to a well-defined unaddressed slave mode and releases the SCL and SDA lines to a high impedance state. RW 0 TWWC I2WC TWI Write Collition Flag The TWWC bit is set when attempting to write to the TWI Data Register - TWDR when TWINT is low. This flag is cleared by writing the TWDR register when TWINT is high. RW 0 TWEN I2EN ENI2C TWI Enable Bit The TWEN bit enables TWI operation and activates the TWI interface. When TWEN is written to one, the TWI takes control over the I/O pins connected to the SCL and SDA pins, enabling the slew-rate limiters and spike filters. If this bit is written to zero, the TWI is switched off and all TWI transmissions are terminated, regardless of any ongoing operation. RW 0 TWIE I2IE TWI Interrupt Enable When this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request will be activated for as long as the TWINT flag is high. RW 0 TWSR I2SR TWI Status Register NA 0x71 io_flag.bmp Y TWS7 I2S7 TWI Status Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient c RW 0 TWS6 I2S6 TWI Status Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient co RW 0 TWS5 I2S5 TWI Status Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient c RW 0 TWS4 I2S4 TWI Status Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient co RW 0 TWS3 I2S3 TWI Status Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient co RW 0 TWPS1 TWS1 TWI Prescaler Bits 1..0: These bits can be read and written, and control the bit rate prescaler. See “Bit Rate Generator Unit” on page 165 for calculating bit rates. RW 0 TWPS0 TWS0 I2GCE TWI Prescaler Bits 1..0: These bits can be read and written, and control the bit rate prescaler. See “Bit Rate Generator Unit” on page 165 for calculating bit rates. RW 0 TWDR I2DR TWI Data register In transmit mode, TWDR contains the next byte to be transmitted. In receive mode, the TWDR contains the last byte received. It is writable while the TWI is not in the process of shifting a byte. This occurs when the TWI interrupt flag (TWINT) is set by hardware. Note that the data register cannot be initialized by the user before the first interrupt occurs. The data in TWDR remains stable as long as TWINT is set. While data is shifted out, data on the bus is simultaneously shifted in. TWDR always contains the last byte present on the bus, except after a wake up from a sleep mode by the TWI interrupt. In this case, the contents of TWDR is undefined. In the case of a lost bus arbitration, no data is lost in the transi-tion from Master to Slave. Handling of the ACK bit is controlled automatically by the TWI logic, the CPU cannot access the ACK bit directl NA 0x73 io_com.bmp N TWD7 TWI Data Register Bit 7 RW 1 TWD6 TWI Data Register Bit 6 RW 1 TWD5 TWI Data Register Bit 5 RW 1 TWD4 TWI Data Register Bit 4 RW 1 TWD3 TWI Data Register Bit 3 RW 1 TWD2 TWI Data Register Bit 2 RW 1 TWD1 TWI Data Register Bit 1 RW 1 TWD0 TWI Data Register Bit 0 RW 1 TWAR I2AR TWI (Slave) Address register The TWAR should be loaded with the 7-bit slave address (in the seven most significant bits of TWAR) to which the TWI will respond when programmed as a slave transmitter or receiver, and not needed in the master modes. In multimaster sys-tems, TWAR must be set in masters which can be addressed as slaves by other masters. The LSB of TWAR is used to enable recognition of the general call address ($00). There is an associated address compar-ator that looks for the slave address (or general call address if enabled) in the received serial address. If a match is found, an interrupt request is genera NA 0x72 io_com.bmp Y TWA6 TWI (Slave) Address register Bit 6 RW 0 TWA5 TWI (Slave) Address register Bit 5 RW 0 TWA4 TWI (Slave) Address register Bit 4 RW 0 TWA3 TWI (Slave) Address register Bit 3 RW 0 TWA2 TWI (Slave) Address register Bit 2 RW 0 TWA1 TWI (Slave) Address register Bit 1 RW 0 TWA0 TWI (Slave) Address register Bit 0 RW 0 TWGCE TWI General Call Recognition Enable Bit RW 0 [UDR0:UCSR0A:UCSR0B:UCSR0C:UBRR0H:UBRR0L] [UBRR0H:UBRR0L] io_com.bmp The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. The main features are: • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • High Resolution Baud Rate Generator • Supports Serial Frames with 5, 6, 7, 8 or 9 Data Bits and 1 or 2 Stop Bits • Odd or Even Parity Generation and Parity Check Supported by Hardware • Data OverRun Detection • Framing Error Detection • Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter • Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete • Multi-processor Communication Mode • Double Speed Asynchronous Commu UDR0 USART I/O Data Register The UDR0 register is actually two physically separate registers sharing the same I/O address. When writing to the register, the USART Transmit Data register is written. When reading from UDR0, the USART Receive Data register is read. 0x0C 0x2C io_com.bmp N UDR07 USART I/O Data Register bit 7 RW 0 UDR06 USART I/O Data Register bit 6 RW 0 UDR05 USART I/O Data Register bit 5 RW 0 UDR04 USART I/O Data Register bit 4 RW 0 UDR03 USART I/O Data Register bit 3 RW 0 UDR02 USART I/O Data Register bit 2 RW 0 UDR01 USART I/O Data Register bit 1 RW 0 UDR00 USART I/O Data Register bit 0 RW 0 UCSR0A USART Control and Status Register A 0x0B 0x2B io_flag.bmp Y RXC0 USART Receive Complete This bit is set (one) when a received character is transferred from the Receiver Shift register to UDR0. The bit is set regard-less of any detected framing errors. When the RXCIE bit in UCR is set, the USART Receive Complete interrupt will be executed when RXC is set(one). RXC is cleared by reading UDR0. When interrupt-driven data reception is used, the USART Receive Complete Interrupt routine must read UDR0 in order to clear RXC, otherwise a new interrupt will occur once the interrupt routine terminates. R 0 TXC0 USART Transmitt Complete This bit is set (one) when the entire character (including the stop bit) in the Transmit Shift register has been shifted out and no new data has been written to UDR0. This flag is especially useful in half-duplex communications interfaces, where a transmitting application must enter receive mode and free the communications bus immediately after completing the transmission. When the TXCIE bit in UCR is set, setting of TXC causes the USART Transmit Complete interrupt to be executed. TXC is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the TXC bit is cleared (zero) by writing a logical one to th RW 0 UDRE0 USART Data Register Empty This bit is set (one) when a character written to UDR0 is transferred to the Transmit shift register. Setting of this bit indicates that the transmitter is ready to receive a new character for transmission. When the UDR0IE bit in UCR is set, the USART Transmit Complete interrupt to be executed as long as UDR0E is set. UDR0E is cleared by writing UDR0. When interrupt-driven data transmittal is used, the USART Data Register Empty Interrupt routine must write UDR0 in order to clear UDR0E, otherwise a new interrupt will occur once the interrupt routine terminates. UDR0E is set (one) during reset to indicate that the transmitter is re R 1 FE0 Framing Error This bit is set if a Framing Error condition is detected, i.e. when the stop bit of an incoming character is zero. The FE bit is cleared when the stop bit of received data is one. R 0 DOR0 Data overRun This bit is set if an Overrun condition is detected, i.e. when a character already present in the UDR0 register is not read before the next character has been shifted into the Receiver Shift register. The OR bit is buffered, which means that it will be set once the valid data still in UDR0E is read. The OR bit is cleared (zero) when data is received and transferred to UDR0. R 0 UPE0 Parity Error This bit is set if the next character in the receive buffer had a Parity Error when received and the parity checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer (UDR0) is read. Always set this bit to zero when writing to UCSR0A. R 0 U2X0 Double the USART transmission speed This bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation. Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous communication. RW 0 MPCM0 Multi-processor Communication Mode This bit enables the Multi-processor Communication Mode. When the MPCM bit is written to one, all the incoming frames received by the USART receiver that do not contain address information will be ignored. The transmitter is unaffected by the MPCM setting. For more detailed information see “Multi-processor Communication Mode” on page 152. RW 0 UCSR0B USART Control and Status Register B 0x0A 0x2A io_flag.bmp Y RXCIE0 RX Complete Interrupt Enable Writing this bit to one enables interrupt on the RXC flag. A USART Receive Complete interrupt will be generated only if the RXCIE bit is written to one, the global interrupt flag in SREG is written to one and the RXC bit in UCSR0A is set. RW 0 TXCIE0 TX Complete Interrupt Enable Writing this bit to one enables interrupt on the TXC flag. A USART Transmit Complete interrupt will be generated only if the TXCIE bit is written to one, the global interrupt flag in SREG is written to one and the TXC bit in UCSR0A is set. RW 0 UDRIE0 USART Data register Empty Interrupt Enable Writing this bit to one enables interrupt on the UDR0E flag. A Data Register Empty interrupt will be generated only if the UDR0IE bit is written to one, the global interrupt flag in SREG is written to one and the UDR0E bit in UCSR0A is set. RW 1 RXEN0 Receiver Enable Writing this bit to one enables the USART receiver. The receiver will override normal port operation for the RxD pin when enabled. Disabling the receiver will flush the receive buffer invalidating the FE, DOR and PE flags. RW 0 TXEN0 Transmitter Enable Writing this bit to one enables the USART transmitter. The transmitter will override normal port operation for the TxD pin when enabled. The disabling of the transmitter (writing TXEN to zero) will not become effective until ongoing and pending transmissions are completed, i.e. when the transmit shift register and transmit buffer register does not contain data to be transmitted. When disabled, the transmitter will no longer override the TxD port. RW 0 UCSZ02 UCSZ2 Character Size The UCSZ2 bits combined with the UCSZ1:0 bit in UCSR0C sets the number of data bits (character size) in a frame the receiver and transmitter use. RW 0 RXB80 Receive Data Bit 8 RXB8 is the 9th data bit of the received character when operating with serial frames with 9 data bits. Must be read before reading the low bits from UDR0. R 0 TXB80 Transmit Data Bit 8 TXB8 is the 9th data bit in the character to be transmitted when operating with serial frames with 9 data bits. Must be writ-ten before writing the low bits to UDR0. W 0 UCSR0C USART Control and Status Register C NA 0x95 io_flag.bmp Y UMSEL0 USART Mode Select 0: Asynchronous Operation. 1: Synchronous Operation RW 0 UPM01 Parity Mode Bit 1 This bit enable and set type of parity generation and check. If enabled, the transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value for the incoming data and compare it to the UPM0 setting. If a mismatch is detected, the PE flag in UCSR0A will be set. RW 0 UPM00 Parity Mode Bit 0 This bit enable and set type of parity generation and check. If enabled, the transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value for the incoming data and compare it to the UPM0 setting. If a mismatch is detected, the PE flag in UCSR0A will be set. RW 0 USBS0 Stop Bit Select 0: 1-bit. 1: 2-bit. RW 0 UCSZ01 Character Size Character Size: 0 0 0 = 5-bit. 0 0 1 = 6-bit. 0 1 0 = 7 bit. 0 1 1 = 8-bit. 1 1 1 = 9 bit. RW 0 UCSZ00 Character Size Character Size: 0 0 0 = 5-bit. 0 0 1 = 6-bit. 0 1 0 = 7 bit. 0 1 1 = 8-bit. 1 1 1 = 9 bit. RW 1 UCPOL0 Clock Polarity This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOL bit sets the relationship between data output change and data input sample, and the synchronous clock (XCK). RW 0 UBRR0H USART Baud Rate Register Hight Byte This is a 12-bit register which contains the USART baud rate. The UBRR0H contains the 4 most significant bits, and the UBRR0L contains the 8 least significant bits of the USART baud rate. Ongoing transmissions by the transmitter and receiver will be corrupted if the baud rate is changed. Writing UBRR0L will trigger an immediate update of the baud rate prescaler. NA 0x90 io_com.bmp N UBRR11 USART Baud Rate Register bit 11 RW 0 UBRR10 USART Baud Rate Register bit 10 RW 0 UBRR9 USART Baud Rate Register bit 9 RW 0 UBRR8 USART Baud Rate Register bit 8 RW 0 UBRR0L USART Baud Rate Register Low Byte This is a 12-bit register which contains the USART baud rate. The UBRR0H contains the 4 most significant bits, and the UBRR0L contains the 8 least significant bits of the USART baud rate. Ongoing transmissions by the transmitter and receiver will be corrupted if the baud rate is changed. Writing UBRR0L will trigger an immediate update of the baud rate prescaler. 0x09 0x29 io_com.bmp N UBRR7 USART Baud Rate Register bit 7 RW 0 UBRR6 USART Baud Rate Register bit 6 RW 0 UBRR5 USART Baud Rate Register bit 5 RW 0 UBRR4 USART Baud Rate Register bit 4 RW 0 UBRR3 USART Baud Rate Register bit 3 RW 0 UBRR2 USART Baud Rate Register bit 2 RW 0 UBRR1 USART Baud Rate Register bit 1 RW 0 UBRR0 USART Baud Rate Register bit 0 RW 0 [UDR1:UCSR1A:UCSR1B:UCSR1C:UBRR1H:UBRR1L] [UBRR1H:UBRR1L] io_com.bmp The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. The main features are: • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • High Resolution Baud Rate Generator • Supports Serial Frames with 5, 6, 7, 8 or 9 Data Bits and 1 or 2 Stop Bits • Odd or Even Parity Generation and Parity Check Supported by Hardware • Data OverRun Detection • Framing Error Detection • Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter • Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete • Multi-processor Communication Mode • Double Speed Asynchronous Communicat UDR1 USART I/O Data Register The UDR1 register is actually two physically separate registers sharing the same I/O address. When writing to the register, the USART Transmit Data register is written. When reading from UDR1, the USART Receive Data register is read. NA 0x9C io_com.bmp N UDR17 USART I/O Data Register bit 7 RW 0 UDR16 USART I/O Data Register bit 6 RW 0 UDR15 USART I/O Data Register bit 5 RW 0 UDR14 USART I/O Data Register bit 4 RW 0 UDR13 USART I/O Data Register bit 3 RW 0 UDR12 USART I/O Data Register bit 2 RW 0 UDR11 USART I/O Data Register bit 1 RW 0 UDR10 USART I/O Data Register bit 0 RW 0 UCSR1A USART Control and Status Register A NA 0x9B io_flag.bmp Y RXC1 USART Receive Complete This bit is set (one) when a received character is transferred from the Receiver Shift register to UDR1. The bit is set regard-less of any detected framing errors. When the RXCIE bit in UCR is set, the USART Receive Complete interrupt will be executed when RXC is set(one). RXC is cleared by reading UDR1. When interrupt-driven data reception is used, the USART Receive Complete Interrupt routine must read UDR1 in order to clear RXC, otherwise a new interrupt will occur once the interrupt routine terminates. R 0 TXC1 USART Transmitt Complete This bit is set (one) when the entire character (including the stop bit) in the Transmit Shift register has been shifted out and no new data has been written to UDR1. This flag is especially useful in half-duplex communications interfaces, where a transmitting application must enter receive mode and free the communications bus immediately after completing the transmission. When the TXCIE bit in UCR is set, setting of TXC causes the USART Transmit Complete interrupt to be executed. TXC is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the TXC bit is cleared (zero) by writing a logical one to the bi RW 0 UDRE1 USART Data Register Empty This bit is set (one) when a character written to UDR1 is transferred to the Transmit shift register. Setting of this bit indicates that the transmitter is ready to receive a new character for transmission. When the UDR1IE bit in UCR is set, the USART Transmit Complete interrupt to be executed as long as UDR1E is set. UDR1E is cleared by writing UDR1. When interrupt-driven data transmittal is used, the USART Data Register Empty Interrupt routine must write UDR1 in order to clear UDR1E, otherwise a new interrupt will occur once the interrupt routine terminates. UDR1E is set (one) during reset to indicate that the transmitter is read R 1 FE1 Framing Error This bit is set if a Framing Error condition is detected, i.e. when the stop bit of an incoming character is zero. The FE bit is cleared when the stop bit of received data is one. R 0 DOR1 Data overRun This bit is set if an Overrun condition is detected, i.e. when a character already present in the UDR1 register is not read before the next character has been shifted into the Receiver Shift register. The OR bit is buffered, which means that it will be set once the valid data still in UDR1E is read. The OR bit is cleared (zero) when data is received and transferred to UDR1. R 0 UPE1 Parity Error This bit is set if the next character in the receive buffer had a Parity Error when received and the parity checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer (UDR1) is read. Always set this bit to zero when writing to UCSR1A. R 0 U2X1 Double the USART transmission speed This bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation. Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous communication. RW 0 MPCM1 Multi-processor Communication Mode This bit enables the Multi-processor Communication Mode. When the MPCM bit is written to one, all the incoming frames received by the USART receiver that do not contain address information will be ignored. The transmitter is unaffected by the MPCM setting. For more detailed information see “Multi-processor Communication Mode” on page 152. RW 0 UCSR1B USART Control and Status Register B NA 0x9A io_flag.bmp Y RXCIE1 RX Complete Interrupt Enable Writing this bit to one enables interrupt on the RXC flag. A USART Receive Complete interrupt will be generated only if the RXCIE bit is written to one, the global interrupt flag in SREG is written to one and the RXC bit in UCSR1A is set. RW 0 TXCIE1 TX Complete Interrupt Enable Writing this bit to one enables interrupt on the TXC flag. A USART Transmit Complete interrupt will be generated only if the TXCIE bit is written to one, the global interrupt flag in SREG is written to one and the TXC bit in UCSR1A is set. RW 0 UDRIE1 USART Data register Empty Interrupt Enable Writing this bit to one enables interrupt on the UDR1E flag. A Data Register Empty interrupt will be generated only if the UDR1IE bit is written to one, the global interrupt flag in SREG is written to one and the UDR1E bit in UCSR1A is set. RW 1 RXEN1 Receiver Enable Writing this bit to one enables the USART receiver. The receiver will override normal port operation for the RxD pin when enabled. Disabling the receiver will flush the receive buffer invalidating the FE, DOR and PE flags. RW 0 TXEN1 Transmitter Enable Writing this bit to one enables the USART transmitter. The transmitter will override normal port operation for the TxD pin when enabled. The disabling of the transmitter (writing TXEN to zero) will not become effective until ongoing and pending transmissions are completed, i.e. when the transmit shift register and transmit buffer register does not contain data to be transmitted. When disabled, the transmitter will no longer override the TxD port. RW 0 UCSZ12 Character Size The UCSZ2 bits combined with the UCSZ1:0 bit in UCSR1C sets the number of data bits (character size) in a frame the receiver and transmitter use. RW 0 RXB81 Receive Data Bit 8 RXB8 is the 9th data bit of the received character when operating with serial frames with 9 data bits. Must be read before reading the low bits from UDR1. R 0 TXB81 Transmit Data Bit 8 TXB8 is the 9th data bit in the character to be transmitted when operating with serial frames with 9 data bits. Must be writ-ten before writing the low bits to UDR1. W 0 UCSR1C USART Control and Status Register C NA 0x9D io_flag.bmp Y UMSEL1 USART Mode Select 0: Asynchronous Operation. 1: Synchronous Operation RW 0 UPM11 Parity Mode Bit 1 This bit enable and set type of parity generation and check. If enabled, the transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value for the incoming data and compare it to the UPM0 setting. If a mismatch is detected, the PE flag in UCSR1A will be set. RW 0 UPM10 Parity Mode Bit 0 This bit enable and set type of parity generation and check. If enabled, the transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value for the incoming data and compare it to the UPM0 setting. If a mismatch is detected, the PE flag in UCSR1A will be set. RW 0 USBS1 Stop Bit Select 0: 1-bit. 1: 2-bit. RW 0 UCSZ11 Character Size Character Size: 0 0 0 = 5-bit. 0 0 1 = 6-bit. 0 1 0 = 7 bit. 0 1 1 = 8-bit. 1 1 1 = 9 bit. RW 0 UCSZ10 Character Size Character Size: 0 0 0 = 5-bit. 0 0 1 = 6-bit. 0 1 0 = 7 bit. 0 1 1 = 8-bit. 1 1 1 = 9 bit. RW 1 UCPOL1 Clock Polarity This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOL bit sets the relationship between data output change and data input sample, and the synchronous clock (XCK). RW 0 UBRR1H USART Baud Rate Register Hight Byte This is a 12-bit register which contains the USART baud rate. The UBRR1H contains the 4 most significant bits, and the UBRR1L contains the 8 least significant bits of the USART baud rate. Ongoing transmissions by the transmitter and receiver will be corrupted if the baud rate is changed. Writing UBRR1L will trigger an immediate update of the baud rate prescaler. NA 0x98 io_com.bmp N UBRR11 USART Baud Rate Register bit 11 RW 0 UBRR10 USART Baud Rate Register bit 10 RW 0 UBRR9 USART Baud Rate Register bit 9 RW 0 UBRR8 USART Baud Rate Register bit 8 RW 0 UBRR1L USART Baud Rate Register Low Byte This is a 12-bit register which contains the USART baud rate. The UBRR1H contains the 4 most significant bits, and the UBRR1L contains the 8 least significant bits of the USART baud rate. Ongoing transmissions by the transmitter and receiver will be corrupted if the baud rate is changed. Writing UBRR1L will trigger an immediate update of the baud rate prescaler. NA 0x99 io_com.bmp N UBRR7 USART Baud Rate Register bit 7 RW 0 UBRR6 USART Baud Rate Register bit 6 RW 0 UBRR5 USART Baud Rate Register bit 5 RW 0 UBRR4 USART Baud Rate Register bit 4 RW 0 UBRR3 USART Baud Rate Register bit 3 RW 0 UBRR2 USART Baud Rate Register bit 2 RW 0 UBRR1 USART Baud Rate Register bit 1 RW 0 UBRR0 USART Baud Rate Register bit 0 RW 0 [SREG:SPH:SPL:MCUCR:XMCRA:XMCRB:OSCCAL:XDIV:MCUCSR:RAMPZ] [SPH:SPL] io_cpu.bmp SREG Status Register 0x3F 0x5F io_sreg.bmp Y I Global Interrupt Enable The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable bit is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. RW 0 T Bit Copy Storage The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction. RW 0 H Half Carry Flag The half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed information. RW 0 S Sign Bit The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruc-tion Set Description for detailed information. RW 0 V Two's Complement Overflow Flag The two’s complement overflow flag V supports two’s complement arithmetics. See the Instruction Set Description for detailed information. RW 0 N Negative Flag The negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information. RW 0 Z Zero Flag The zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information. RW 0 C Carry Flag The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software. RW 0 SPH Stack Pointer High The general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the AT90S4414/8515 supports up to 64 kB external SRAM, all 16-bits are used. The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or return from interrupt R 0x3E 0x5E io_sph.bmp N SP15 Stack pointer bit 15 RW 0 SP14 Stack pointer bit 14 RW 0 SP13 Stack pointer bit 13 RW 0 SP12 Stack pointer bit 12 RW 0 SP11 Stack pointer bit 11 RW 0 SP10 Stack pointer bit 10 RW 0 SP9 Stack pointer bit 9 RW 0 SP8 Stack pointer bit 8 RW 0 SPL Stack Pointer Low The general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the AT90S4414/8515 supports up to 64 kB external SRAM, all 16-bits are used. The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or return from interrupt 0x3D 0x5D io_sph.bmp N SP7 Stack pointer bit 7 RW 0 SP6 Stack pointer bit 6 RW 0 SP5 Stack pointer bit 5 RW 0 SP4 Stack pointer bit 4 RW 0 SP3 Stack pointer bit 3 RW 0 SP2 Stack pointer bit 2 RW 0 SP1 Stack pointer bit 1 RW 0 SP0 Stack pointer bit 0 RW 0 MCUCR MCU Control Register The MCU Control Register contains control bits for general MCU functions. 0x35 0x55 io_flag.bmp Y SRE External SRAM Enable Writing SRE to one enables the External Memory Interface.The pin functions AD7:0, A15:8, ALE, WR, and RD are acti-vated as the alternate pin functions. The SRE bit overrides any pin direction settings in the respective data direction regis-ters. Writing SRE to zero, disables the External Memory Interface and the normal pin and data direction settings are used. RW 0 SRW10 External SRAM Wait State Select For a detailed description in non ATmega103 Compatibility mode, see common description for the SRWn bits below (XMRA description). In ATmega103 Compatibility mode, writing SRW10 to one enables the wait state and one extra cycle is added during read/write strobe as shown in Figure 14. RW 0 SE Sleep Enable RW 0 SM1 Sleep Mode Select The description is to long for the tooltip help, please refer to the manual RW 0 SM0 Sleep Mode Select The description is to long for the tooltip help, please refer to the manual RW 0 SM2 Sleep Mode Select The description is to long for the tooltip help, please refer to the manual RW 0 IVSEL Interrupt Vector Select When the IVSEL bit is cleared (zero), the interrupt vectors are placed at the start of the Flash memory. When this bit is set (one), the interrupt vectors are moved to the beginning of the Boot Loader section of the flash. The actual address of the start of the boot flash section is determined by the BOOTSZ fuses. Refer to the section “Boot Loader Support - Read While Write self-programming” on page 228 for details. To avoid unintentional changes of interrupt vector tables, a special write procedure must be followed to change the IVSEL bit: 1. Write the Interrupt Vector Change Enable (IVCE) bit to one. 2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE. Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts remain dis-abled for four cycles. The I-bit in the Status Register is unaffected by the automatic disabling. Note: Note: If interrupt vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed, interrupts are disabled while executing from the Application section. If interrupt vectors are placed in the Application section and Boot Lock bit BLB01 is pro-gramed, interrupts are disabled while executing from the Boot Loader section. Refer to the section “Boot Loader Support - Read While Write self-programming” on page 228 for details on Boot Lock bits RW 0 IVCE Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above. RW 0 MCUCSR MCU Control And Status Register The MCU Control And Status Register provides information on which reset source caused a MCU reset. 0x34 0x54 io_flag.bmp Y JTD JTAG Interface Disable When this bit is zero, the JTAG interface is enabled if the JTAGEN fuse is programmed. R/W 0 JTRF JTAG Reset Flag This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on reset, or by writing a logic zero to the flag. • Bit 3 - WDRF: Watchdog Reset Flag R/W 0 WDRF Watchdog Reset Flag This bit is set if a watchdog reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag. R/W 0 BORF Brown-out Reset Flag This bit is set if a brown-out reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag. R/W 0 EXTRF External Reset Flag This bit is set if an external reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag. R/W 0 PORF Power-on reset flag This bit is set if a power-on reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the reset flags to identify a reset condition, the user should read and then reset the MCUCSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags. R/W 0 XMCRA External Memory Control Register A NA 0x6D io_cpu.bmp Y SRL2 Wait state page limit It is possible to configure different wait-states for different external memory addresses. The external memory address space can be divided in two pages that have separate wait-state bits. The SRL2, SRL1, and SRL0 bits select the split of the pages, see Table 2 and Figure 11. As default, the SRL2, SRL1, and SRL0 bits are set to zero and the entire external mem-ory address space is treated as one page. When the entire SRAM address space is configured as one page, the wait-states are configured by the SRW11 and SRW10 bits R/W 0 SRL1 Wait state page limit It is possible to configure different wait-states for different external memory addresses. The external memory address space can be divided in two pages that have separate wait-state bits. The SRL2, SRL1, and SRL0 bits select the split of the pages, see Table 2 and Figure 11. As default, the SRL2, SRL1, and SRL0 bits are set to zero and the entire external mem-ory address space is treated as one page. When the entire SRAM address space is configured as one page, the wait-states are configured by the SRW11 and SRW10 bits R/W 0 SRL0 Wait state page limit It is possible to configure different wait-states for different external memory addresses. The external memory address space can be divided in two pages that have separate wait-state bits. The SRL2, SRL1, and SRL0 bits select the split of the pages, see Table 2 and Figure 11. As default, the SRL2, SRL1, and SRL0 bits are set to zero and the entire external mem-ory address space is treated as one page. When the entire SRAM address space is configured as one page, the wait-states are configured by the SRW11 and SRW10 bits R/W 0 SRW01 Wait state select bit lower page Note: n = 0 or 1 (lower/upper page). For further details of the timing and wait-states of the External Memory Interface, see Figure 13 to Figure 16 how the setting of the SRW bits affects the timing. Wait-states SRWn1 SRWn0 Wait-states 0 0 No wait states 0 1 Wait one cycle during read/write strobe 1 0 Wait two cycles during read/write strobe 1 1 Wait two cycles during read/write and wait one cycle before driving out new address R/W 0 SRW00 Wait state select bit lower page Note: n = 0 or 1 (lower/upper page). For further details of the timing and wait-states of the External Memory Interface, see Figure 13 to Figure 16 how the setting of the SRW bits affects the timing. Wait-states SRWn1 SRWn0 Wait-states 0 0 No wait states 0 1 Wait one cycle during read/write strobe 1 0 Wait two cycles during read/write strobe 1 1 Wait two cycles during read/write and wait one cycle before driving out new address R/W 0 SRW11 Wait state select bit upper page Wait state select bits for upper page. The SRW11 and SRW10 bits control the number of wait-states for the upper page of the external memory address space, see Table 3. R 0 XMCRB External Memory Control Register B NA 0x6C io_cpu.bmp Y XMBK External Memory Bus Keeper Enable Writing XMBK to one enables the bus keeper on the AD7:0 lines. When the bus keeper is enabled, AD7:0 will keep the last driven value on the lines even if the XMEM interface has tri-stated the lines. Writing XMBK to zero disables the bus keeper. XMBK is not qualified with SRE, so even if the XMEM interface is disabled, the bus keepers are still activiated as long as XMBK is one. R/W 0 XMM2 External Memory High Mask When the External Memory is enabled, all Port C pins are default used for the high address byte. If the full 60KB address space is not required to access the external memory, some, or all, Port C pins can be released for normal Port Pin function as described in Table 4. As described in “Using all 64KB locations of external memory” on page 27, it is possible to use the XMMn bits to access all 64KB locations of the external memory. R/W 0 XMM1 External Memory High Mask When the External Memory is enabled, all Port C pins are default used for the high address byte. If the full 60KB address space is not required to access the external memory, some, or all, Port C pins can be released for normal Port Pin function as described in Table 4. As described in “Using all 64KB locations of external memory” on page 27, it is possible to use the XMMn bits to access all 64KB locations of the external memory. R/W 0 XMM0 External Memory High Mask When the External Memory is enabled, all Port C pins are default used for the high address byte. If the full 60KB address space is not required to access the external memory, some, or all, Port C pins can be released for normal Port Pin function as described in Table 4. As described in “Using all 64KB locations of external memory” on page 27, it is possible to use the XMMn bits to access all 64KB locations of the external memory. R/W 0 OSCCAL Oscillator Calibration Value Writing the calibration byte to this address will trim the internal oscillator to remove process variations from the oscillator frequency. This is done automatically during chip reset. When OSCCAL is zero, the lowest available frequency is chosen. Writing non-zero values to this register will increase the frequency of the internal oscillator. Writing $FF to the register gives the highest available frequency. The calibrated oscillator is used to time EEPROM and Flash access. If EEPROM or Flash is written, do not calibrate to more than 10% above the nominal frequency. Otherwise, the EEPROM or Flash write may fail. Note that the Oscillator is intended for calibration to 1.0 MHz, 2.0 MHz, 4.0 MHz, or 8.0MHz. Tuning to other values is not guaranteed, as indicated in Table 14 NA 0x6F io_cpu.bmp N CAL7 Oscillator Calibration Value R/W 0 CAL6 Oscillator Calibration Value R/W 0 CAL5 Oscillator Calibration Value R/W 0 CAL4 Oscillator Calibration Value R/W 0 CAL3 Oscillator Calibration Value R/W 0 CAL2 Oscillator Calibration Value R/W 0 CAL1 Oscillator Calibration Value R/W 0 CAL0 Oscillator Calibration Value R/W 0 XDIV XTAL Divide Control Register The XTAL Divide Control Register is used to divide the Source clock frequency by a number in the range 1 - 129. This fea-ture can be used to decrease power consumption when the requirement for processing power is low. 0x3C 0x5C io_cpu.bmp N XDIVEN XTAL Divide Enable When the XDIVEN bit is written one, the clock frequency of the CPU and all peripherals (clk I/O , clk ADC , clk CPU , clk FLASH ) is divided by the factor defined by the setting of XDIV6 - XDIV0. This bit can be written run-time to vary the clock frequency as suitable to the application. R/W 0 XDIV6 XTAl Divide Select Bit 6 These bits define the division factor that applies when the XDIVEN bit is set (one). Please refer to the manual for details on the formulas. R/W 0 XDIV5 XTAl Divide Select Bit 5 These bits define the division factor that applies when the XDIVEN bit is set (one). Please refer to the manual for details on the formulas. R/W 0 XDIV4 XTAl Divide Select Bit 4 These bits define the division factor that applies when the XDIVEN bit is set (one). Please refer to the manual for details on the formulas. R/W 0 XDIV3 XTAl Divide Select Bit 3 These bits define the division factor that applies when the XDIVEN bit is set (one). Please refer to the manual for details on the formulas. R/W 0 XDIV2 XTAl Divide Select Bit 2 These bits define the division factor that applies when the XDIVEN bit is set (one). Please refer to the manual for details on the formulas. R/W 0 XDIV1 XTAl Divide Select Bit 1 These bits define the division factor that applies when the XDIVEN bit is set (one). Please refer to the manual for details on the formulas. R/W 0 XDIV0 XTAl Divide Select Bit 0 These bits define the division factor that applies when the XDIVEN bit is set (one). Please refer to the manual for details on the formulas. R/W 0 RAMPZ RAM Page Z Select Register 0x3B 0x5B io_cpu.bmp Y RAMPZ0 RAM Page Z Select Register Bit 0 The RAMPZ register is normally used to select which 64K RAM Page is accessed by the Z pointer. As the ATmega104 does not support more than 64K of SRAM memory, this register is used only to select which page in the program memory is accessed when the ELPM/SPM instruction is used. The different settings of the RAMPZ0 bit have the following effects: Note that LPM is not affected by the RAMPZ setting. RAMPZ0 = 0: Program memory address $0000- $7FFF (lower 64K bytes) is accessed by ELPM/SPM RAMPZ0 = 1: Program memory address $8000- $FFFF (higher 64K bytes) is accessed by ELPM/ RW 0 [SPMCSR] io_cpu.bmp AVRSimIOSPM.SimIOSPM The Boot Loader Support provides a real Read While Write self-programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program. The Boot Loader program can use any available data interface and associated proto-col to read code and write (program) that code into the Flash memory, or read the code from the program memory. The program code within the Boot Loader section has the capability to write into the entire Flash, including the Boot Loader Memory. The Boot Loader can thus even modify itself, and it can also erase itself from the code if the feature is not needed anymore. The size of the Boot Loader Memory is configurable with fuses and the Boot Loader has two separate sets of Boot Lock Bits which can be set independently. This gives the user a unique flexibility to select different levels of protection. Boot Loader Features: Read While Write self-programming. Flexibl Boot Memory size. High security (separate Boot Lock bits for a flexible protection). Separate fuse to select reset vector Optimized page (1) size. Code efficient algorithm Efficient read-modify-write suppor SPMCSR SPMCR Store Program Memory Control Register The Store Program Memory Control Register contains the control bits needed to control the Boot Loader operations. NA 0x68 io_flag.bmp Y SPMIE SPM Interrupt Enable When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN bit in the SPMCR register is cleared. RW 0 RWWSB ASB Read While Write Section Busy When a self-programming (page erase or page write) operation to the RWW section is initiated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a self-programming operation is completed. Alternatively the RWWSB bit will auto-matically be cleared if a page load operation is initiated. R 0 RWWSRE ASRE Read While Write section read enable When programming (page erase or page write) to the RWW section, the RWW section is blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW section, the user software must wait until the programming is completed (SPMEN will be cleared). Then, if the RWWSRE bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles re-enables the RWW section. The RWW section cannot be re-enabled while Flash is busy with a page erase or a page write (SPMEN is set). If the RWWSRE bit is written while the Flash is being loaded, the Flash load operation will abort and the data loaded will be lo RW 0 BLBSET Boot Lock Bit Set If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles sets Boot Lock bits, according to the data in R0. The data in R1 and the address in the Z pointer are ignored. The BLBSET bit will automatically be cleared upon completion of the lock bit set, or if no SPM instruction is executed within four clock cycles. An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCR register, will read either the Lock-bits or the Fuse bits (depending on Z0 in the Z pointer) into the destination register. See “Reading the Fuse and Lock Bits from Software” on page 235 for details RW 0 PGWRT Page Write If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPM instruction is exe-cuted within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed. RW 0 PGERS Page Erase If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page erase. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a page erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed. RW 0 SPMEN Store Program Memory Enable This bit enables the SPM instruction for the next four clock cycles. If written to one together with either RWWSRE, BLB-SET, PGWRT or PGERS, the following SPM instruction will have a special meaning, see description above. If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z pointer. The LSB of the Z pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During page erase and page write, the SPMEN bit remain high until the operation is completed. Writing any other combination than “10001”, "01001", "00101", "00011" or "00001" in the lower five bits will have no effec RW 0 [OCDR:MCUCSR] io_com.bmp 00 JTAG Features: JTAG (IEEE std. 1149.1 compliant) Interface. Boundary-Scan Capabilities According to the IEEE std. 1149.1 (JTAG) Standard. Debugger Access to: – All Internal Peripheral Units – Internal and External RAM – The Internal Register File –Program Counter – EEPROM and Flash Memories. Extensive On-Chip Debug Support for Break Conditions, Including: –AVR Break Instruction – Break on Change of Program Memory Flow –Single Step Break –Program Memory Breakpoints on Single Address or Address Range – Data Memory Breakpoints on Single Address or Address Range. Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface. On-Chip Debugging Supported by AVR S OCDR On-Chip Debug Related Register in I/O Memory The OCDR register provides a communication channel from the running program in the microcontroller to the debugger. The CPU can transfer a byte to the debugger by writing to this location. At the same time, an internal flag; I/O Debug Reg-ister Dirty - IDRD - is set to indicate to the debugger that the register has been written. When the CPU reads the OCDR reg-ister the 7 LSB will be from the OCDR register, while the MSB is the IDRD bit. The debugger clears the IDRD bit when it has read the information. In some AVR devices, this register is shared with a standard I/O location. In this case, the OCDR register can only be accessed if the OCDEN fuse is programmed, and the debugger enables access to the OCDR register. In all other cases, the standard I/O location is accessed. Refer to the debugger documentation for further information on how to use this registe 0x22 0x42 io_com.bmp Y OCDR7 IDRD On-Chip Debug Register Bit 7 RW 0 OCDR6 On-Chip Debug Register Bit 6 RW 0 OCDR5 On-Chip Debug Register Bit 5 RW 0 OCDR4 On-Chip Debug Register Bit 4 RW 0 OCDR3 On-Chip Debug Register Bit 3 RW 0 OCDR2 On-Chip Debug Register Bit 2 RW 0 OCDR1 On-Chip Debug Register Bit 1 RW 0 OCDR0 On-Chip Debug Register Bit 0 RW 0 MCUCSR MCU Control And Status Register The MCU Control and Status Register contains control bits for general MCU functions, and provides information on which reset source caused an MCU reset. 0x34 0x54 io_flag.bmp Y JTD JTAG Interface Disable When this bit is written to zero, the JTAG interface is enabled if the JTAGEN fuse is programmed. If this bit is written to one, the JTAG interface is disabled. In order to avoid unintentional disabling or enabling of the JTAG interface, a timed sequence must be followed: The application software must write this to the desired value twice within four cycles to change the bit. RW 0 JTRF JTAG Reset Flag This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on reset, or by writing a logic zero to the flag. RW 0 [SFIOR] io_cpu.bmp SFIOR Special Function IO Register 0x20 0x40 io_flag.bmp Y TSM Timer/Counter Synchronization Mode RW 0 ACME Analog Comparator Multiplexer Enable RW 0 PUD Pull Up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn registers are config-ured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See “Configuring the Pin” on page 52 for more details about this fea-ture. RW 0 PSR0 Prescaler Reset Timer/Counter0 RW 0 PSR321 PSR1 PSR2 PSR3 Prescaler Reset Timer/Counter3, Timer/Counter2, and Timer/Counter1 RW 0 [EICRA:EICRB:EIMSK:EIFR] io_ext.bmp The external interrupts are triggered by the INT7:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT7:0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The external inter-rupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the Exter-nal Interrupt Control Registers - EICRA (INT3:0) and EICRB (INT7:4). When the external interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT7:4 requires the presence of an I/O clock, described in “Clock Systems and their Distribution” on page 29. Low level interrupts and the edge interrupt on INT3:0 are detected asynchronously. This implies that these inter-rupts can be used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode. Note that if a level triggered interrupt is used for wake-up from Power Down Mode, the changed level must be held for some time to wake up the MCU. This makes the MCU less sensitive to noise. The changed level is sampled twice by the watchdog oscillator clock. The period of the watchdog oscillator is 1 µs (nominal) at 5.0V and 25°C. The frequency of the watchdog oscillator is voltage dependent as shown in the Electrical Characteristics section. The MCU will wake up if the input has the required level during this sampling or if it is held until the end of the start-up time. The start-up time is defined by the SUT fuses as described in “Clock Systems and their Distribution” on page 29. If the level is sampled twice by the watchdog oscillator clock but disappears before the end of the start-up time, the MCU will still wake up, but no interrupt will be generated. The required level must be held long enough for the MCU to complete the wake up to trigger the level interrupt EICRA External Interrupt Control Register A This Register can not be reached in ATmega103 compatibility mode, but the initial value defines INT3:0 as low level inter-rupts,as in ATmega103. • Bits 7..0 - ISC31, ISC30 - ISC00, ISC00: External Interrupt 3-0 Sense Control bits The External Interrupts 3 - 0 are activated by the external pins INT3:0 if the SREG I-flag and the corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that activate the interrupts are defined in Table 47. Edges on INT3..INT0 are registered asynchronously. Pulses on INT3:0 pins wider than the minimum pulse width given in Table 48 will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an interrupt request as long as the pin is held low. When changing the ISCn bit, an interrupt can occur. Therefore, it is recommended to first disable INTn by clearing its Interrupt Enable bit in the EIMSK register. Then, the ISCn bit can be changed. Finally, the INTn interrupt flag should be cleared by writing a logical one to its Interrupt Flag bit (INTFn) in the EIFR register before the interrupt is re-enable NA 0x6A io_flag.bmp Y ISC31 External Interrupt Sense Control Bit RW 0 ISC30 External Interrupt Sense Control Bit RW 0 ISC21 External Interrupt Sense Control Bit RW 0 ISC20 External Interrupt Sense Control Bit RW 0 ISC11 External Interrupt Sense Control Bit RW 0 ISC10 External Interrupt Sense Control Bit RW 0 ISC01 External Interrupt Sense Control Bit RW 0 ISC00 External Interrupt Sense Control Bit RW 0 EICRB External Interrupt Control Register B The External Interrupts 7 - 4 are activated by the external pins INT7:4 if the SREG I-flag and the corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that activate the interrupts are defined in Table 49. The value on the INT7:4 pins are sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL divider is enabled. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an interrupt request as long as the pin is held low 0x3A 0x5A io_flag.bmp Y ISC71 External Interrupt 7-4 Sense Control Bit RW 0 ISC70 External Interrupt 7-4 Sense Control Bit RW 0 ISC61 External Interrupt 7-4 Sense Control Bit RW 0 ISC60 External Interrupt 7-4 Sense Control Bit RW 0 ISC51 External Interrupt 7-4 Sense Control Bit RW 0 ISC50 External Interrupt 7-4 Sense Control Bit RW 0 ISC41 External Interrupt 7-4 Sense Control Bit RW 0 ISC40 External Interrupt 7-4 Sense Control Bit RW 0 EIMSK GICR GIMSK External Interrupt Mask Register When an INT7- INT4 bit is written to one and the I-bit in the Status Register (SREG) is set (one), the corresponding external pin interrupt is enabled. The Interrupt Sense Control bits in the External Interrupt Control Registers - EICRA and EICRB defines whether the external interrupt is activated on rising or falling edge or level sensed. Activity on any of these pins will trigger an interrupt request even if the pin is enabled as an output. This provides a way of generating a software interrupt. 0x39 0x59 io_flag.bmp Y INT7 External Interrupt Request 7 Enable RW 0 INT6 External Interrupt Request 6 Enable RW 0 INT5 External Interrupt Request 5 Enable RW 0 INT4 External Interrupt Request 4 Enable RW 0 INT3 External Interrupt Request 3 Enable RW 0 INT2 External Interrupt Request 2 Enable RW 0 INT1 External Interrupt Request 1 Enable RW 0 INT0 External Interrupt Request 0 Enable RW 0 EIFR GIFR External Interrupt Flag Register When an event on the INT7 - INT0 pins triggers an interrupt request, the corresponding interrupt flag, INTF7 - INTF0 becomes set (one). If the I-bit in SREG and the corresponding interrupt enable bit, INT7 - INT0 in EIMSK, are set (one), the MCU will jump to the interrupt vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag is cleared by writing a logical one to it. Note that when entering some sleep modes with the INT3:0 interrupts disabled, the input buffers on these pin will be disabled. This may cause a logic change in internal signals which will set the INTF3:0 flags. See “Digital Input Enable and Sleep Modes” on page 54 for more informa 0x38 0x58 io_flag.bmp Y INTF7 External Interrupt Flag 7 RW 0 INTF6 External Interrupt Flag 6 RW 0 INTF5 External Interrupt Flag 5 RW 0 INTF4 External Interrupt Flag 4 RW 0 INTF3 External Interrupt Flag 3 RW 0 INTF2 External Interrupt Flag 2 RW 0 INTF1 External Interrupt Flag 1 RW 0 INTF0 External Interrupt Flag 0 RW 0 [EEARH:EEARL:EEDR:EECR] [EEARH:EEARL] io_cpu.bmp EEPROM Read/Write Access. The EEPROM access registers are accessible in the I/O space. The write access time for the EEPROM is given in Table 1. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page 19. for details on how to avoid problems in these situations.In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When theEEPROM is written, the CPU is halted for two clock cycles before the next instruction is execute EEARH EEPROM Read/Write Access High Byte Bits 11..0 - EEAR11..0: EEPROM Address The EEPROM Address Registers - EEARH and EEARL specify the EEPROM address in the 4K bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 4096. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed. 0x1F 0x3F io_cpu.bmp N EEAR11 EEPROM Read/Write Access Bit 11 RW 0 EEAR10 EEPROM Read/Write Access Bit 10 RW 0 EEAR9 EEPROM Read/Write Access Bit 9 RW 0 EEAR8 EEPROM Read/Write Access Bit 8 RW 0 EEARL EEPROM Read/Write Access Low Byte Bits 11..0 - EEAR11..0: EEPROM Address The EEPROM Address Registers - EEARH and EEARL specify the EEPROM address in the 4K bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 4096. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed. 0x1E 0x3E io_cpu.bmp N EEARL7 EEPROM Read/Write Access Bit 7 RW 0 EEARL6 EEPROM Read/Write Access Bit 6 RW 0 EEARL5 EEPROM Read/Write Access Bit 5 RW 0 EEARL4 EEPROM Read/Write Access Bit 4 RW 0 EEARL3 EEPROM Read/Write Access Bit 3 RW 0 EEARL2 EEPROM Read/Write Access Bit 2 RW 0 EEARL1 EEPROM Read/Write Access Bit 1 RW 0 EEARL0 EEPROM Read/Write Access Bit 0 RW 0 EEDR EEPROM Data Register For the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR. 0x1D 0x3D io_cpu.bmp N EEDR7 EEPROM Data Register bit 7 RW 0 EEDR6 EEPROM Data Register bit 6 RW 0 EEDR5 EEPROM Data Register bit 5 RW 0 EEDR4 EEPROM Data Register bit 4 RW 0 EEDR3 EEPROM Data Register bit 3 RW 0 EEDR2 EEPROM Data Register bit 2 RW 0 EEDR1 EEPROM Data Register bit 1 RW 0 EEDR0 EEPROM Data Register bit 0 RW 0 EECR EEPROM Control Register 0x1C 0x3C io_flag.bmp Y EERIE EEPROM Ready Interrupt Enable EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared. RW 0 EEMWE EEPROM Master Write Enable The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is written to one, writing EEWE to one within 4 clock cycles will write data to the EEPROM at the selected address. If EEMWE is zero, writing EEWE to one will have no effect. When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure. RW 0 EEWE EEPROM Write Enable The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential): 1. Wait until EEWE becomes zero. 2. Wait until SPMEN in SPMCR becomes zero. 3. Write new EEPROM address to EEAR (optional). 4. Write new EEPROM data to EEDR (optional). 5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR. 6. Within four clock cycles after setting EEMWE, write a logical one to EEWE. The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a boot loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See “Boot Loader Support - Read While Write self-programming” on page 228 for details about boot programming. Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR regis-ter will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the 4 last steps to avoid these problems. When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruc-tion is executed RW X EERE EEPROM Read Enable The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR register. The calibrated oscillator is used to time the EEPROM accesses. Table 1 lists the typical programming time for EEPROM access from the CPU RW 0 [PORTA:DDRA:PINA] io_port.bmp AVRSimIOPort.SimIOPort PORTA Port A Data Register 0x1B 0x3B io_port.bmp N PORTA7 Port A Data Register bit 7 RW 0 PORTA6 Port A Data Register bit 6 RW 0 PORTA5 Port A Data Register bit 5 RW 0 PORTA4 Port A Data Register bit 4 RW 0 PORTA3 Port A Data Register bit 3 RW 0 PORTA2 Port A Data Register bit 2 RW 0 PORTA1 Port A Data Register bit 1 RW 0 PORTA0 Port A Data Register bit 0 RW 0 DDRA Port A Data Direction Register 0x1A 0x3A io_flag.bmp N DDA7 Data Direction Register, Port A, bit 7 RW 0 DDA6 Data Direction Register, Port A, bit 6 RW 0 DDA5 Data Direction Register, Port A, bit 5 RW 0 DDA4 Data Direction Register, Port A, bit 4 RW 0 DDA3 Data Direction Register, Port A, bit 3 RW 0 DDA2 Data Direction Register, Port A, bit 2 RW 0 DDA1 Data Direction Register, Port A, bit 1 RW 0 DDA0 Data Direction Register, Port A, bit 0 RW 0 PINA Port A Input Pins The Port A Input Pins address - PINA - is not a register, and this address enables access to the physical value on each Port A pin. When reading PORTA the Port A Data Latch is read, and when reading PINA, the logical values present on the pins are read. 0x19 0x39 io_port.bmp N PINA7 Input Pins, Port A bit 7 RW Hi-Z PINA6 Input Pins, Port A bit 6 RW Hi-Z PINA5 Input Pins, Port A bit 5 RW Hi-Z PINA4 Input Pins, Port A bit 4 RW Hi-Z PINA3 Input Pins, Port A bit 3 RW Hi-Z PINA2 Input Pins, Port A bit 2 RW Hi-Z PINA1 Input Pins, Port A bit 1 RW Hi-Z PINA0 Input Pins, Port A bit 0 RW Hi-Z [PORTB:DDRB:PINB] io_port.bmp AVRSimIOPort.SimIOPort PORTB Port B Data Register 0x18 0x38 io_port.bmp N PORTB7 Port B Data Register bit 7 RW 0 PORTB6 Port B Data Register bit 6 RW 0 PORTB5 Port B Data Register bit 5 RW 0 PORTB4 Port B Data Register bit 4 RW 0 PORTB3 Port B Data Register bit 3 RW 0 PORTB2 Port B Data Register bit 2 RW 0 PORTB1 Port B Data Register bit 1 RW 0 PORTB0 Port B Data Register bit 0 RW 0 DDRB Port B Data Direction Register 0x17 0x37 io_flag.bmp N DDB7 Port B Data Direction Register bit 7 RW 0 DDB6 Port B Data Direction Register bit 6 RW 0 DDB5 Port B Data Direction Register bit 5 RW 0 DDB4 Port B Data Direction Register bit 4 RW 0 DDB3 Port B Data Direction Register bit 3 RW 0 DDB2 Port B Data Direction Register bit 2 RW 0 DDB1 Port B Data Direction Register bit 1 RW 0 DDB0 Port B Data Direction Register bit 0 RW 0 PINB Port B Input Pins The Port B Input Pins address - PINB - is not a register, and this address enables access to the physical value on each Port B pin. When reading PORTB, the Port B Data Latch is read, and when reading PINB, the logical values present on the pins are read. 0x16 0x36 io_port.bmp N PINB7 Port B Input Pins bit 7 R 0 PINB6 Port B Input Pins bit 6 R 0 PINB5 Port B Input Pins bit 5 R 0 PINB4 Port B Input Pins bit 4 R 0 PINB3 Port B Input Pins bit 3 R 0 PINB2 Port B Input Pins bit 2 R 0 PINB1 Port B Input Pins bit 1 R 0 PINB0 Port B Input Pins bit 0 R 0 [PORTC:DDRC:PINC] io_port.bmp AVRSimIOPort.SimIOPort PORTC Port C Data Register 0x15 0x35 io_port.bmp N PORTC7 Port C Data Register bit 7 RW 0 PORTC6 Port C Data Register bit 6 RW 0 PORTC5 Port C Data Register bit 5 RW 0 PORTC4 Port C Data Register bit 4 RW 0 PORTC3 Port C Data Register bit 3 RW 0 PORTC2 Port C Data Register bit 2 RW 0 PORTC1 Port C Data Register bit 1 RW 0 PORTC0 Port C Data Register bit 0 RW 0 DDRC Port C Data Direction Register 0x14 0x34 io_flag.bmp N DDC7 Port C Data Direction Register bit 7 RW 0 DDC6 Port C Data Direction Register bit 6 RW 0 DDC5 Port C Data Direction Register bit 5 RW 0 DDC4 Port C Data Direction Register bit 4 RW 0 DDC3 Port C Data Direction Register bit 3 RW 0 DDC2 Port C Data Direction Register bit 2 RW 0 DDC1 Port C Data Direction Register bit 1 RW 0 DDC0 Port C Data Direction Register bit 0 RW 0 PINC Port C Input Pins The Port C Input Pins address - PINC - is not a register, and this address enables access to the physical value on each Port C pin. When reading PORTC, the Port C Data Latch is read, and when reading PINC, the logical values present on the pins are read. 0x13 0x33 io_port.bmp N PINC7 Port C Input Pins bit 7 R 0 PINC6 Port C Input Pins bit 6 R 0 PINC5 Port C Input Pins bit 5 R 0 PINC4 Port C Input Pins bit 4 R 0 PINC3 Port C Input Pins bit 3 R 0 PINC2 Port C Input Pins bit 2 R 0 PINC1 Port C Input Pins bit 1 R 0 PINC0 Port C Input Pins bit 0 R 0 [PORTD:DDRD:PIND] io_port.bmp AVRSimIOPort.SimIOPort PORTD Port D Data Register 0x12 0x32 io_port.bmp N PORTD7 Port D Data Register bit 7 RW 0 PORTD6 Port D Data Register bit 6 RW 0 PORTD5 Port D Data Register bit 5 RW 0 PORTD4 Port D Data Register bit 4 RW 0 PORTD3 Port D Data Register bit 3 RW 0 PORTD2 Port D Data Register bit 2 RW 0 PORTD1 Port D Data Register bit 1 RW 0 PORTD0 Port D Data Register bit 0 RW 0 DDRD Port D Data Direction Register 0x11 0x31 io_flag.bmp N DDD7 Port D Data Direction Register bit 7 RW 0 DDD6 Port D Data Direction Register bit 6 RW 0 DDD5 Port D Data Direction Register bit 5 RW 0 DDD4 Port D Data Direction Register bit 4 RW 0 DDD3 Port D Data Direction Register bit 3 RW 0 DDD2 Port D Data Direction Register bit 2 RW 0 DDD1 Port D Data Direction Register bit 1 RW 0 DDD0 Port D Data Direction Register bit 0 RW 0 PIND Port D Input Pins The Port D Input Pins address - PIND - is not a register, and this address enables access to the physical value on each Port D pin. When reading PORTD, the Port D Data Latch is read, and when reading PIND, the logical values present on the pins are read. 0x10 0x30 io_port.bmp N PIND7 Port D Input Pins bit 7 R 0 PIND6 Port D Input Pins bit 6 R 0 PIND5 Port D Input Pins bit 5 R 0 PIND4 Port D Input Pins bit 4 R 0 PIND3 Port D Input Pins bit 3 R 0 PIND2 Port D Input Pins bit 2 R 0 PIND1 Port D Input Pins bit 1 R 0 PIND0 Port D Input Pins bit 0 R 0 [PORTE:DDRE:PINE] io_port.bmp AVRSimIOPort.SimIOPort PORTE Data Register, Port E 0x03 0x23 io_port.bmp N PORTE7 RW 0 PORTE6 RW 0 PORTE5 RW 0 PORTE4 RW 0 PORTE3 RW 0 PORTE2 RW 0 PORTE1 RW 0 PORTE0 RW 0 DDRE Data Direction Register, Port E 0x02 0x22 io_flag.bmp N DDE7 RW 0 DDE6 RW 0 DDE5 RW 0 DDE4 RW 0 DDE3 RW 0 DDE2 RW 0 DDE1 RW 0 DDE0 RW 0 PINE Input Pins, Port E 0x01 0x21 io_port.bmp N PINE7 R 0 PINE6 R 0 PINE5 R 0 PINE4 R 0 PINE3 R 0 PINE2 R 0 PINE1 R 0 PINE0 R 0 [PORTF:DDRF:PINF] io_port.bmp AVRSimIOPort.SimIOPort PORTF Data Register, Port F NA 0x62 io_port.bmp N PORTF7 RW 0 PORTF6 RW 0 PORTF5 RW 0 PORTF4 RW 0 PORTF3 RW 0 PORTF2 RW 0 PORTF1 RW 0 PORTF0 RW 0 DDRF Data Direction Register, Port F NA 0x61 io_flag.bmp N DDF7 RW 0 DDF6 RW 0 DDF5 RW 0 DDF4 RW 0 DDF3 RW 0 DDF2 RW 0 DDF1 RW 0 DDF0 RW 0 PINF Input Pins, Port F 0x00 0x20 io_port.bmp N PINF7 R 0 PINF6 R 0 PINF5 R 0 PINF4 R 0 PINF3 R 0 PINF2 R 0 PINF1 R 0 PINF0 R 0 [PORTG:DDRG:PING] io_port.bmp AVRSimIOPort.SimIOPort PORTG Data Register, Port G NA 0x65 io_port.bmp N PORTG4 RW 0 PORTG3 RW 0 PORTG2 RW 0 PORTG1 RW 0 PORTG0 RW 0 DDRG Data Direction Register, Port G NA 0x64 io_flag.bmp N DDG4 RW 0 DDG3 RW 0 DDG2 RW 0 DDG1 RW 0 DDG0 RW 0 PING Input Pins, Port G NA 0x63 io_port.bmp N PING4 R 0 PING3 R 0 PING2 R 0 PING1 R 0 PING0 R 0 [TCCR0:TCNT0:OCR0:ASSR:TIMSK:TIFR:SFIOR] io_timer.bmp At8pwm1 TCCR0 Timer/Counter Control Register 0x33 0x53 io_flag.bmp Y FOC0 Force Output Compare The FOC0 bit is only active when the WGM bits specifies a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0 is written when operating in PWM mode. When writing a logical one to the FOC0 bit, an immediate compare match is forced on the waveform generation unit. The OC0 output is changed accord-ing to its COM01:0 bits setting. Note that the FOC0 bit is implemented as a strobe. Therefore it is the value present in the COM01:0 bits that determines the effect of the forced compare. A FOC0 strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0 as TOP. The FOC0 bit is always read as zero. W 0 WGM00 PWM0 Waveform Generation Mode 0 These bits control the counting sequence of the counter, the source for the maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See Table 51 and “Modes of Operation” on page 80. RW 0 COM01 Compare Match Output Mode 1 These bits control the output compare pin (OC0) behavior. If one or both of the COM01:0 bits are set, the OC0 output over-rides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to OC0 pin must be set in order to enable the output driver. When OC0 is connected to the pin, the function of the COM01:0 bits depends on the WGM01:0 bit setting. Table 52 shows the COM01:0 bit functionality when the WGM01:0 bits are set to a normal or CTC mode (non-PWM) RW 0 COM00 Compare match Output Mode 0 These bits control the output compare pin (OC0) behavior. If one or both of the COM01:0 bits are set, the OC0 output over-rides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to OC0 pin must be set in order to enable the output driver. When OC0 is connected to the pin, the function of the COM01:0 bits depends on the WGM01:0 bit setting. Table 52 shows the COM01:0 bit functionality when the WGM01:0 bits are set to a normal or CTC mode (non-PWM) RW 0 WGM01 CTC0 Waveform Generation Mode 1 These bits control the counting sequence of the counter, the source for the maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See Table 51 and “Modes of Operation” on page 80. RW 0 CS02 Clock Select 2 The three clock select bits select the clock source to be used by the Timer/Counter, RW 0 CS01 Clock Select 1 The three clock select bits select the clock source to be used by the Timer/Counter, RW 0 CS00 Clock Select 0 The three clock select bits select the clock source to be used by the Timer/Counter, RW 0 TCNT0 Timer/Counter Register The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT0 register blocks (removes) the compare match on the following timer clock. Modifying the counter (TCNT0) while the counter is running, introduces a risk of missing a compare match between TCNT0 the OCR0 register. 0x32 0x52 io_timer.bmp N TCNT0_7 RW 0 TCNT0_6 RW 0 TCNT0_5 RW 0 TCNT0_4 RW 0 TCNT0_3 RW 0 TCNT0_2 RW 0 TCNT0_1 RW 0 TCNT0_0 RW 0 OCR0 Output Compare Register The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC0 pin. 0x31 0x51 io_timer.bmp N OCR0_7 RW 0 OCR0_6 RW 0 OCR0_5 RW 0 OCR0_4 RW 0 OCR0_3 RW 0 OCR0_2 RW 0 OCR0_1 RW 0 OCR0_0 RW 0 ASSR Asynchronus Status Register 0x30 0x50 io_flag.bmp Y AS0 Asynchronus Timer/Counter 0 When AS0 is cleared, Timer/Counter 0 is clocked from the I/O clock, clk I/O . When AS0 is set, Timer/Counter 0 is clocked from a crystal oscillator connected to the Timer Oscillator 1 (TOSC1) pin. When the value of AS0 is changed, the contents of TCNT0, OCR0, and TCCR0 might be corrupted. RW 0 TCN0UB Timer/Counter0 Update Busy When Timer/Counter0 operates asynchronously and TCNT0 is written, this bit becomes set. When TCNT0 has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCNT0 is ready to be updated with a new value. RW 0 OCR0UB Output Compare register 0 Busy When Timer/Counter0 operates asynchronously and OCR0 is written, this bit becomes set. When OCR0 has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that OCR0 is ready to be updated with a new value. RW 0 TCR0UB Timer/Counter Control Register 0 Update Busy When Timer/Counter0 operates asynchronously and TCCR0 is written, this bit becomes set. When TCCR0 has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCCR0 is ready to be updated with a new value. If a write is performed to any of the three Timer/Counter0 registers while its update busy flag is set, the updated value might get corrupted and cause an unintentional interrupt to occur.The mechanisms for reading TCNT0, OCR0, and TCCR0 are different. When reading TCNT0, the actual timer value is read. When reading OCR0 or TCCR0, the value in the temporary storage register is read RW 0 TIMSK Timer/Counter Interrupt Mask Register 0x37 0x57 io_flag.bmp Y OCIE0 Timer/Counter0 Output Compare Match Interrupt register When the OCIE0 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Compare Match interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter0 occurs, i.e. when the OCF0 bit is set in the Timer/Counter Interrupt Flag Register - TIFR. RW 0 TOIE0 Timer/Counter0 Overflow Interrupt Enable When the TOIE0 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, i.e. when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register - TIFR. RW 0 TIFR Timer/Counter Interrupt Flag register 0x36 0x56 io_flag.bmp Y OCF0 Output Compare Flag 0 The OCF0 bit is set (one) when a compare match occurs between the Timer/Counter0 and the data in OCR0 - Output Compare Register0. OCF0 is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF0 is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0 (Timer/Counter0 Compare match Interrupt Enable), and OCF0 are set (one), the Timer/Counter0 Compare match Interrupt is executed. RW 0 TOV0 Timer/Counter0 Overflow Flag The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter0 changes counting direction at $00. RW 0 SFIOR Special Function IO Register 0x20 0x40 io_cpu.bmp Y TSM Timer/Counter Synchronization Mode Writing TSM to one, PSR0 and PSR321 becomes registers that hold their value until rewritten, or the TSM bit is written zero. This mode is useful for synchronizing timer/counters. By setting both TSM and the appropriate PSR bit(s), the appro-priate timer/counters are halted, and can be configured to same value without the risk of one of them advancing during con-figuration. When the TSM bit written zero, the Timer/Counters start counting simultaneously. R 0 PSR0 Prescaler Reset Timer/Counter0 When this bit is written to one, the Timer/Counter0 prescaler will be reset. The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. This bit will always be read as zero if Timer/Counter0 is clocked by the internal CPU clock. If this bit is written when Timer/Counter0 is operating in asynchronous mode, the bit will remain one until the prescaler has been reset. RW 0 [TIMSK:ETIMSK:TIFR:ETIFR:SFIOR:TCCR1A:TCCR1B:TCCR1C:TCNT1H:TCNT1L:OCR1AH:OCR1AL:OCR1BH:OCR1BL:OCR1CH:OCR1CL:ICR1H:ICR1L] [TCNT1H:TCNT1L];[OCR1AH:OCR1AL];[OCR1BH:OCR1BL];[OCR1CH:OCR1CL];[ICR1H:ICR1L] io_timer.bmp t16pwm1_01.xml TIMSK Timer/Counter Interrupt Mask Register 0x37 0x57 io_flag.bmp Y TICIE1 Timer/Counter1 Input Capture Interrupt Enable When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on pin 31, ICP, i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR. RW 0 OCIE1A Timer/Counter1 Output CompareA Match Interrupt Enable When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a CompareA match in Timer/Counter1 occurs, i.e., when the OCF1A bit is set in the Timer/Counter Interrupt Flag Register - TIFR. RW 0 OCIE1B Timer/Counter1 Output CompareB Match Interrupt Enable When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter1 occurs, i.e., when the OCF1B bit is set in the Timer/Counter Interrupt Flag Register - TIFR. R 0 TOIE1 Timer/Counter1 Overflow Interrupt Enable When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $006) is executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR. RW 0 ETIMSK Extended Timer/Counter Interrupt Mask Register NA 0x7D io_flag.bmp Y OCIE1C Timer/Counter 1, Output Compare Match C Interrupt Enable When this bit is written to one, and the I-flag in the status register is set (interrupts globally enabled), the timer/counter 1 output compare C match interrupt is enabled. The corresponding interrupt vector (See “Interrupts” on page 46.) is executed when the OCF1C flag, located in ETIFR, is set. RW 0 TIFR Timer/Counter Interrupt Flag register 0x36 0x56 io_flag.bmp Y ICF1 Input Capture Flag 1 The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to the input capture register - ICR1. ICF1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF1 is cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable), and ICF1 are set (one), the Timer/Counter1 Capture Interrupt is executed. RW 0 OCF1A Output Compare Flag 1A The OCF1A bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare match InterruptA Enable), and the OCF1A are set (one), the Timer/Counter1 Compare A match Interrupt is executed. RW 0 OCF1B Output Compare Flag 1B The OCF1B bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1B - Output Compare Register 1B. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1B (Timer/Counter1 Compare match InterruptB Enable), and the OCF1B are set (one), the Timer/Counter1 Compare B match Interrupt is executed. RW 0 TOV1 Timer/Counter1 Overflow Flag The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the cor-responding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter1 changes counting direction at $0000. RW 0 ETIFR Extended Timer/Counter Interrupt Flag register NA 0x7C io_flag.bmp Y OCF1C Timer/Counter 1, Output Compare C Match Flag This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register C (OCR1C). Note that a forced output compare (FOC1C) strobe will not set the OCF1C flag. OCF1C is automatically cleared when the Output Compare Match 1 C interrupt vector is executed. Alternatively, OCF1C can be cleared by writing a logic one to its bit location. RW 0 SFIOR Special Function IO Register 0x20 0x40 io_cpu.bmp Y TSM Timer/Counter Synchronization Mode • Bit 7 - TSM: Timer/Counter Synchronization Mode Writing TSM to one, PSR0 and PSR321 becomes registers that hold their value until rewritten, or the TSM bit is written zero. This mode is useful for synchronizing timer/counters. By setting both TSM and the appropriate PSR bit(s), the appro-priate timer/counters are halted, and can be configured to same value without the risk of one of them advancing during con-figuration. When the TSM bit written zero, the Timer/Counters start counting simultaneously. RW 0 PSR321 Prescaler Reset, T/C3, T/C2, T/C1 • Bit 0 - PSR321: Prescaler Reset Timer/Counter3, Timer/Counter2, and Timer/Counter1 Writing PSR321 to one resets the prescalter for Timer/Counter3, Timer/Counter2, and Timer/Counter1. The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. Note that Timer/Counter3 Timer/Counter2, and Timer/Counter1 share the same prescaler and a reset of this prescaler will affect both timers. This bit will always be read as zero. RW 0 TCCR1A Timer/Counter1 Control Register A Bit 7:6 - COMnA1:0: Compare Output Mode for channel A • Bit 5:4 - COMnB1:0: Compare Output Mode for channel B • Bit 3:2 - COMnC1:0: Compare Output Mode for channel C The COMnA1:0, COMnB1:0, and COMnC1:0 control the output compare pins (OCnA, OCnB, and OCnC respectively) behavior. If one or both of the COMnA1:0 bits are written to one, the OCnA output overrides the normal port functionality of the I/O pin it is connected to. If one or both of the COMnB1:0 bits are written to one, the OCnB output overrides the normal port functionality of the I/O pin it is connected to. If one or both of the COMnC1:0 bits are written to one, the OCnC output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to OCnA, OCnB or OCnC pin must be set in order to enable the output driver. When the OCnA, OCnB or OCnC is connected to the pin, the function of the COMnx1:0 bits are dependent of the WGMn3:0 bits setting. Table 57 shows the COMnx1 0 bit functionality when the WGMn3:0 bits are set to a normal or a CTC mode (non-PW 0x2F 0x4F io_flag.bmp Y COM1A1 Compare Output Mode 1A, bit 1 RW 0 COM1A0 Compare Ouput Mode 1A, bit 0 RW 0 COM1B1 Compare Output Mode 1B, bit 1 RW 0 COM1B0 Compare Output Mode 1B, bit 0 RW 0 COM1C1 Compare Output Mode 1C, bit 1 RW 0 COM1C0 Compare Output Mode 1C, bit 0 RW 0 WGM11 PWM11 Waveform Generation Mode Bit 1 Combined with the WGMn3:2 bits found in the TCCRnB register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 60. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. (See “Modes of Operation” on page 101.) RW 0 WGM10 PWM10 Waveform Generation Mode Bit 0 Combined with the WGMn3:2 bits found in the TCCRnB register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 60. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. (See “Modes of Operation” on page 101.) RW 0 TCCR1B Timer/Counter1 Control Register B 0x2E 0x4E io_flag.bmp Y ICNC1 Input Capture 1 Noise Canceler When the ICNC1 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the ICP - input capture pin - as specified. When the ICNC1 bit is set (one), four successive samples are measures on the ICP - input capture pin, and all samples must be high/low according to the input capture trigger specification in the ICES1 bit. The actual sampling frequency is XTAL clock frequency. RW 0 ICES1 Input Capture 1 Edge Select While the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the falling edge of the input capture pin - ICP. While the ICES1 bit is set (one), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the rising edge of the input capture pin - ICP. RW 0 WGM13 CTC11 Waveform Generation Mode See description found for TCCR1A RW 0 WGM12 CTC10 Waveform Generation Mode See description found for TCCR1A RW 0 CS12 Clock Select1 bit 2 Select clock source RW 0 CS11 Clock Select 1 bit 1 Select clock source RW 0 CS10 Clock Select bit 0 Select clock source RW 0 TCCR1C Timer/Counter1 Control Register C NA 0x7A io_flag.bmp Y FOC1A Force Output Compare for channel A • Bit 7- FOCnA: Force Output Compare for channel A • Bit 6- FOCnB: Force Output Compare for channel B • Bit 5- FOCnC: Force Output Compare for channel C The FOCnA/FOCnB//FOCnC bits are only active when the WGMn3:0 bits specifies a non-PWM mode. When writing a log-icalone to the FOCnA/FOCnB//FOCnC bit, an immediate compare match is forced on the waveform generation unit. The OCnA/OCnB/OCnC output is changed according to its COMnx1:0 bits setting. Note that the FOCnA/FOCnB/FOCnC bits are implemented as strobes. Therefore it is the value present in the COMnx1:0 bits that determine the effect of the forced compare. A FOCnA/FOCnB/FOCnC strobe will not generate any interrupt nor will it clear the timer in clear timer on compare match (CTC) mode using OCRnA as TOP. The FOCnA/FOCnB//FOCnB bits are always read as zero W 0 FOC1B Force Output Compare for channel B • Bit 7- FOCnA: Force Output Compare for channel A • Bit 6- FOCnB: Force Output Compare for channel B • Bit 5- FOCnC: Force Output Compare for channel C The FOCnA/FOCnB//FOCnC bits are only active when the WGMn3:0 bits specifies a non-PWM mode. When writing a log-icalone to the FOCnA/FOCnB//FOCnC bit, an immediate compare match is forced on the waveform generation unit. The OCnA/OCnB/OCnC output is changed according to its COMnx1:0 bits setting. Note that the FOCnA/FOCnB/FOCnC bits are implemented as strobes. Therefore it is the value present in the COMnx1:0 bits that determine the effect of the forced compare. A FOCnA/FOCnB/FOCnC strobe will not generate any interrupt nor will it clear the timer in clear timer on compare match (CTC) mode using OCRnA as TOP. The FOCnA/FOCnB//FOCnB bits are always read as zero W 0 FOC1C Force Output Compare for channel C • Bit 7- FOCnA: Force Output Compare for channel A • Bit 6- FOCnB: Force Output Compare for channel B • Bit 5- FOCnC: Force Output Compare for channel C The FOCnA/FOCnB//FOCnC bits are only active when the WGMn3:0 bits specifies a non-PWM mode. When writing a log-icalone to the FOCnA/FOCnB//FOCnC bit, an immediate compare match is forced on the waveform generation unit. The OCnA/OCnB/OCnC output is changed according to its COMnx1:0 bits setting. Note that the FOCnA/FOCnB/FOCnC bits are implemented as strobes. Therefore it is the value present in the COMnx1:0 bits that determine the effect of the forced compare. A FOCnA/FOCnB/FOCnC strobe will not generate any interrupt nor will it clear the timer in clear timer on compare match (CTC) mode using OCRnA as TOP. The FOCnA/FOCnB//FOCnB bits are always read as zero W 0 TCNT1H Timer/Counter1 High Byte This 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR1A, OCR1B and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt rou 0x2D 0x4D io_timer.bmp N TCNT1H7 Timer/Counter1 High Byte bit 7 RW 0 TCNT1H6 Timer/Counter1 High Byte bit 6 RW 0 TCNT1H5 Timer/Counter1 High Byte bit 5 RW 0 TCNT1H4 Timer/Counter1 High Byte bit 4 RW 0 TCNT1H3 Timer/Counter1 High Byte bit 3 RW 0 TCNT1H2 Timer/Counter1 High Byte bit 2 RW 0 TCNT1H1 Timer/Counter1 High Byte bit 1 RW 0 TCNT1H0 Timer/Counter1 High Byte bit 0 RW 0 TCNT1L Timer/Counter1 Low Byte This 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR1A, OCR1B and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt 0x2C 0x4C io_timer.bmp N TCNT1L7 Timer/Counter1 Low Byte bit 7 RW 0 TCNT1L6 Timer/Counter1 Low Byte bit 6 RW 0 TCNT1L5 Timer/Counter1 Low Byte bit 5 RW 0 TCNT1L4 Timer/Counter1 Low Byte bit 4 RW 0 TCNT1L3 Timer/Counter1 Low Byte bit 3 RW 0 TCNT1L2 Timer/Counter1 Low Byte bit 2 RW 0 TCNT1L1 Timer/Counter1 Low Byte bit 1 RW 0 TCNT1L0 Timer/Counter1 Low Byte bit 0 RW 0 OCR1AH Timer/Counter1 Outbut Compare Register High Byte The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt 0x2B 0x4B io_timer.bmp N OCR1AH7 Timer/Counter1 Outbut Compare Register High Byte bit 7 RW 0 OCR1AH6 Timer/Counter1 Outbut Compare Register High Byte bit 6 RW 0 OCR1AH5 Timer/Counter1 Outbut Compare Register High Byte bit 5 RW 0 OCR1AH4 Timer/Counter1 Outbut Compare Register High Byte bit 4 RW 0 OCR1AH3 Timer/Counter1 Outbut Compare Register High Byte bit 3 RW 0 OCR1AH2 Timer/Counter1 Outbut Compare Register High Byte bit 2 RW 0 OCR1AH1 Timer/Counter1 Outbut Compare Register High Byte bit 1 RW 0 OCR1AH0 Timer/Counter1 Outbut Compare Register High Byte bit 0 RW 0 OCR1AL Timer/Counter1 Outbut Compare Register Low Byte The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interru 0x2A 0x4A io_timer.bmp N OCR1AL7 Timer/Counter1 Outbut Compare Register Low Byte Bit 7 RW 0 OCR1AL6 Timer/Counter1 Outbut Compare Register Low Byte Bit 6 RW 0 OCR1AL5 Timer/Counter1 Outbut Compare Register Low Byte Bit 5 RW 0 OCR1AL4 Timer/Counter1 Outbut Compare Register Low Byte Bit 4 RW 0 OCR1AL3 Timer/Counter1 Outbut Compare Register Low Byte Bit 3 RW 0 OCR1AL2 Timer/Counter1 Outbut Compare Register Low Byte Bit 2 RW 0 OCR1AL1 Timer/Counter1 Outbut Compare Register Low Byte Bit 1 RW 0 OCR1AL0 Timer/Counter1 Outbut Compare Register Low Byte Bit 0 RW 0 OCR1BH Timer/Counter1 Output Compare Register High Byte The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt ro 0x29 0x49 io_timer.bmp N OCR1BH7 Timer/Counter1 Output Compare Register High Byte bit 7 RW 0 OCR1BH6 Timer/Counter1 Output Compare Register High Byte bit 6 RW 0 OCR1BH5 Timer/Counter1 Output Compare Register High Byte bit 5 RW 0 OCR1BH4 Timer/Counter1 Output Compare Register High Byte bit 4 RW 0 OCR1BH3 Timer/Counter1 Output Compare Register High Byte bit 3 RW 0 OCR1BH2 Timer/Counter1 Output Compare Register High Byte bit 2 RW 0 OCR1BH1 Timer/Counter1 Output Compare Register High Byte bit 1 RW 0 OCR1BH0 Timer/Counter1 Output Compare Register High Byte bit 0 RW 0 OCR1BL Timer/Counter1 Output Compare Register Low Byte The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt rout 0x28 0x48 io_timer.bmp N OCR1BL7 Timer/Counter1 Output Compare Register Low Byte bit 7 R 0 OCR1BL6 Timer/Counter1 Output Compare Register Low Byte bit 6 RW 0 OCR1BL5 Timer/Counter1 Output Compare Register Low Byte bit 5 RW 0 OCR1BL4 Timer/Counter1 Output Compare Register Low Byte bit 4 RW 0 OCR1BL3 Timer/Counter1 Output Compare Register Low Byte bit 3 RW 0 OCR1BL2 Timer/Counter1 Output Compare Register Low Byte bit 2 RW 0 OCR1BL1 Timer/Counter1 Output Compare Register Low Byte bit 1 RW 0 OCR1BL0 Timer/Counter1 Output Compare Register Low Byte bit 0 RW 0 OCR1CH Timer/Counter1 Output Compare Register High Byte The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt r NA 0x79 io_timer.bmp N OCR1CH7 Timer/Counter1 Output Compare Register High Byte bit 7 RW 0 OCR1CH6 Timer/Counter1 Output Compare Register High Byte bit 6 RW 0 OCR1CH5 Timer/Counter1 Output Compare Register High Byte bit 5 RW 0 OCR1CH4 Timer/Counter1 Output Compare Register High Byte bit 4 RW 0 OCR1CH3 Timer/Counter1 Output Compare Register High Byte bit 3 RW 0 OCR1CH2 Timer/Counter1 Output Compare Register High Byte bit 2 RW 0 OCR1CH1 Timer/Counter1 Output Compare Register High Byte bit 1 RW 0 OCR1CH0 Timer/Counter1 Output Compare Register High Byte bit 0 RW 0 OCR1CL Timer/Counter1 Output Compare Register Low Byte The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt rou NA 0x78 io_timer.bmp N OCR1CL7 Timer/Counter1 Output Compare Register Low Byte bit 7 R 0 OCR1CL6 Timer/Counter1 Output Compare Register Low Byte bit 6 RW 0 OCR1CL5 Timer/Counter1 Output Compare Register Low Byte bit 5 RW 0 OCR1CL4 Timer/Counter1 Output Compare Register Low Byte bit 4 RW 0 OCR1CL3 Timer/Counter1 Output Compare Register Low Byte bit 3 RW 0 OCR1CL2 Timer/Counter1 Output Compare Register Low Byte bit 2 RW 0 OCR1CL1 Timer/Counter1 Output Compare Register Low Byte bit 1 RW 0 OCR1CL0 Timer/Counter1 Output Compare Register Low Byte bit 0 RW 0 ICR1H Timer/Counter1 Input Capture Register High Byte The input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES1) of the signal at the input capture pin -ICP - is detected, the current value of the Timer/Counter1 is transferred to the Input Capture Register - ICR1. At the same time, the input capture flag - ICF1 - is set (one). Since the Input Capture Register - ICR1 - is a 16-bit register, a temporary register TEMP is used when ICR1 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR1L, the data is sent to the CPU and the data of the high byte ICR1H is placed in the TEMP register. When the CPU reads the data in the high byte ICR1H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR1L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT1, OCR1A and OCR1B. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt 0x27 0x47 io_timer.bmp N ICR1H7 Timer/Counter1 Input Capture Register High Byte bit 7 RW 0 ICR1H6 Timer/Counter1 Input Capture Register High Byte bit 6 R 0 ICR1H5 Timer/Counter1 Input Capture Register High Byte bit 5 R 0 ICR1H4 Timer/Counter1 Input Capture Register High Byte bit 4 R 0 ICR1H3 Timer/Counter1 Input Capture Register High Byte bit 3 R 0 ICR1H2 Timer/Counter1 Input Capture Register High Byte bit 2 R 0 ICR1H1 Timer/Counter1 Input Capture Register High Byte bit 1 R 0 ICR1H0 Timer/Counter1 Input Capture Register High Byte bit 0 R 0 ICR1L Timer/Counter1 Input Capture Register Low Byte The input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES1) of the signal at the input capture pin -ICP - is detected, the current value of the Timer/Counter1 is transferred to the Input Capture Register - ICR1. At the same time, the input capture flag - ICF1 - is set (one). Since the Input Capture Register - ICR1 - is a 16-bit register, a temporary register TEMP is used when ICR1 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR1L, the data is sent to the CPU and the data of the high byte ICR1H is placed in the TEMP register. When the CPU reads the data in the high byte ICR1H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR1L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT1, OCR1A and OCR1B. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within inter 0x26 0x46 io_timer.bmp N ICR1L7 Timer/Counter1 Input Capture Register Low Byte bit 7 R 0 ICR1L6 Timer/Counter1 Input Capture Register Low Byte bit 6 R 0 ICR1L5 Timer/Counter1 Input Capture Register Low Byte bit 5 R 0 ICR1L4 Timer/Counter1 Input Capture Register Low Byte bit 4 R 0 ICR1L3 Timer/Counter1 Input Capture Register Low Byte bit 3 R 0 ICR1L2 Timer/Counter1 Input Capture Register Low Byte bit 2 R 0 ICR1L1 Timer/Counter1 Input Capture Register Low Byte bit 1 R 0 ICR1L0 Timer/Counter1 Input Capture Register Low Byte bit 0 R 0 [TCCR2:TCNT2:OCR2:TIMSK:TIFR] io_timer.bmp t8pwm1_00 TCCR2 Timer/Counter Control Register 0x25 0x45 io_flag.bmp Y FOC2 Force Output Compare The FOC2 bit is only active when the WGM20 bit specifies a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR2 is written when operating in PWM mode. When writing a logical one to the FOC2 bit, an immediate compare match is forced on the waveform generation unit. The OC2 output is changed according to its COM21:0 bits setting. Note that the FOC2 bit is implemented as a strobe. Therefore it is the value present in the COM21:0 bits that determines the effect of the forced compare. A FOC2 strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR2 as TOP. The FOC2 bit is always read as zero. W 0 WGM20 PWM2 Wafeform Generation Mode These bits control the counting sequence of the counter, the source for the maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. RW 0 COM21 Compare Match Output Mode These bits control the output compare pin (OC2) behavior. If one or both of the COM21:0 bits are set, the OC2 output over-rides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to OC2 pin must be set in order to enable the output driver. When OC2 is connected to the pin, the function of the COM21:0 bits depends on the WGM21:0 bit setting. Table 64 shows the COM21:0 bit functionality when the WGM21:0 bits are set to a normal or CTC mode (non-PWM). RW 0 COM20 Compare Match Output Mode These bits control the output compare pin (OC2) behavior. If one or both of the COM21:0 bits are set, the OC2 output over-rides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to OC2 pin must be set in order to enable the output driver. When OC2 is connected to the pin, the function of the COM21:0 bits depends on the WGM21:0 bit setting. Table 64 shows the COM21:0 bit functionality when the WGM21:0 bits are set to a normal or CTC mode (non-PWM) RW 0 WGM21 CTC2 Waveform Generation Mode These bits control the counting sequence of the counter, the source for the maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. RW 0 CS22 Clock Select The three clock select bits select the clock source to be used by the Timer/Counter. RW 0 CS21 Clock Select The three clock select bits select the clock source to be used by the Timer/Counter. RW 0 CS20 Clock Select The three clock select bits select the clock source to be used by the Timer/Counter. RW 0 TCNT2 Timer/Counter Register The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT2 register blocks (removes) the compare match on the following timer clock. Modifying the counter (TCNT2) while the counter is running, introduces a risk of missing a compare match between TCNT2 the OCR2 register. 0x24 0x44 io_timer.bmp N TCNT2_7 Timer/Counter Register Bit 7 RW 0 TCNT2_6 Timer/Counter Register Bit 6 RW 0 TCNT2_5 Timer/Counter Register Bit 5 RW 0 TCNT2_4 Timer/Counter Register Bit 4 RW 0 TCNT2_3 Timer/Counter Register Bit 3 RW 0 TCNT2_2 Timer/Counter Register Bit 2 RW 0 TCNT2_1 Timer/Counter Register Bit 1 RW 0 TCNT2_0 Timer/Counter Register Bit 0 RW 0 OCR2 Output Compare Register The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC2 pin. 0x23 0x43 io_timer.bmp N OCR2_7 Output Compare Register Bit 7 RW 0 OCR2_6 Output Compare Register Bit 6 RW 0 OCR2_5 Output Compare Register Bit 5 RW 0 OCR2_4 Output Compare Register Bit 4 RW 0 OCR2_3 Output Compare Register Bit 3 RW 0 OCR2_2 Output Compare Register Bit 2 RW 0 OCR2_1 Output Compare Register Bit 1 RW 0 OCR2_0 Output Compare Register Bit 0 RW 0 TIFR Timer/Counter Interrupt Flag Register 0x36 0x56 io_flag.bmp Y OCF2 Output Compare Flag 2 The OCF2 bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2 - Output Compare Register2. OCF2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF2 is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2 (Timer/Counter2 Compare match Interrupt Enable), and OCF2 are set (one), the Timer/Counter2 Compare match Interrupt is executed. RW 0 TOV2 Timer/Counter2 Overflow Flag The bit TOV2 is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE2 (Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter2 changes counting direction at $00. RW 0 TIMSK 0x37 0x57 io_flag.bmp Y OCIE2 TOIE2 [ETIMSK:ETIFR:SFIOR:TCCR3A:TCCR3B:TCCR3C:TCNT3H:TCNT3L:OCR3AH:OCR3AL:OCR3BH:OCR3BL:OCR3CH:OCR3CL:ICR3H:ICR3L] [TCNT3H:TCNT3L];[OCR3AH:OCR3AL];[OCR3BH:OCR3BL];[OCR3CH:OCR3CL];[ICR3H:ICR3L] io_timer.bmp t16pwm1_03.xml ETIMSK Extended Timer/Counter Interrupt Mask Register NA 0x7D io_flag.bmp Y TICIE3 Timer/Counter3 Input Capture Interrupt Enable When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter3 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on pin 31, ICP, i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR. RW 0 OCIE3A Timer/Counter3 Output CompareA Match Interrupt Enable When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter3 CompareA Match interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a CompareA match in Timer/Counter3 occurs, i.e., when the OCF3Abit is set in the Timer/Counter Interrupt Flag Register - TIFR. RW 0 OCIE3B Timer/Counter3 Output CompareB Match Interrupt Enable When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter3 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter3 occurs, i.e., when the OCF3Bbit is set in the Timer/Counter Interrupt Flag Register - TIFR. R 0 TOIE3 Timer/Counter3 Overflow Interrupt Enable When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter3 Overflow interrupt is enabled. The corresponding interrupt (at vector $006) is executed if an overflow in Timer/Counter3 occurs, i.e., when the TOV3bit is set in the Timer/Counter Interrupt Flag Register - TIFR. RW 0 OCIE3C Timer/Counter3, Output Compare Match Interrupt Enable When this bit is written to one, and the I-flag status register is set (interrupts globally enabled), the timer/counter3 output compare C match interrupt is enabled. The corresponding interrupt vector is executed when the OCF3C flag, located in ETIFR is set. RW 0 ETIFR Extended Timer/Counter Interrupt Flag register NA 0x7C io_flag.bmp Y ICF3 Input Capture Flag 1 The ICF3 bit is set (one) to flag an input capture event, indicating that the Timer/Counter3 value has been transferred to the input capture register - ICR1. ICF1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF3 is cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE3 (Timer/Counter3 Input Capture Interrupt Enable), and ICF3 are set (one), the Timer/Counter3 Capture Interrupt is executed. RW 0 OCF3A Output Compare Flag 1A The OCF3Abit is set (one) when compare match occurs between the Timer/Counter3 and the data in OCR1A - Output Compare Register 1A. OCF3Ais cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF3Ais cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter3 Compare match InterruptA Enable), and the OCF3Aare set (one), the Timer/Counter3 Compare A match Interrupt is executed. RW 0 OCF3B Output Compare Flag 1B The OCF3Bbit is set (one) when compare match occurs between the Timer/Counter3 and the data in OCR3B- Output Compare Register 1B. OCF3Bis cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF3Bis cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1B (Timer/Counter3 Compare match InterruptB Enable), and the OCF3Bare set (one), the Timer/Counter3 Compare B match Interrupt is executed. RW 0 TOV3 Timer/Counter3 Overflow Flag The TOV3is set (one) when an overflow occurs in Timer/Counter3. TOV3is cleared by hardware when executing the cor-responding interrupt handling vector. Alternatively, TOV3is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE1 (Timer/Counter3 Overflow Interrupt Enable), and TOV3are set (one), the Timer/Counter3 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter3 changes counting direction at $0000. RW 0 OCF3C Timer/Counter3 Output Compare C Match Flag This flag is set in the timer clock sycle after the counter (TCNT3) value matches the Output Compare Register C (OCR3C) RW 0 SFIOR Special Function IO Register 0x20 0x40 io_cpu.bmp Y TSM Timer/Counter Synchronization Mode • Bit 7 - TSM: Timer/Counter Synchronization Mode Writing TSM to one, PSR0 and PSR321 becomes registers that hold their value until rewritten, or the TSM bit is written zero. This mode is useful for synchronizing timer/counters. By setting both TSM and the appropriate PSR bit(s), the appro-priate timer/counters are halted, and can be configured to same value without the risk of one of them advancing during con-figuration. When the TSM bit written zero, the Timer/Counters start counting simultaneously. RW 0 PSR321 PSR1 PSR2 Prescaler Reset, T/C3, T/C2, T/C1 • Bit 0 - PSR321: Prescaler Reset Timer/Counter3, Timer/Counter2, and Timer/Counter3 Writing PSR321 to one resets the prescalter for Timer/Counter3, Timer/Counter2, and Timer/Counter3. The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. Note that Timer/Counter3 Timer/Counter2, and Timer/Counter3 share the same prescaler and a reset of this prescaler will affect both timers. This bit will always be read as zero. RW 0 TCCR3A Timer/Counter3 Control Register A Bit 7:6 - COMnA1:0: Compare Output Mode for channel A • Bit 5:4 - COMnB1:0: Compare Output Mode for channel B • Bit 3:2 - COMnC1:0: Compare Output Mode for channel C The COMnA1:0, COMnB1:0, and COMnC1:0 control the output compare pins (OCnA, OCnB, and OCnC respectively) behavior. If one or both of the COMnA1:0 bits are written to one, the OCnA output overrides the normal port functionality of the I/O pin it is connected to. If one or both of the COMnB1:0 bits are written to one, the OCnB output overrides the normal port functionality of the I/O pin it is connected to. If one or both of the COMnC1:0 bits are written to one, the OCnC output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to OCnA, OCnB or OCnC pin must be set in order to enable the output driver. When the OCnA, OCnB or OCnC is connected to the pin, the function of the COMnx1:0 bits are dependent of the WGMn3:0 bits setting. Table 57 shows the COMnx1 0 bit functionality when the WGMn3:0 bits are set to a normal or a CTC mode (non- NA 0x8B io_flag.bmp Y COM3A1 Compare Output Mode 3A, bit 1 RW 0 COM3A0 Comparet Ouput Mode 3A, bit 0 RW 0 COM3B1 Compare Output Mode 3B, bit 1 RW 0 COM3B0 Compare Output Mode 3B, bit 0 RW 0 COM3C1 Compare Output Mode 3C, bit 1 RW 0 COM3C0 Compare Output Mode 3C, bit 0 RW 0 WGM31 PWM31 Waveform Generation Mode Bit 1 Combined with the WGMn3:2 bits found in the TCCRnB register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 60. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. (See “Modes of Operation” on page 101.) RW 0 WGM30 PWM30 Waveform Generation Mode Bit 0 Combined with the WGMn3:2 bits found in the TCCRnB register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 60. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. (See “Modes of Operation” on page 101.) RW 0 TCCR3B Timer/Counter3 Control Register B NA 0x8A io_flag.bmp Y ICNC3 Input Capture 3 Noise Canceler When the ICNC3 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the ICP - input capture pin - as specified. When the ICNC3 bit is set (one), four successive samples are measures on the ICP - input capture pin, and all samples must be high/low according to the input capture trigger specification in the ICES3 bit. The actual sampling frequency is XTAL clock frequency. RW 0 ICES3 Input Capture 3 Edge Select While the ICES3 bit is cleared (zero), the Timer/Counter3 contents are transferred to the Input Capture Register - ICR3 - on the falling edge of the input capture pin - ICP. While the ICES3 bit is set (one), the Timer/Counter3 contents are transferred to the Input Capture Register - ICR3 - on the rising edge of the input capture pin - ICP. RW 0 WGM33 CTC31 Waveform Generation Mode See description found for TCCR3A RW 0 WGM32 CTC30 Waveform Generation Mode See description found for TCCR3A RW 0 CS32 Clock Select3 bit 2 Select clock source RW 0 CS31 Clock Select 3 bit 1 Select clock source RW 0 CS30 Clock Select 3 bit 0 Select clock source RW 0 TCCR3C Timer/Counter3 Control Register C NA 0x8C io_flag.bmp Y FOC3A Force Output Compare for channel A • Bit 7- FOCnA: Force Output Compare for channel A • Bit 6- FOCnB: Force Output Compare for channel B • Bit 5- FOCnC: Force Output Compare for channel C The FOCnA/FOCnB//FOCnC bits are only active when the WGMn3:0 bits specifies a non-PWM mode. When writing a log-icalone to the FOCnA/FOCnB//FOCnC bit, an immediate compare match is forced on the waveform generation unit. The OCnA/OCnB/OCnC output is changed according to its COMnx1:0 bits setting. Note that the FOCnA/FOCnB/FOCnC bits are implemented as strobes. Therefore it is the value present in the COMnx1:0 bits that determine the effect of the forced compare. A FOCnA/FOCnB/FOCnC strobe will not generate any interrupt nor will it clear the timer in clear timer on compare match (CTC) mode using OCRnA as TOP. The FOCnA/FOCnB//FOCnB bits are always read as zer W 0 FOC3B Force Output Compare for channel B • Bit 7- FOCnA: Force Output Compare for channel A • Bit 6- FOCnB: Force Output Compare for channel B • Bit 5- FOCnC: Force Output Compare for channel C The FOCnA/FOCnB//FOCnC bits are only active when the WGMn3:0 bits specifies a non-PWM mode. When writing a log-icalone to the FOCnA/FOCnB//FOCnC bit, an immediate compare match is forced on the waveform generation unit. The OCnA/OCnB/OCnC output is changed according to its COMnx1:0 bits setting. Note that the FOCnA/FOCnB/FOCnC bits are implemented as strobes. Therefore it is the value present in the COMnx1:0 bits that determine the effect of the forced compare. A FOCnA/FOCnB/FOCnC strobe will not generate any interrupt nor will it clear the timer in clear timer on compare match (CTC) mode using OCRnA as TOP. The FOCnA/FOCnB//FOCnB bits are always read as zer W 0 FOC3C Force Output Compare for channel C • Bit 7- FOCnA: Force Output Compare for channel A • Bit 6- FOCnB: Force Output Compare for channel B • Bit 5- FOCnC: Force Output Compare for channel C The FOCnA/FOCnB//FOCnC bits are only active when the WGMn3:0 bits specifies a non-PWM mode. When writing a log-icalone to the FOCnA/FOCnB//FOCnC bit, an immediate compare match is forced on the waveform generation unit. The OCnA/OCnB/OCnC output is changed according to its COMnx1:0 bits setting. Note that the FOCnA/FOCnB/FOCnC bits are implemented as strobes. Therefore it is the value present in the COMnx1:0 bits that determine the effect of the forced compare. A FOCnA/FOCnB/FOCnC strobe will not generate any interrupt nor will it clear the timer in clear timer on compare match (CTC) mode using OCRnA as TOP. The FOCnA/FOCnB//FOCnB bits are always read as zero W 0 TCNT3H Timer/Counter3 High Byte This 16-bit register contains the prescaled value of the 16-bit Timer/Counter3. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR1A, OCR3Band ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt NA 0x89 io_timer.bmp N TCNT3H7 Timer/Counter 3 bit 15 RW 0 TCNT3H6 Timer/Counter 3 bit 14 RW 0 TCNT3H5 Timer/Counter 3 bit 13 RW 0 TCNT3H4 Timer/Counter 3 bit 12 RW 0 TCNT3H3 Timer/Counter 3 bit 11 RW 0 TCNT3H2 Timer/Counter 3 bit 10 RW 0 TCNT3H1 Timer/Counter 3 bit 9 RW 0 TCNT3H0 Timer/Counter 3 bit 8 RW 0 TCNT3L Timer/Counter3 Low Byte This 16-bit register contains the prescaled value of the 16-bit Timer/Counter3. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR1A, OCR3Band ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrup NA 0x88 io_timer.bmp N TCN3L7 Timer/Counter 3 bit 7 RW 0 TCN3L6 Timer/Counter 3 bit 6 RW 0 TCN3L5 Timer/Counter 3 bit 5 RW TCN3L4 Timer/Counter 3 bit 4 RW 0 TCN3L3 Timer/Counter 3 bit 3 RW 0 TCN3L2 Timer/Counter 3 bit 2 RW 0 TCN3L1 Timer/Counter 3 bit 1 RW 0 TCN3L0 Timer/Counter 3 bit 0 RW 0 OCR3AH Timer/Counter3 Outbut Compare Register A High Byte The output compare registers are 16-bit read/write registers. The Timer/Counter3 Output Compare Registers contain the data to be continuously compared with Timer/Counter3. Actions on compare matches are specified in the Timer/Counter3 Control and Status register.A compare match does only occur if Timer/Counter3 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR3Bto the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR3B- are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR3AH or OCR3BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR3AL or OCR3BL, the TEMP register is simultaneously written to OCR3AH or OCR3BH. Consequently, the high byte OCR3AH or OCR3BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interru NA 0x87 io_timer.bmp N OCR3AH7 Timer/Counter3 Output Compare Register A bit 15 RW 0 OCR3AH6 Timer/Counter3 Output Compare Register A bit 14 RW 0 OCR3AH5 Timer/Counter3 Output Compare Register A bit 13 RW 0 OCR3AH4 Timer/Counter3 Output Compare Register A bit 12 RW 0 OCR3AH3 Timer/Counter3 Output Compare Register A bit 11 RW 0 OCR3AH2 Timer/Counter3 Output Compare Register A bit 10 RW 0 OCR3AH1 Timer/Counter3 Output Compare Register A bit 9 RW 0 OCR3AH0 Timer/Counter3 Output Compare Register A bit 8 RW 0 OCR3AL Timer/Counter3 Outbut Compare Register A Low Byte The output compare registers are 16-bit read/write registers. The Timer/Counter3 Output Compare Registers contain the data to be continuously compared with Timer/Counter3. Actions on compare matches are specified in the Timer/Counter3 Control and Status register.A compare match does only occur if Timer/Counter3 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR3Bto the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR3B- are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR3AH or OCR3BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR3AL or OCR3BL, the TEMP register is simultaneously written to OCR3AH or OCR3BH. Consequently, the high byte OCR3AH or OCR3BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within inte NA 0x86 io_timer.bmp N OCR3AL7 Timer/Counter3 Output Compare Register A bit 7 RW 0 OCR3AL6 Timer/Counter3 Output Compare Register A bit 6 RW 0 OCR3AL5 Timer/Counter3 Output Compare Register A bit 5 RW 0 OCR3AL4 Timer/Counter3 Output Compare Register A bit 4 RW 0 OCR3AL3 Timer/Counter3 Output Compare Register A bit 3 RW 0 OCR3AL2 Timer/Counter3 Output Compare Register A bit 2 RW 0 OCR3AL1 Timer/Counter3 Output Compare Register A bit 1 RW 0 OCR3AL0 Timer/Counter3 Output Compare Register A bit 0 RW 0 OCR3BH Timer/Counter3 Output Compare Register B High Byte The output compare registers are 16-bit read/write registers. The Timer/Counter3 Output Compare Registers contain the data to be continuously compared with Timer/Counter3. Actions on compare matches are specified in the Timer/Counter3 Control and Status register.A compare match does only occur if Timer/Counter3 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR3Bto the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR3B- are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR3AH or OCR3BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR3AL or OCR3BL, the TEMP register is simultaneously written to OCR3AH or OCR3BH. Consequently, the high byte OCR3AH or OCR3BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrup NA 0x85 io_timer.bmp N OCR3BH7 Timer/Counter3 Output Compare Register B bit 15 RW 0 OCR3BH6 Timer/Counter3 Output Compare Register B bit 14 RW 0 OCR3BH5 Timer/Counter3 Output Compare Register B bit 13 RW 0 OCR3BH4 Timer/Counter3 Output Compare Register B bit 12 RW 0 OCR3BH3 Timer/Counter3 Output Compare Register B bit 11 RW 0 OCR3BH2 Timer/Counter3 Output Compare Register B bit 10 RW 0 OCR3BH1 Timer/Counter3 Output Compare Register B bit 9 RW 0 OCR3BH0 Timer/Counter3 Output Compare Register B bit 8 RW 0 OCR3BL Timer/Counter3 Output Compare Register B Low Byte The output compare registers are 16-bit read/write registers. The Timer/Counter3 Output Compare Registers contain the data to be continuously compared with Timer/Counter3. Actions on compare matches are specified in the Timer/Counter3 Control and Status register.A compare match does only occur if Timer/Counter3 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR3Bto the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR3B- are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR3AH or OCR3BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR3AL or OCR3BL, the TEMP register is simultaneously written to OCR3AH or OCR3BH. Consequently, the high byte OCR3AH or OCR3BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt r NA 0x84 io_timer.bmp N OCR3BL7 Timer/Counter3 Output Compare Register B bit 7 RW 0 OCR3BL6 Timer/Counter3 Output Compare Register B bit 6 RW 0 OCR3BL5 Timer/Counter3 Output Compare Register B bit 5 RW 0 OCR3BL4 Timer/Counter3 Output Compare Register B bit 4 RW 0 OCR3BL3 Timer/Counter3 Output Compare Register B bit 3 RW 0 OCR3BL2 Timer/Counter3 Output Compare Register B bit 2 RW 0 OCR3BL1 Timer/Counter3 Output Compare Register B bit 1 RW 0 OCR3BL0 Timer/Counter3 Output Compare Register 3 B bit 0 RW 0 OCR3CH Timer/Counter3 Output compare Register C High Byte The output compare registers are 16-bit read/write registers. The Timer/Counter3 Output Compare Registers contain the data to be continuously compared with Timer/Counter3. Actions on compare matches are specified in the Timer/Counter3 Control and Status register.A compare match does only occur if Timer/Counter3 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR3Bto the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR3B- are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR3AH or OCR3BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR3AL or OCR3BL, the TEMP register is simultaneously written to OCR3AH or OCR3BH. Consequently, the high byte OCR3AH or OCR3BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within NA 0x83 io_timer.bmp N OCR3CH7 Timer/Counter3 Output compare Register C 15 RW 0 OCR3CH6 Timer/Counter3 Output compare Register C 14 RW 0 OCR3CH5 Timer/Counter3 Output compare Register C 13 RW 0 OCR3CH4 Timer/Counter3 Output compare Register C 12 RW 0 OCR3CH3 Timer/Counter3 Output compare Register C 11 RW 0 OCR3CH2 Timer/Counter3 Output compare Register C 10 RW 0 OCR3CH1 Timer/Counter3 Output compare Register C 9 RW 0 OCR3CH0 Timer/Counter3 Output compare Register C 8 RW 0 OCR3CL Timer/Counter3 Output compare register C Low byte The output compare registers are 16-bit read/write registers. The Timer/Counter3 Output Compare Registers contain the data to be continuously compared with Timer/Counter3. Actions on compare matches are specified in the Timer/Counter3 Control and Status register.A compare match does only occur if Timer/Counter3 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR3Bto the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR3B- are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR3AH or OCR3BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR3AL or OCR3BL, the TEMP register is simultaneously written to OCR3AH or OCR3BH. Consequently, the high byte OCR3AH or OCR3BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from with NA 0x82 io_timer.bmp N OCR3CL7 Timer/Counter3 Output compare register C bit 7 RW 0 OCR3CL6 Timer/Counter3 Output compare register C bit 6 RW 0 OCR3CL5 Timer/Counter3 Output compare register C bit 5 RW 0 OCR3CL4 Timer/Counter3 Output compare register C bit 4 RW 0 OCR3CL3 Timer/Counter3 Output compare register C bit 3 RW 0 OCR3CL2 Timer/Counter3 Output compare register C bit 2 RW 0 OCR3CL1 Timer/Counter3 Output compare register C bit 1 RW 0 OCR3CL0 Timer/Counter3 Output compare register C bit 0 RW 0 ICR3H Timer/Counter3 Input Capture Register High Byte The input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES3) of the signal at the input capture pin -ICP - is detected, the current value of the Timer/Counter3 is transferred to the Input Capture Register - ICR1. At the same time, the input capture flag - ICF1 - is set (one). Since the Input Capture Register - ICR1 - is a 16-bit register, a temporary register TEMP is used when ICR1 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR3L, the data is sent to the CPU and the data of the high byte ICR3H is placed in the TEMP register. When the CPU reads the data in the high byte ICR3H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR3L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT1, OCR1A and OCR1B. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt NA 0x81 io_timer.bmp N ICR3H7 Timer/Counter3 Input Capture Register bit 15 RW 0 ICR3H6 Timer/Counter3 Input Capture Register bit 14 RW 0 ICR3H5 Timer/Counter3 Input Capture Register bit 13 RW 0 ICR3H4 Timer/Counter3 Input Capture Register bit 12 RW 0 ICR3H3 Timer/Counter3 Input Capture Register bit 11 RW 0 ICR3H2 Timer/Counter3 Input Capture Register bit 10 RW 0 ICR3H1 Timer/Counter3 Input Capture Register bit 9 RW 0 ICR3H0 Timer/Counter3 Input Capture Register bit 8 RW 0 ICR3L Timer/Counter3 Input Capture Register Low Byte The input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES3) of the signal at the input capture pin -ICP - is detected, the current value of the Timer/Counter3 is transferred to the Input Capture Register - ICR1. At the same time, the input capture flag - ICF1 - is set (one). Since the Input Capture Register - ICR1 - is a 16-bit register, a temporary register TEMP is used when ICR1 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR3L, the data is sent to the CPU and the data of the high byte ICR3H is placed in the TEMP register. When the CPU reads the data in the high byte ICR3H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR3L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT1, OCR1A and OCR1B. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within inter NA 0x80 io_timer.bmp N ICR3L7 Timer/Counter3 Input Capture Register bit 7 RW 0 ICR3L6 Timer/Counter3 Input Capture Register bit 6 RW 0 ICR3L5 Timer/Counter3 Input Capture Register bit 5 RW 0 ICR3L4 Timer/Counter3 Input Capture Register bit 4 RW 0 ICR3L3 Timer/Counter3 Input Capture Register bit 3 RW 0 ICR3L2 Timer/Counter3 Input Capture Register bit 2 RW 0 ICR3L1 Timer/Counter3 Input Capture Register bit 1 RW 0 ICR3L0 Timer/Counter3 Input Capture Register bit 0 RW 0 [WDTCR] io_watch.bmp WDTCR WDTCSR Watchdog Timer Control Register 0x21 0x41 io_flag.bmp Y WDCE WDTOE Watchdog Change Enable This bit must be set when the WDE bit is written to logic zero.Otherwise,the watchdog will not be disabled.Once written to one,hardware will clear this bit after four clock cycles.Refer to the description of the WDE bit for a watchdog disable procedure.This bit must also be set when changing the prescaler bits. RW 0 WDE Watch Dog Enable When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog RW 0 WDP2 Watch Dog Timer Prescaler bit 2 The WDP2,WDP1,and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. RW 0 WDP1 Watch Dog Timer Prescaler bit 1 The WDP2,WDP1,and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. RW 0 WDP0 Watch Dog Timer Prescaler bit 0 The WDP2,WDP1,and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. RW 0 [ADMUX:ADCSRA:ADCH:ADCL] ((IF ADMUX.ADLAR = 1) LINK [ADCH(1:0):ADCL(7:0)]); (IF ADMUX.ADLAR = 0) LINK [ADCH(7:0):ADCL(7:6)]); io_analo.bmp AD Converter Feature list: 10-bit Resolution. 0.5 LSB Integral Non-Linearity. +-2 LSB Absolute Accuracy. TBD - 260 µs Conversion Time. Up to TBD kSPS at maximum resolution. 8 Multiplexed Single Ended Input Channels. 7 Differential input channels (TQFP package only). 2 Differential input channels with optional gain of 10x and 200x (TQFP package only). Optional left adjustment for ADC result readout. 0 - VCC ADC Input Voltage Range. Selectable 2.56 V ADC reference voltage. Free Running or Single Conversion Mode. Interrupt on ADC Conversion Complete. Sleep Mode Noise ADMUX The ADC multiplexer Selection Register 0x07 0x27 io_analo.bmp Y REFS1 Reference Selection Bit 1 These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin. RW 0 REFS0 Reference Selection Bit 0 These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin. RW 0 ADLAR Left Adjust Result The ADLAR bit affects the presentation of the ADC conversion result in the ADC data register. If ADLAR is cleared, the result is right adjusted. If ADLAR is set, the result is left adjusted. Changing the ADLAR bit will affect the ADC data register immediately, regardless of any ongoing conversions. For a complete description of this bit, see “The ADC Data Register -ADCL and ADCH” on page 198. RW 0 MUX4 Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). RW 0 MUX3 Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). RW 0 MUX2 Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). RW 0 MUX1 Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). RW 0 MUX0 Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). RW 0 ADCSRA ADCSR The ADC Control and Status register 0x06 0x26 io_flag.bmp Y ADEN ADC Enable Writing a logical ‘1’ to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion. RW 0 ADSC ADC Start Conversion In Single Conversion Mode, a logical ‘1’ must be written to this bit to start each conversion. In Free Running Mode, a logical ‘1’ must be written to this bit to start the first conversion. The first time ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, an extended conversion will result. This extended conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. When a dummy conversion precedes a real conversion, ADSC will stay high until the real conversion completes. Writing a 0 to this bit has no effect RW 0 ADFR ADC Free Running Select When this bit is set (one) the ADC operates in Free Running Mode. In this mode, the ADC samples and updates the data registers continuously. Clearing this bit (zero) will terminate Free Running Mode. RW 0 ADIF ADC Interrupt Flag This bit is set (one) when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set (one). ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a read-modify-write on ADCSR, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used. RW 0 ADIE ADC Interrupt Enable When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Complete Interrupt is activated. RW 0 ADPS2 ADC Prescaler Select Bits These bits determine the division factor between the XTAL frequency and the input clock to the ADC. RW 0 ADPS1 ADC Prescaler Select Bits These bits determine the division factor between the XTAL frequency and the input clock to the ADC. RW 0 ADPS0 ADC Prescaler Select Bits These bits determine the division factor between the XTAL frequency and the input clock to the ADC. RW 0 ADCH ADC Data Register High Byte When an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. The selected channel is differential if MUX4..0 are between ‘01000’ and ‘11101’, otherwise the selected channel is single ended. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8 bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUX4..0 bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adju 0x05 0x25 io_analo.bmp N ADCH7 ADC Data Register High Byte Bit 7 RW 0 ADCH6 ADC Data Register High Byte Bit 6 RW 0 ADCH5 ADC Data Register High Byte Bit 5 RW 0 ADCH4 ADC Data Register High Byte Bit 4 RW 0 ADCH3 ADC Data Register High Byte Bit 3 RW 0 ADCH2 ADC Data Register High Byte Bit 2 RW 0 ADCH1 ADC Data Register High Byte Bit 1 RW 0 ADCH0 ADC Data Register High Byte Bit 0 RW 0 ADCL ADC Data Register Low Byte When an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. The selected channel is differential if MUX4..0 are between ‘01000’ and ‘11101’, otherwise the selected channel is single ended. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8 bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUX4..0 bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right ad 0x04 0x24 io_analo.bmp N ADCL7 ADC Data Register Low Byte Bit 7 RW 0 ADCL6 ADC Data Register Low Byte Bit 6 RW 0 ADCL5 ADC Data Register Low Byte Bit 5 RW 0 ADCL4 ADC Data Register Low Byte Bit 4 RW 0 ADCL3 ADC Data Register Low Byte Bit 3 RW 0 ADCL2 ADC Data Register Low Byte Bit 2 RW 0 ADCL1 ADC Data Register Low Byte Bit 1 RW 0 ADCL0 ADC Data Register Low Byte Bit 0 RW 0 [ICE50:SIMULATOR:JTAGICEmkII:STK500:STK500_2:AVRISPmkII:AVRDragon] 0x05 0x0F 0x0F 0x0F 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x0F 0x0F 0x0F 0x15 0x14 0x14 0x000010FF 0x00000000 0x00000000 0x00000000 0x00000FFF 0x0001FFFF 0x0000FFFF 0x0000FFFF 0x0000FFFF 0x0000FFFF 0x000010FF 0x0000FFFF 0x00000FFF 0x00000000 0x00000000 0x00000000 0x0023FFFF 0x00000FFF 0x000000FF 0x0000FFFF 0x00000000 0x00000000 0x00000000 0x00000FFF 0x0001FFFF 0x0000FFFF 0x0000FFFF 0x0000FFFF 0x0000FFFF 0x0000FFFF 0x0000FFFF 0x00000FFF 0x00000000 0x00000000 0x00000000 0x0023FFFF 0x00000FFF 0x000000FF 0x000010FF 0x00000000 0x00000000 0x00000000 0x00000FFF 0x0001FFFF 0x0000FFFF 0x0000FFFF 0x0000FFFF 0x0000FFFF 0x0000FFFF 0x0000FFFF 0x00000FFF 0x00000000 0x00000000 0x00000000 0x0023FFFF 0x00000FFF 0x0000FFFF 0xF9 0xff 0xE1 0xff 0x6f 0xc7 ATmega128.bin 0x02 0x00 1000000 40000000 7 2 ; INTOSC = 1, INTRC=2;EXTCLK=4 1 ;NOTUSE = 1, EXTERNAL = 4, INTERNAL = 2 1 0 0x00 0x01 0x00000600 0x00000600 Boot Size 512 Words, 4 pages, $FE00-$FFFF, Boot reset $FE00 0x00000600 0x00000400 Boot Size 1024 Words, 8 pages, $FC00-$FFFF, Boot reset $FC00 0x00000600 0x00000200 Boot Size 2048 Words, 16 pages, $F800-$FFFF, Boot reset $F800 0x00000600 0x00000000 Boot Size 4096 Words, 32 pages, $F000-$FFFF, Boot reset $F000 0x00000031 0x00000000 258 CK, 4 ms 0x00000031 0x00000010 258 CK, 64 ms 0x00000031 0x00000020 1K CK 0x00000031 0x00000030 1K CK, 4 ms 0x00000031 0x00000001 1K CK, 64 ms 0x00000031 0x00000011 16K CK 0x00000031 0x00000021 16K CK, 4 ms 0x00000031 0x00000031 16K CK, 64 ms 0x00000030 0x00000000 6 CK 0x00000030 0x00000010 6 CK,4 ms 0x00000030 0x00000020 6 CK, 64 ms 0x00000030 0x00000000 6 CK 0x00000030 0x00000010 6 CK 0x00000030 0x00000020 6 CK, 64 ms 0x0000103f 0x0000002b 0x0000103f 0x00001021 1.0 0x0000103f 0x00001022 2.0 0x0000103f 0x00001023 4.0 0x0000103f 0x00001024 8.0 0x0000103f 0x00001020 0x00000100 0x00000100 Application reset, address $0 0x00000100 0x00000000 Boot loader reset 0x0c000000 0x0c000000 No restrictions for SPM or (E)LPM 0x0c000000 0x08000000 No write to the Application section 0x0c000000 0x00000000 No write to Application section, No read from the Application section 0x0c000000 0x04000000 No read from the Application section 0x30000000 0x30000000 No restrictions for SPM or (E)LPM 0x30000000 0x20000000 No write to the Boot Loader section 0x30000000 0x00000000 No write to Boot Loader section, No read from the Boot Loader section 0x30000000 0x10000000 No read from the Boot Loader section 0x00010000 0x00000000 Watchdog always ON 0x00010000 0x00010000 Watchdog disabled 0x000000C0 0x000000C0 BOD disabled 0x000000C0 0x00000080 BOD enabled, 2.7 V 0x000000C0 0x00000000 BOD enabled, 4.0 V AVRSimCoreV2.SimCoreV2 AVRSimMemory8bit.SimMemory8bit AVRSimInterrupt.SimInterrupt 0x2c 0 26 AVRSimIOPort.SimIOPort N AVRSimIOPort.SimIOPort N AVRSimIOPort.SimIOPort N AVRSimIOPort.SimIOPort N AVRSimIOPort.SimIOPort N AVRSimIOPort.SimIOPort N AVRSimIOPort.SimIOPort N AVRSimIOExtInterrupt.SimIOExtInterrupt 0x02 0x39 0x01 0x38 0x01 0x10 0x01 0x4a 0x03 AVRSimIOExtInterrupt.SimIOExtInterrupt 0x04 0x39 0x02 0x38 0x02 0x10 0x02 0x4a 0x0c AVRSimIOExtInterrupt.SimIOExtInterrupt 0x06 0x39 0x04 0x38 0x04 0x10 0x04 0x4a 0x30 AVRSimIOExtInterrupt.SimIOExtInterrupt 0x08 0x39 0x08 0x38 0x08 0x10 0x08 0x4a 0xc0 AVRSimIOExtInterrupt.SimIOExtInterrupt 0x0a 0x39 0x10 0x38 0x10 0x01 0x10 0x3a 0x03 AVRSimIOExtInterrupt.SimIOExtInterrupt 0x0c 0x39 0x20 0x38 0x20 0x01 0x20 0x3a 0x0c AVRSimIOExtInterrupt.SimIOExtInterrupt 0x0e 0x39 0x40 0x38 0x40 0x01 0x40 0x3a 0x30 AVRSimIOExtInterrupt.SimIOExtInterrupt 0x10 0x39 0x80 0x38 0x80 0x01 0x80 0x3a 0xc0 AvrMasterTimer.MasterTimer 0x1E 0x20 PORTB 4 1:8:32:64:128:256:1024 AvrMasterTimer.MasterTimer 0x16 0x18 0x1A 0x30 0x1C 0x10 0x10 0x18 0x20 0x18 0x40 0x18 0x80 TIFR/OCF1A TIFR/OCF1B ETIFR/OCF1C 1:8:64:256:1024 0x20 0x01 AvrMasterTimer.MasterTimer 0x12 0x14 PORTB 7 0x10 0x80 1:8:64:256:1024 AvrMasterTimer.MasterTimer 0x32 0x34 0x36 0x38 0x3A 0x01 0x40 0x03 0x80 ETIFR 0x03 0x08 0x03 0x10 0x03 0x20 ETIFR/OCF3A ETIFR/OCF3B ETIFR/OCF3C 1:8:64:256:1024 AVRSimIOSPM.SimIOSPM 0x44 AVRSimIOSpi.SimIOSpi 0x22 0x16 0x02 0x16 0x08 0x16 0x04 0x16 0x17 0x01 AVRSimIOUsart.SimIOUsart 0x24 0x28 0x26 0x01 0x02 0x01 0x01 AVRSimIOUsart.SimIOUsart 0x3C 0x40 0x3E 0x10 0x08 0x10 0x04 AVRSimAC.SimIOAC 0x2E AVRSimADC.SimADC 0x2A AvrSimTWI.SimTWI 0x42 AvrMasterTimer.MasterTimer 0 16384:32768:65536:131072:262144:524288:1048576:2097152 0xFF 0xff 0xFF 0xFF 0x0970203F JTAG 0xFF,0x6F,0xFF,0xFF,0xFB,0xFF,0xFF,0xFF 0x8C,0x26,0xB6,0xFD,0xFB,0xFF,0xBF,0xFE 0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00 0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00 0x3E,0xB5,0x1F,0x37,0xFF,0x1F,0x21,0x2F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 0x36,0xB5,0x0F,0x27,0xFF,0x1F,0x21,0x27,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 0x22 0x68 0x3B 256 8 0xFE00 0xFE00 0xFC00 0xF800 0xF000 0x9D 0x20000 0x0000,32 0x0020,64 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x3e 0x3d 0x00 0x00 0x00 0x01 0x00 0x01 1,0,0,0,0,0,0,0 0x3c 0xB2 1 1 1 0xFF 0xFF 0xFF 0 2001002532030x53112000x21128100x400x4C0x200xFF0x000x0464200xC00x000xA00xFF0xFF25625644440x0E 0x1E 0x0F 0x1F 0x2E 0x3E 0x2F 0x3F 0x4E 0x5E 0x4F 0x5F 0x6E 0x7E 0x6F 0x7F 0x66 0x76 0x67 0x77 0x6A 0x7A 0x6B 0x7B 0xBE 0xFD 0x00 0x01 0x00 0x00 0x00 0x00100060000151501050x0125625650x072562560505