[CORE:INTERRUPT_VECTOR:LOCKBIT:POWER:PROGVOLT:PROGRAMMING:PACKAGE:MEMORY:ADMIN:FUSE:IO_MODULE:ICE_SETTINGS]V3AVRSimCore32.SimCoreV3[][][]32$00$1B$1A$1D$1C$1F$1E57$000External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet. $002External Interrupt Request 0$004External Interrupt Request 1$006External Interrupt Request 2$008External Interrupt Request 3$00AExternal Interrupt Request 4$00CExternal Interrupt Request 5$00EExternal Interrupt Request 6$010External Interrupt Request 7$012Pin Change Interrupt Request 0$014Pin Change Interrupt Request 1$016Pin Change Interrupt Request 2$018Watchdog Time-out Interrupt$01ATimer/Counter2 Compare Match A$01CTimer/Counter2 Compare Match B$01ETimer/Counter2 Overflow$020Timer/Counter1 Capture Event$022Timer/Counter1 Compare Match A$024Timer/Counter1 Compare Match B$026Timer/Counter1 Compare Match C$028Timer/Counter1 Overflow$02ATimer/Counter0 Compare Match A$02CTimer/Counter0 Compare Match B$02ETimer/Counter0 Overflow$030SPI Serial Transfer Complete$032USART0, Rx Complete$034USART0 Data register Empty$036USART0, Tx Complete$038Analog Comparator$03AADC Conversion Complete$03CEEPROM Ready$03ETimer/Counter3 Capture Event$040Timer/Counter3 Compare Match A$042Timer/Counter3 Compare Match B$044Timer/Counter3 Compare Match C$046Timer/Counter3 Overflow$048USART1, Rx Complete$04AUSART1 Data register Empty$04CUSART1, Tx Complete$04E2-wire Serial Interface$050Store Program Memory Read$052Timer/Counter4 Capture Event$054Timer/Counter4 Compare Match A$056Timer/Counter4 Compare Match B$058Timer/Counter4 Compare Match C$05ATimer/Counter4 Overflow$05CTimer/Counter5 Capture Event$05ETimer/Counter5 Compare Match A$060Timer/Counter5 Compare Match B$062Timer/Counter5 Compare Match C$064Timer/Counter5 Overflow$066USART2, Rx Complete$068USART2 Data register Empty$06AUSART2, Tx Complete$06CUSART3, Rx Complete$06EUSART3 Data register Empty$070USART3, Tx Complete[LB1 = 1 : LB2 = 1] No memory lock features enabled. [LB1 = 0 : LB2 = 1] Further programming of Flash and EEPROM is enabled. [LB1 = 0 : LB2 = 0] Same as previous, but verify is also disabled6110x030x03Mode 1: No memory lock features enabled0x030x02Mode 2: Further programming disabled0x030x00Mode 3: Further programming and verification disabled0x0C0x0CApplication Protection Mode 1: No lock on SPM and LPM in Application Section0x0C0x08Application Protection Mode 2: SPM prohibited in Application Section0x0C0x00Application Protection Mode 3: LPM and SPM prohibited in Application Section0x0C0x04Application Protection Mode 4: LPM prohibited in Application Section0x300x30Boot Loader Protection Mode 1: No lock on SPM and LPM in Boot Loader Section0x300x20Boot Loader Protection Mode 2: SPM prohibited in Boot Loader Section0x300x00Boot Loader Protection Mode 3: LPM and SPM prohibited in Boot Loader Section0x300x10Boot Loader Protection Mode 4: LPM prohibited in Boot Loader SectionLB1Lock bitLB2Lock bitBLB01Boot Lock bitBLB02Boot Lock bitBLB11Boot lock bitBLB12Boot lock bit4MHz25C5.0mA2.2mA<3uA2.76.04.55.50xff,0xdf0xff,0xdf1,0x40,0x40,WARNING! These fuse settings will disable the JTAG interface!1,0x20,0x20,WARNING! These fuse settings will disable the ISP interface!1,0x40,0x40,WARNING! These fuse settings will disable the JTAG interface!1,0x20,0x20,WARNING! These fuse settings will disable the ISP interface!1,0x40,0x40,WARNING! These fuse settings will disable the JTAG interface!1,0x20,0x20,WARNING! These fuse settings will disable the ISP interface!0x00,8.0 MHz2568[TQFP]100[OC0B][PG5][RXD:PCINT8][PE0][TXD0][PE1][XCK:AIN0][PE2][OC3A:AIN1][PE3][OC3B:INT4][PE4][OC3C:INT5][PE5[T3:INT6][PE6][CLKO:ICP3:INT7][PE7][VCC][GND][RXD2][PH0][TXD2][PH1][XCK2][PH2][OC4A][PH3][OC4B][PH4][OC4C][PH5[OC2B][PH6]['SS:PCINT0][PB0][SCK:PCINT1][PB1][MOSI:PCINT2][PB2][MISO:PCINT3][PB3][OC0A:PCINT4][PB4][OC1A:PCINT5][PB5[OC1B:PCINT6][PB6][OC0A:OC1C:PCINT7][PB7][T4][PH7][TOSC2][PG3][TOSC1][PG4]['RESET][VCC][GND][XTAL2][XTAL1][ICP4][PL0][ICP5][PL1][T5][PL2][OC5A][PL3][OC5B][PL4][OC5C][PL5[PL6][PL7][SCL:INT0][PD0][SDA:INT1][PD1][RXD1:INT2][PD2][TXD1:INT3][PD3][ICP1][PD4][XCK1][PD5][T1][PD6][T0][PD7]['WR][PG0]['RD][PG1][A8][PC0][A9][PC1][A10][PC2][A11][PC3][A12][PC4][A13][PC5][A14][PC6][A15][PC7][VCC][GND][RXD3:PCINT9][PJ0][TXD3:PCINT10][PJ1][XCK3:PCINT11][PJ2][PCINT12][PJ3][PCINT13][PJ4][PCINT14][PJ5[PCINT15][PJ6][ALE][PG2][AD7][PA7][AD6][PA6][AD5][PA5][AD4][PA4][AD3][PA3][AD2][PA2][AD1][PA1][AD0][PA0][PJ7][VCC][GND][ADC15:PCINT23][PK7][ADC14:PCINT22][PK6][ADC13:PCINT21][PK5][ADC12:PCINT20][PK4][ADC11:PCINT19][PK3][ADC10:PCINT18][PK2][ADC9:PCINT17][PK1][ADC8:PCINT16][PK0][ADC7:TDI][PF7][ADC6:TDO][PF6][ADC5:TMS][PF5[ADC4:TCK][PF4][ADC3][PF3][ADC2][PF2][ADC1][PF1][ADC0][PF0][AREF][AGND][AVCC]AVRSimMemory8bit.SimMemory8bit13107240968192$20065536$2200$00$3F$60$1FF$20$1FFNA$1360x010x020x040x080x100x200x400x80NA$1350x010x020x040x08NA$1340x010x020x040x080x100x200x400x80NA$1320x010x020x040x080x100x200x400x80NA$1310x010x020x040x080x100x200x400x80NA$1300x010x020x040x080x100x200x400x80NA$12D0x010x020x040x080x100x200x400x80NA$12C0x010x020x040x080x100x200x400x80NA$12B0x010x020x040x080x100x200x400x80NA$12A0x010x020x040x080x100x200x400x80NA$1290x010x020x040x080x100x200x400x80NA$1280x010x020x040x080x100x200x400x80NA$1270x010x020x040x080x100x200x400x80NA$1260x010x020x040x080x100x200x400x80NA$1250x010x020x040x080x100x200x400x80NA$1240x010x020x040x080x100x200x400x80NA$1220x200x400x80NA$1210x010x020x040x080x100x400x80NA$1200x010x020x040x080x100x200x400x80NA$10B0x010x020x040x080x100x200x400x80NA$10A0x010x020x040x080x100x200x400x80NA$1090x010x020x040x080x100x200x400x80NA$1080x010x020x040x080x100x200x400x80NA$1070x010x020x040x080x100x200x400x80NA$1060x010x020x040x080x100x200x400x80NA$1050x010x020x040x080x100x200x400x80NA$1040x010x020x040x080x100x200x400x80NA$1030x010x020x040x080x100x200x400x80NA$1020x010x020x040x080x100x200x400x80NA$1010x010x020x040x080x100x200x400x80NA$1000x010x020x040x080x100x200x400x80NA$D60x010x020x040x080x100x200x400x80NA$D50x010x020x040x08NA$D40x010x020x040x080x100x200x400x80NA$D20x010x020x040x080x100x200x400x80NA$D10x010x020x040x080x100x200x400x80NA$D00x010x020x040x080x100x200x400x80NA$CE0x010x020x040x080x100x200x400x80NA$CD0x010x020x040x08NA$CC0x010x020x040x080x100x200x400x80NA$CA0x010x020x040x080x100x200x400x80NA$C90x010x020x040x080x100x200x400x80NA$C80x010x020x040x080x100x200x400x80NA$C60x010x020x040x080x100x200x400x80NA$C50x010x020x040x08NA$C40x010x020x040x080x100x200x400x80NA$C20x010x020x040x080x100x200x400x80NA$C10x010x020x040x080x100x200x400x80NA$C00x010x020x040x080x100x200x400x80NA$BD0x020x040x080x100x200x400x80NA$BC0x010x040x080x100x200x400x80NA$BB0x010x020x040x080x100x200x400x80NA$BA0x010x020x040x080x100x200x400x80NA$B90x010x020x080x100x200x400x80NA$B80x010x020x040x080x100x200x400x80NA$B60x010x020x040x080x100x200x40NA$B40x010x020x040x080x100x200x400x80NA$B30x010x020x040x080x100x200x400x80NA$B20x010x020x040x080x100x200x400x80NA$B10x010x020x040x080x400x80NA$B00x010x020x100x200x400x80NA$AD0x010x020x040x080x100x200x400x80NA$AC0x010x020x040x080x100x200x400x80NA$AB0x010x020x040x080x100x200x400x80NA$AA0x010x020x040x080x100x200x400x80NA$A90x010x020x040x080x100x200x400x80NA$A80x010x020x040x080x100x200x400x80NA$A70x010x020x040x080x100x200x400x80NA$A60x010x020x040x080x100x200x400x80NA$A50x010x020x040x080x100x200x400x80NA$A40x010x020x040x080x100x200x400x80NA$A20x200x400x80NA$A10x010x020x040x080x100x400x80NA$A00x010x020x040x080x100x200x400x80NA$9D0x010x020x040x080x100x200x400x80NA$9C0x010x020x040x080x100x200x400x80NA$9B0x010x020x040x080x100x200x400x80NA$9A0x010x020x040x080x100x200x400x80NA$990x010x020x040x080x100x200x400x80NA$980x010x020x040x080x100x200x400x80NA$970x010x020x040x080x100x200x400x80NA$960x010x020x040x080x100x200x400x80NA$950x010x020x040x080x100x200x400x80NA$940x010x020x040x080x100x200x400x80NA$920x200x400x80NA$910x010x020x040x080x100x400x80NA$900x010x020x040x080x100x200x400x80NA$8D0x010x020x040x080x100x200x400x80NA$8C0x010x020x040x080x100x200x400x80NA$8B0x010x020x040x080x100x200x400x80NA$8A0x010x020x040x080x100x200x400x80NA$890x010x020x040x080x100x200x400x80NA$880x010x020x040x080x100x200x400x80NA$870x010x020x040x080x100x200x400x80NA$860x010x020x040x080x100x200x400x80NA$850x010x020x040x080x100x200x400x80NA$840x010x020x040x080x100x200x400x80NA$820x200x400x80NA$810x010x020x040x080x100x400x80NA$800x010x020x040x080x100x200x400x80NA$7F0x010x02NA$7E0x010x020x040x080x100x200x400x80NA$7D0x010x020x040x080x100x200x400x80NA$7C0x010x020x040x080x100x200x400x80NA$7B0x400x010x020x040x08NA$7A0x010x020x040x080x100x200x400x80NA$790x010x020x040x080x100x200x400x80NA$780x010x020x040x080x100x200x400x80NA$750x010x020x040x80NA$740x010x020x040x080x100x200x400x80NA$730x010x020x040x080x20NA$720x010x020x040x080x20NA$710x010x020x040x080x20NA$700x010x020x04NA$6F0x010x020x040x080x20NA$6E0x010x020x04NA$6D0x010x020x040x080x100x200x400x80NA$6C0x010x020x040x080x100x200x400x80NA$6B0x010x020x040x080x100x200x400x80NA$6A0x010x020x040x080x100x200x400x80NA$690x010x020x040x080x100x200x400x80NA$680x010x020x04NA$660x010x020x040x080x100x200x400x80NA$650x010x020x040x080x100x20NA$640x010x020x040x080x200x400x80NA$610x010x020x040x080x80NA$600x010x020x040x080x100x200x400x80$3F$5F0x010x020x040x080x100x200x400x80$3E$5E0x210x010x020x040x080x100x200x400x80$3D$5D0xFF0x010x020x040x080x100x200x400x80$3C$5C0x01$3B$5B0x010x02$37$570x010x020x040x080x100x200x400x80$35$550x800x010x020x10$34$540x100x010x020x040x08$33$530x010x020x040x08$31$510x010x020x040x080x100x200x400x80$30$500x010x020x040x080x100x200x400x80$2E$4E0x010x020x040x080x100x200x400x80$2D$4D0x010x400x80$2C$4C0x010x020x040x080x100x200x400x80$2B$4B0x010x020x040x080x100x200x400x80$2A$4A0x010x020x040x080x100x200x400x80$28$480x010x020x040x080x100x200x400x80$27$470x010x020x040x080x100x200x400x80$26$460x010x020x040x080x100x200x400x80$25$450x010x020x040x080x400x80$24$440x010x020x100x200x400x80$23$430x010x800x02$22$420x010x020x040x08$21$410x010x020x040x080x100x200x400x80$20$400x010x020x040x080x100x200x400x80$1F$3F0x010x020x040x080x100x20$1E$3E0x010x020x040x080x100x200x400x80$1D$3D0x010x020x040x080x100x200x400x80$1C$3C0x010x020x040x080x100x200x400x80$1B$3B0x010x020x04$1A$3A0x010x020x040x080x20$19$390x010x020x040x080x20$18$380x010x020x040x080x20$17$370x010x020x04$16$360x010x020x040x080x20$15$350x010x020x04$14$340x010x020x040x080x100x20$13$330x010x020x040x080x100x20$12$320x010x020x040x080x100x20$11$310x010x020x040x080x100x200x400x80$10$300x010x020x040x080x100x200x400x80$0F$2F0x010x020x040x080x100x200x400x80$0E$2E0x010x020x040x080x100x200x400x80$0D$2D0x010x020x040x080x100x200x400x80$0C$2C0x010x020x040x080x100x200x400x80$0B$2B0x010x020x040x080x100x200x400x80$0A$2A0x010x020x040x080x100x200x400x80$09$290x010x020x040x080x100x200x400x80$08$280x010x020x040x080x100x200x400x80$07$270x010x020x040x080x100x200x400x80$06$260x010x020x040x080x100x200x400x80$05$250x010x020x040x080x100x200x400x80$04$240x010x020x040x080x100x200x400x80$03$230x010x020x040x080x100x200x400x80$02$220x010x020x040x080x100x200x400x80$01$210x010x020x040x080x100x200x400x80$00$200x010x020x040x080x100x200x400x80$F000$FFFF$0000$EFFF1285124$0000$FE00$FE0010248$0000$FC00$FC00204816$0000$F800$F800409632$0000$F000$F000ATmega128016MHZ1RELEASED$1E$97$03[LOW:HIGH:EXTENDED]8CLKDIV8Divide clock by 80CKOUTClock output1SUT1Select start-up time0SUT0Select start-up time0CKSEL3Select Clock Source0CKSEL2Select Clock Source0CKSEL1Select Clock Source1CKSEL0Select Clock Source0570x800x00Divide clock by 8 internally; [CKDIV8=0]0x400x00Clock output on PORTE7; [CKOUT=0]0x3F0x00Ext. Clock; Start-up time: 6 CK + 0 ms; [CKSEL=0000 SUT=00]0x3F0x10Ext. Clock; Start-up time: 6 CK + 4.1 ms; [CKSEL=0000 SUT=01]0x3F0x20Ext. Clock; Start-up time: 6 CK + 65 ms; [CKSEL=0000 SUT=10]0x3F0x02Int. RC Osc.; Start-up time: 6 CK + 0 ms; [CKSEL=0010 SUT=00]0x3F0x12Int. RC Osc.; Start-up time: 6 CK + 4.1 ms; [CKSEL=0010 SUT=01]0x3F0x22Int. RC Osc.; Start-up time: 6 CK + 65 ms; [CKSEL=0010 SUT=10]0x3F0x03Int. 128kHz RC Osc.; Start-up time: 6 CK + 0 ms; [CKSEL=0011 SUT=00]0x3F0x13Int. 128kHz RC Osc.; Start-up time: 6 CK + 4 ms; [CKSEL=0011 SUT=01]0x3F0x23Int. 128kHz RC Osc.; Start-up time: 6 CK + 64 ms; [CKSEL=0011 SUT=10]0x3F0x04Ext. Low-Freq. Crystal; Start-up time: 1K CK + 0 ms; [CKSEL=0100 SUT=00]0x3F0x14Ext. Low-Freq. Crystal; Start-up time: 1K CK + 4.1 ms; [CKSEL=0100 SUT=01]0x3F0x24Ext. Low-Freq. Crystal; Start-up time: 1K CK + 65 ms; [CKSEL=0100 SUT=10]0x3F0x05Ext. Low-Freq. Crystal; Start-up time: 32K CK + 0 ms; [CKSEL=0101 SUT=00]0x3F0x15Ext. Low-Freq. Crystal; Start-up time: 32K CK + 4.1 ms; [CKSEL=0101 SUT=01]0x3F0x25Ext. Low-Freq. Crystal; Start-up time: 32K CK + 65 ms; [CKSEL=0101 SUT=10]0x3F0x06Full Swing Oscillator; Start-up time: 258 CK + 4.1 ms; Ceramic res.; fast rising power; [CKSEL=0110 SUT=00]0x3F0x16Full Swing Oscillator; Start-up time: 258 CK + 65 ms; Ceramic res.; slowly rising power; [CKSEL=0110 SUT=01]0x3F0x26Full Swing Oscillator; Start-up time: 1K CK + 0 ms; Ceramic res.; BOD enable; [CKSEL=0110 SUT=10]0x3F0x36Full Swing Oscillator; Start-up time: 1K CK + 4.1 ms; Ceramic res.; fast rising power; [CKSEL=0110 SUT=11]0x3F0x07Full Swing Oscillator; Start-up time: 1K CK + 65 ms; Ceramic res.; slowly rising power; [CKSEL=0111 SUT=00]0x3F0x17Full Swing Oscillator; Start-up time: 16K CK + 0 ms; Crystal Osc.; BOD enabled; [CKSEL=0111 SUT=01]0x3F0x27Full Swing Oscillator; Start-up time: 16K CK + 4.1 ms; Crystal Osc.; fast rising power; [CKSEL=0111 SUT=10]0x3F0x37Full Swing Oscillator; Start-up time: 16K CK + 65 ms; Crystal Osc.; slowly rising power; [CKSEL=0111 SUT=11]0x3F0x08Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 258 CK + 4.1 ms; [CKSEL=1000 SUT=00]0x3F0x18Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 258 CK + 65 ms; [CKSEL=1000 SUT=01]0x3F0x28Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 1K CK + 0 ms; [CKSEL=1000 SUT=10]0x3F0x38Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 1K CK + 4.1 ms; [CKSEL=1000 SUT=11]0x3F0x09Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 1K CK + 65 ms; [CKSEL=1001 SUT=00]0x3F0x19Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 16K CK + 0 ms; [CKSEL=1001 SUT=01]0x3F0x29Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 16K CK + 4.1 ms; [CKSEL=1001 SUT=10]0x3F0x39Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 16K CK + 65 ms; [CKSEL=1001 SUT=11]0x3F0x0AExt. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 258 CK + 4.1 ms; [CKSEL=1010 SUT=00]0x3F0x1AExt. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 258 CK + 65 ms; [CKSEL=1010 SUT=01]0x3F0x2AExt. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 1K CK + 0 ms; [CKSEL=1010 SUT=10]0x3F0x3AExt. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 1K CK + 4.1 ms; [CKSEL=1010 SUT=11]0x3F0x0BExt. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 1K CK + 65 ms; [CKSEL=1011 SUT=00]0x3F0x1BExt. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 16K CK + 0 ms; [CKSEL=1011 SUT=01]0x3F0x2BExt. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 16K CK + 4.1 ms; [CKSEL=1011 SUT=10]0x3F0x3BExt. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 16K CK + 65 ms; [CKSEL=1011 SUT=11]0x3F0x0CExt. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 258 CK + 4.1 ms; [CKSEL=1100 SUT=00]0x3F0x1CExt. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 258 CK + 65 ms; [CKSEL=1100 SUT=01]0x3F0x2CExt. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 1K CK + 0 ms; [CKSEL=1100 SUT=10]0x3F0x3CExt. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 1K CK + 4.1 ms; [CKSEL=1100 SUT=11]0x3F0x0DExt. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 1K CK + 65 ms; [CKSEL=1101 SUT=00]0x3F0x1DExt. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 16K CK + 0 ms; [CKSEL=1101 SUT=01]0x3F0x2DExt. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 16K CK + 4.1 ms; [CKSEL=1101 SUT=10]0x3F0x3DExt. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 16K CK + 65 ms; [CKSEL=1101 SUT=11]0x3F0x0EExt. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 258 CK + 4.1 ms; [CKSEL=1110 SUT=00]0x3F0x1EExt. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 258 CK + 65 ms; [CKSEL=1110 SUT=01]0x3F0x2EExt. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 1K CK + 0 ms; [CKSEL=1110 SUT=10]0x3F0x3EExt. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 1K CK + 4.1 ms; [CKSEL=1110 SUT=11]0x3F0x0FExt. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 1K CK + 65 ms; [CKSEL=1111 SUT=00]0x3F0x1FExt. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 16K CK + 0 ms; [CKSEL=1111 SUT=01]0x3F0x2FExt. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 16K CK + 4.1 ms; [CKSEL=1111 SUT=10]0x3F0x3FExt. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 16K CK + 65 ms; [CKSEL=1111 SUT=11]8OCDENEnable OCD1JTAGENEnable JTAG0SPIENEnable Serial programming and Data Downloading0WDTONWatchdog timer always on1EESAVEEEPROM memory is preserved through chip erase1BOOTSZ1Select Boot Size0BOOTSZ0Select Boot Size0BOOTRSTSelect Reset Vector1100x800x00On-Chip Debug Enabled; [OCDEN=0]0x400x00JTAG Interface Enabled; [JTAGEN=0]0x200x00Serial program downloading (SPI) enabled; [SPIEN=0]0x100x00Watchdog timer always on; [WDTON=0]0x080x00Preserve EEPROM memory through the Chip Erase cycle; [EESAVE=0]0x060x06Boot Flash section size=512 words Boot start address=$FE00; [BOOTSZ=11]0x060x04Boot Flash section size=1024 words Boot start address=$FC00; [BOOTSZ=10]0x060x02Boot Flash section size=2048 words Boot start address=$F800; [BOOTSZ=01]0x060x00Boot Flash section size=4096 words Boot start address=$F000; [BOOTSZ=00] ; default value0x010x00Boot Reset vector Enabled (default address=$0000); [BOOTRST=0]3BODLEVEL2Brown-out Detector trigger level1BODLEVEL1Brown-out Detector trigger level1BODLEVEL0Brown-out Detector trigger level140x070x07Brown-out detection disabled; [BODLEVEL=111]0x070x06Brown-out detection level at VCC=1.8 V; [BODLEVEL=110]0x070x05Brown-out detection level at VCC=2.7 V; [BODLEVEL=101]0x070x04Brown-out detection level at VCC=4.3 V; [BODLEVEL=100][ANALOG_COMPARATOR:USART0:TWI:SPI:PORTA:PORTB:PORTC:PORTD:PORTE:PORTF:PORTG:PORTH:PORTJ:PORTK:PORTL:TIMER_COUNTER_0:TIMER_COUNTER_2:WATCHDOG:USART1:EEPROM:TIMER_COUNTER_5:TIMER_COUNTER_4:TIMER_COUNTER_3:TIMER_COUNTER_1:JTAG:EXTERNAL_INTERRUPT:CPU:AD_CONVERTER:BOOT_LOAD:USART2:USART3][ADCSRB:ACSR:DIDR1]io_analo.bmpAlgComp_01ADCSRBADC Control and Status Register BNA$7Bio_flag.bmpYACMEAnalog Comparator Multiplexer EnableWhen this bit is written logic one and the ADC is switched off (ADEN in ADCSR is zero), the ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed description of this bit, see “Analog Comparator Multiplexed Input” on page 186.RW0ACSRAnalog Comparator Control And Status Register$30$50io_analo.bmpYACDAnalog Comparator DisableWhen this bit is written logic one, the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.RW0ACBGAnalog Comparator Bandgap SelectWhen this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. See “Internal Voltage Reference” on page 42.RW0ACOAnalog Compare OutputThe output of the analog comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1-2 clock cycles.RNAACIAnalog Comparator Interrupt FlagThis bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hard-ware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.RW0ACIEAnalog Comparator Interrupt EnableWhen the ACIE bit is written logic one and the I-bit in the Status Register is set, the analog comparator interrupt is acti-vated. When written logic zero, the interrupt is disabled.RW0ACICAnalog Comparator Input Capture EnableWhen written logic one, this bit enables the Input Capture function in Timer/Counter1 to be triggered by the analog comparator. The comparator output is in this case directly connected to the Input Capture front-end logic, making the comparator utilize the noise canceler and edge select features of the Timer/Counter1 Input Capture interrupt. When written logic zero, no connection between the analog comparator and the Input Capture function exists. To make the comparator trigger the Timer/Counter1 Input Capture interrupt, the TICIE1 bit in the Timer Interrupt Mask Register (TIMSK) must be setRW0ACIS1Analog Comparator Interrupt Mode Select bit 1These bits determine which comparator events that trigger the Analog Comparator interrupt.RW0ACIS0Analog Comparator Interrupt Mode Select bit 0These bits determine which comparator events that trigger the Analog Comparator interrupt.RW0DIDR1Digital Input Disable Register 1NA$7Fio_analo.bmpYAIN1DAIN1 Digital Input DisableWhen this bit is written logic one,the digital input buffer on the AIN1/0 pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. RW0AIN0DAIN0 Digital Input DisableWhen this bit is written logic one,the digital input buffer on the AIN1/0 pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. RW0[UDR0:UCSR0A:UCSR0B:UCSR0C:UBRR0H:UBRR0L]
[UBRR0H:UBRR0L]
io_com.bmpThe Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. The main features are: • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • High Resolution Baud Rate Generator • Supports Serial Frames with 5, 6, 7, 8 or 9 Data Bits and 1 or 2 Stop Bits • Odd or Even Parity Generation and Parity Check Supported by Hardware • Data OverRun Detection • Framing Error Detection • Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter • Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete • Multi-processor Communication Mode • Double Speed Asynchronous CommunicaUDR0USART I/O Data RegisterThe UDR0 register is actually two physically separate registers sharing the same I/O address. When writing to the register, the USART Transmit Data register is written. When reading from UDR0, the USART Receive Data register is read.NA$C6io_com.bmpNUDR0-7USART I/O Data Register bit 7RW0UDR0-6USART I/O Data Register bit 6RW0UDR0-5USART I/O Data Register bit 5RW0UDR0-4USART I/O Data Register bit 4RW0UDR0-3USART I/O Data Register bit 3RW0UDR0-2USART I/O Data Register bit 2RW0UDR0-1USART I/O Data Register bit 1RW0UDR0-0USART I/O Data Register bit 0RW0UCSR0AUSART Control and Status Register ANA$C0io_flag.bmpYRXC0USART Receive CompleteThis bit is set (one) when a received character is transferred from the Receiver Shift register to UDR0. The bit is set regard-less of any detected framing errors. When the RXCIE bit in UCR is set, the USART Receive Complete interrupt will be executed when RXC is set(one). RXC is cleared by reading UDR0. When interrupt-driven data reception is used, the USART Receive Complete Interrupt routine must read UDRin order to clear RXC, otherwise a new interrupt will occur once the interrupt routine terminates.R0TXC0USART Transmitt CompleteThis bit is set (one) when the entire character (including the stop bit) in the Transmit Shift register has been shifted out and no new data has been written to UDR0. This flag is especially useful in half-duplex communications interfaces, where a transmitting application must enter receive mode and free the communications bus immediately after completing the transmission. When the TXCIE bit in UCR is set, setting of TXC causes the USART Transmit Complete interrupt to be executed. TXC is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the TXC bit is cleared (zero) by writing a logical one to the bRW0UDRE0USART Data Register EmptyThis bit is set (one) when a character written to UDRis transferred to the Transmit shift register. Setting of this bit indicates that the transmitter is ready to receive a new character for transmission. When the UDR0IE bit in UCR is set, the USART Transmit Complete interrupt to be executed as long as UDR0E is set. UDR0E is cleared by writing UDR0. When interrupt-driven data transmittal is used, the USART Data Register Empty Interrupt routine must write UDRin order to clear UDR0E, otherwise a new interrupt will occur once the interrupt routine terminates. UDR0E is set (one) during reset to indicate that the transmitter is reR1FE0Framing ErrorThis bit is set if a Framing Error condition is detected, i.e. when the stop bit of an incoming character is zero. The FE bit is cleared when the stop bit of received data is one.R0DOR0Data overRunThis bit is set if an Overrun condition is detected, i.e. when a character already present in the UDRregister is not read before the next character has been shifted into the Receiver Shift register. The OR bit is buffered, which means that it will be set once the valid data still in UDR0E is read. The OR bit is cleared (zero) when data is received and transferred to UDR0. R0UPE0Parity ErrorThis bit is set if the next character in the receive buffer had a Parity Error when received and the parity checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer (UDR0) is read. Always set this bit to zero when writing to UCSR0A.R0U2X0Double the USART transmission speedThis bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation. Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous communication.RW0MPCM0Multi-processor Communication ModeThis bit enables the Multi-processor Communication Mode. When the MPCM bit is written to one, all the incoming frames received by the USART receiver that do not contain address information will be ignored. The transmitter is unaffected by the MPCM setting. For more detailed information see “Multi-processor Communication Mode” on page 152.RW0UCSR0BUSART Control and Status Register BNA$C1io_flag.bmpYRXCIE0RX Complete Interrupt EnableWriting this bit to one enables interrupt on the RXC flag. A USART Receive Complete interrupt will be generated only if the RXCIE bit is written to one, the global interrupt flag in SREG is written to one and the RXC bit in UCSR0A is set.RW0TXCIE0TX Complete Interrupt EnableWriting this bit to one enables interrupt on the TXC flag. A USART Transmit Complete interrupt will be generated only if the TXCIE bit is written to one, the global interrupt flag in SREG is written to one and the TXC bit in UCSR0A is set.RW0UDRIE0USART Data register Empty Interrupt EnableWriting this bit to one enables interrupt on the UDR0E flag. A Data Register Empty interrupt will be generated only if the UDR0IE bit is written to one, the global interrupt flag in SREG is written to one and the UDR0E bit in UCSR0A is set.RW1RXEN0Receiver EnableWriting this bit to one enables the USART receiver. The receiver will override normal port operation for the RxD pin when enabled. Disabling the receiver will flush the receive buffer invalidating the FE, DOR and PE flags.RW0TXEN0Transmitter EnableWriting this bit to one enables the USART transmitter. The transmitter will override normal port operation for the TxD pin when enabled. The disabling of the transmitter (writing TXEN to zero) will not become effective until ongoing and pending transmissions are completed, i.e. when the transmit shift register and transmit buffer register does not contain data to be transmitted. When disabled, the transmitter will no longer override the TxD port.RW0UCSZ02Character SizeThe UCSZ2 bits combined with the UCSZ1:0 bit in UCSR0C sets the number of data bits (character size) in a frame the receiver and transmitter use.RW0RXB80Receive Data Bit 8RXB8 is the 9th data bit of the received character when operating with serial frames with 9 data bits. Must be read before reading the low bits from UDR0.R0TXB80Transmit Data Bit 8TXB8 is the 9th data bit in the character to be transmitted when operating with serial frames with 9 data bits. Must be writ-ten before writing the low bits to UDR0.W0UCSR0CUSART Control and Status Register CNA$C2io_flag.bmpYUMSEL01UMSEL1USART Mode SelectRW0UMSEL00UMSEL0USART Mode SelectRW0UPM01Parity Mode Bit 1This bit enable and set type of parity generation and check. If enabled, the transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value for the incoming data and compare it to the UPM0 setting. If a mismatch is detected, the PE flag in UCSR0A will be set.RW0UPM00Parity Mode Bit 0This bit enable and set type of parity generation and check. If enabled, the transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value for the incoming data and compare it to the UPM0 setting. If a mismatch is detected, the PE flag in UCSR0A will be set.RW0USBS0Stop Bit Select0: 1-bit. 1: 2-bit.RW0UCSZ01UDORD0Character SizeCharacter Size: 0 0 0 = 5-bit. 0 0 1 = 6-bit. 0 1 0 = 7 bit. 0 1 1 = 8-bit. 1 1 1 = 9 bit.RW0UCSZ00UCPHA0Character SizeCharacter Size: 0 0 0 = 5-bit. 0 0 1 = 6-bit. 0 1 0 = 7 bit. 0 1 1 = 8-bit. 1 1 1 = 9 bit.RW1UCPOL0Clock PolarityThis bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOL bit sets the relationship between data output change and data input sample, and the synchronous clock (XCK).RW0UBRR0HUSART Baud Rate Register High ByteThis is a 12-bit register which contains the USART baud rate. The UBRR0H contains the 4 most significant bits, and the UBRR0L contains the 8 least significant bits of the USART baud rate. Ongoing transmissions by the transmitter and receiver will be corrupted if the baud rate is changed. Writing UBRR0L will trigger an immediate update of the baud rate prescaler.NA$C5io_com.bmpNUBRR11USART Baud Rate Register bit 11RW0UBRR10USART Baud Rate Register bit 10RW0UBRR9USART Baud Rate Register bit 9RW0UBRR8USART Baud Rate Register bit 8RW0UBRR0LUSART Baud Rate Register Low ByteThis is a 12-bit register which contains the USART baud rate. The UBRR0H contains the 4 most significant bits, and the UBRR0L contains the 8 least significant bits of the USART baud rate. Ongoing transmissions by the transmitter and receiver will be corrupted if the baud rate is changed. Writing UBRR0L will trigger an immediate update of the baud rate prescaler.NA$C4io_com.bmpNUBRR7USART Baud Rate Register bit 7RW0UBRR6USART Baud Rate Register bit 6RW0UBRR5USART Baud Rate Register bit 5RW0UBRR4USART Baud Rate Register bit 4RW0UBRR3USART Baud Rate Register bit 3RW0UBRR2USART Baud Rate Register bit 2RW0UBRR1USART Baud Rate Register bit 1RW0UBRR0USART Baud Rate Register bit 0RW0[TWAMR:TWBR:TWCR:TWSR:TWDR:TWAR]io_com.bmpTWI: Simple yet powerful and flexible communications interface, only two bus lines needed. Both master and slave operation supported. Device can operate as transmitter or receiver. 7-bit address space allows up to 128 different slave addresses. Multi-master arbitration support Up to 400 kHz data transfer speed Slew-rate limited output drivers Noise suppression circuitry rejects spikes on bus lines Fully programmable slave address with general call support Address recognition causes wake-up when AVR is in sleep mode The Two-Wire Serial Interface (TWI) is ideally suited to typical microcontroller applications. The TWI protocol allows the systems designer to interconnect up to 128 different devices using only two bidirectional bus lines, one for clock (SCL) andone for data (SDA). The only external hardware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines. All devices connected to the bus have individual addresses, and mechanisms for resolving bus contention are inherent in the TWI prTWAMRTWI (Slave) Address Mask RegisterThe TWAMR can be loaded with a 7-bit Salve Address mask. Each of the bits in TWAMR can mask (disable) the corresponding address bits in the TWI Address Register (TWAR). If the mask bit is set to one then the address match logic ingnores the compare between the incomming address bit and the corresponding bit in TWAR.NA$BDio_com.bmpYTWAM6TWAMR6RW0TWAM5TWAMR5RW0TWAM4TWAMR4RW0TWAM3TWAMR3RW0TWAM2TWAMR2RW0TWAM1TWAMR1RW0TWAM0TWAMR0RW0TWBRTWI Bit Rate registerTWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency divider which generates the SCL clock frequency in the master modes. See “Bit Rate Generator Unit” on page 165 for calculating bit rates.NA$B8io_com.bmpNTWBR7RW0TWBR6RW0TWBR5RW0TWBR4RW0TWBR3RW0TWBR2RW0TWBR1RW0TWBR0RW0TWCRTWI Control RegisterThe TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate a master access by applying a START condition to the bus, to generate a receiver acknowledge, to generate a stop condition, and to control halting of the bus while the data to be written to the bus are written to the TWDR. It also indicates a write collision if data is attempted written to TWDR while the register is inaccessible.NA$BCio_flag.bmpYTWINTTWI Interrupt FlagThis bit is set by hardware when the TWI has finished its current job and expects application software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the TWI interrupt vector. While the TWINT flag is set, the SCL low period is stretched. The TWINT flag must be cleared by software by writing a logic one to it. Note that this flag is not automatically cleared by hardware when executing the interrupt routine. Also note that clearing this flag starts the operation of the TWI, so all accesses to the TWI Address Register (TWAR), TWI Status Register (TWSR), and TWI Data Register (TWDR) must be complete before clearing this flagRW0TWEATWI Enable Acknowledge BitThe TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is written to one, the ACK pulse is gener-ated on the TWI bus if the following conditions are met: 1. The device’s own slave address has been received. 2. A general call has been received, while the TWGCE bit in the TWAR is set. 3. A data byte has been received in master receiver or slave receiver mode. By writing the TWEA bit to zero, the device can be virtually disconnected from the 2-wire Serial Bus temporarily. Address recognition can then be resumed by writing the TWEA bit to one againRW0TWSTATWI Start Condition BitThe application writes the TWSTA bit to one when it desires to become a master on the 2-wire Serial Bus. The TWI hard-ware checks if the bus is available, and generates a START condition on the bus if it is free. However, if the bus is not free, the TWI waits until a STOP condition is detected, and then generates a new START condition to claim the bus Master sta-tus. TWSTA is cleared by the TWI hardware when the START condition has been transmitted.RW0TWSTOTWI Stop Condition BitWriting the TWSTO bit to one in master mode will generate a STOP condition on the 2-wire Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit is cleared automatically. In slave mode, setting the TWSTO bit can be used to recover from an error condition. This will not generate a STOP condition, but the TWI returns to a well-defined unaddressed slave mode and releases the SCL and SDA lines to a high impedance state.RW0TWWCTWI Write Collition FlagThe TWWC bit is set when attempting to write to the TWI Data Register - TWDR when TWINT is low. This flag is cleared by writing the TWDR register when TWINT is high.RW0TWENTWI Enable BitThe TWEN bit enables TWI operation and activates the TWI interface. When TWEN is written to one, the TWI takes control over the I/O pins connected to the SCL and SDA pins, enabling the slew-rate limiters and spike filters. If this bit is written to zero, the TWI is switched off and all TWI transmissions are terminated, regardless of any ongoing operation.RW0TWIETWI Interrupt EnableWhen this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request will be activated for as long as the TWINT flag is high.RW0TWSRTWI Status RegisterNA$B9io_flag.bmpYTWS7TWI StatusBits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient cRW0TWS6TWI StatusBits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient coRW0TWS5TWI StatusBits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient cRW0TWS4TWI StatusBits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient coRW0TWS3TWI StatusBits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient coRW0TWPS1TWI PrescalerBits 1..0: These bits can be read and written, and control the bit rate prescaler. See “Bit Rate Generator Unit” on page 165 for calculating bit rates.RW0TWPS0TWI PrescalerBits 1..0: These bits can be read and written, and control the bit rate prescaler. See “Bit Rate Generator Unit” on page 165 for calculating bit rates.RW0TWDRTWI Data registerIn transmit mode, TWDR contains the next byte to be transmitted. In receive mode, the TWDR contains the last byte received. It is writable while the TWI is not in the process of shifting a byte. This occurs when the TWI interrupt flag (TWINT) is set by hardware. Note that the data register cannot be initialized by the user before the first interrupt occurs. The data in TWDR remains stable as long as TWINT is set. While data is shifted out, data on the bus is simultaneously shifted in. TWDR always contains the last byte present on the bus, except after a wake up from a sleep mode by the TWI interrupt. In this case, the contents of TWDR is undefined. In the case of a lost bus arbitration, no data is lost in the transi-tion from Master to Slave. Handling of the ACK bit is controlled automatically by the TWI logic, the CPU cannot access the ACK bit directlNA$BBio_com.bmpNTWD7TWI Data Register Bit 7RW1TWD6TWI Data Register Bit 6RW1TWD5TWI Data Register Bit 5RW1TWD4TWI Data Register Bit 4RW1TWD3TWI Data Register Bit 3RW1TWD2TWI Data Register Bit 2RW1TWD1TWI Data Register Bit 1RW1TWD0TWI Data Register Bit 0RW1TWARTWI (Slave) Address registerThe TWAR should be loaded with the 7-bit slave address (in the seven most significant bits of TWAR) to which the TWI will respond when programmed as a slave transmitter or receiver, and not needed in the master modes. In multimaster sys-tems, TWAR must be set in masters which can be addressed as slaves by other masters. The LSB of TWAR is used to enable recognition of the general call address ($00). There is an associated address compar-ator that looks for the slave address (or general call address if enabled) in the received serial address. If a match is found, an interrupt request is generaNA$BAio_com.bmpYTWA6TWI (Slave) Address register Bit 6RW0TWA5TWI (Slave) Address register Bit 5RW0TWA4TWI (Slave) Address register Bit 4RW0TWA3TWI (Slave) Address register Bit 3RW0TWA2TWI (Slave) Address register Bit 2RW0TWA1TWI (Slave) Address register Bit 1RW0TWA0TWI (Slave) Address register Bit 0RW0TWGCETWI General Call Recognition Enable BitRW0[SPDR:SPSR:SPCR]io_com.bmpThe Serial Peripheral Interface(SPI) allows high-speed synchronous data transfer between the AT90S4414/8515 and peripheral devices or between several AVR devices. The AT90S4414/8515 SPI features include the following: • Full-duplex, 3-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Four Programmable Bit Rates • End of Transmission Interrupt Flag • Write Collision Flag Protection • Wakeup from Idle Mode (Slave Mode Only)SPCRSPI Control Register$2C$4Cio_flag.bmpYSPIESPI Interrupt EnableThis bit causes the SPI interrupt to be executed if SPIF bit in the SPSR register is set and the global interrupts are enabled.RW0SPESPI EnableWhen the SPE bit is set (one), the SPI is enabled. This bit must be set to enable any SPI operations.RW0DORDData OrderWhen the DORD bit is set (one), the LSB of the data word is transmitted first. When the DORD bit is cleared (zero), the MSB of the data word is transmitted first.RW0MSTRMaster/Slave SelectThis bit selects Master SPI mode when set (one), and Slave SPI mode when cleared (zero). If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI master mode.RW0CPOLClock polarityWhen this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is low when idle. Refer to Figure 36 and Figure 37 for additional information.RW0CPHAClock PhaseRefer to Figure 36 or Figure 37 for the functionality of this bit.RW0SPR1SPI Clock Rate Select 1These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave.RW0SPR0SPI Clock Rate Select 0These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave.RW0SPSRSPI Status Register$2D$4Dio_flag.bmpYSPIFSPI Interrupt FlagWhen a serial transfer is complete, the SPIF bit is set (one) and an interrupt is generated if SPIE in SPCR is set (one) and global interrupts are enabled. If SS is an input and is driven low when the SPI is in master mode, this will also set the SPIF flag. SPIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the SPI status register when SPIF is set (one), then accessing the SPI Data Register (SPDR).R0WCOLWrite Collision FlagThe WCOL bit is set if the SPI data register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Register when WCOL is set (one), and then accessing the SPI Data Register.R0SPI2XDouble SPI Speed BitWhen this bit is written logic one the SPI speed (SCK Frequency)will be doubled when the SPI is in master mode .This means that the minimum SCK period will be 2 CPU clock periods.When the SPI is configured as Slave,the SPI is only guaranteed to work at f osc /4orlower. The SPI interface on the ATmega162 is also used for program memory and EEPROM downloading or uploading. RW0SPDRSPI Data RegisterThe SPI Data Register is a read/write register used for data transfer between the register file and the SPI Shift register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read.$2E$4Eio_com.bmpNSPDR7SPI Data Register bit 7RWXSPDR6SPI Data Register bit 6RWXSPDR5SPI Data Register bit 5RWXSPDR4SPI Data Register bit 4RWXSPDR3SPI Data Register bit 3RWXSPDR2SPI Data Register bit 2RWXSPDR1SPI Data Register bit 1R0SPDR0SPI Data Register bit 0R0[PORTA:DDRA:PINA]io_port.bmpAVRSimIOPort.SimIOPortPORTAPort A Data Register$02$22io_port.bmpNPORTA7Port A Data Register bit 7RW0PORTA6Port A Data Register bit 6RW0PORTA5Port A Data Register bit 5RW0PORTA4Port A Data Register bit 4RW0PORTA3Port A Data Register bit 3RW0PORTA2Port A Data Register bit 2RW0PORTA1Port A Data Register bit 1RW0PORTA0Port A Data Register bit 0RW0DDRAPort A Data Direction Register$01$21io_flag.bmpNDDA7Data Direction Register, Port A, bit 7RW0DDA6Data Direction Register, Port A, bit 6RW0DDA5Data Direction Register, Port A, bit 5RW0DDA4Data Direction Register, Port A, bit 4RW0DDA3Data Direction Register, Port A, bit 3RW0DDA2Data Direction Register, Port A, bit 2RW0DDA1Data Direction Register, Port A, bit 1RW0DDA0Data Direction Register, Port A, bit 0RW0PINAPort A Input PinsThe Port A Input Pins address - PINA - is not a register, and this address enables access to the physical value on each Port A pin. When reading PORTA the Port A Data Latch is read, and when reading PINA, the logical values present on the pins are read.$00$20io_port.bmpNPINA7Input Pins, Port A bit 7RWHi-ZPINA6Input Pins, Port A bit 6RWHi-ZPINA5Input Pins, Port A bit 5RWHi-ZPINA4Input Pins, Port A bit 4RWHi-ZPINA3Input Pins, Port A bit 3RWHi-ZPINA2Input Pins, Port A bit 2RWHi-ZPINA1Input Pins, Port A bit 1RWHi-ZPINA0Input Pins, Port A bit 0RWHi-Z[PORTB:DDRB:PINB]io_port.bmpAVRSimIOPort.SimIOPortPORTBPort B Data Register$05$25io_port.bmpNPORTB7Port B Data Register bit 7RW0PORTB6Port B Data Register bit 6RW0PORTB5Port B Data Register bit 5RW0PORTB4Port B Data Register bit 4RW0PORTB3Port B Data Register bit 3RW0PORTB2Port B Data Register bit 2RW0PORTB1Port B Data Register bit 1RW0PORTB0Port B Data Register bit 0RW0DDRBPort B Data Direction Register$04$24io_flag.bmpNDDB7Port B Data Direction Register bit 7RW0DDB6Port B Data Direction Register bit 6RW0DDB5Port B Data Direction Register bit 5RW0DDB4Port B Data Direction Register bit 4RW0DDB3Port B Data Direction Register bit 3RW0DDB2Port B Data Direction Register bit 2RW0DDB1Port B Data Direction Register bit 1RW0DDB0Port B Data Direction Register bit 0RW0PINBPort B Input PinsThe Port B Input Pins address - PINB - is not a register, and this address enables access to the physical value on each Port B pin. When reading PORTB, the Port B Data Latch is read, and when reading PINB, the logical values present on the pins are read.$03$23io_port.bmpNPINB7Port B Input Pins bit 7R0PINB6Port B Input Pins bit 6R0PINB5Port B Input Pins bit 5R0PINB4Port B Input Pins bit 4R0PINB3Port B Input Pins bit 3R0PINB2Port B Input Pins bit 2R0PINB1Port B Input Pins bit 1R0PINB0Port B Input Pins bit 0R0[PORTC:DDRC:PINC]io_port.bmpAVRSimIOPort.SimIOPortPORTCPort C Data Register$08$28io_port.bmpNPORTC7Port C Data Register bit 7RW0PORTC6Port C Data Register bit 6RW0PORTC5Port C Data Register bit 5RW0PORTC4Port C Data Register bit 4RW0PORTC3Port C Data Register bit 3RW0PORTC2Port C Data Register bit 2RW0PORTC1Port C Data Register bit 1RW0PORTC0Port C Data Register bit 0RW0DDRCPort C Data Direction Register$07$27io_flag.bmpNDDC7Port C Data Direction Register bit 7RW0DDC6Port C Data Direction Register bit 6RW0DDC5Port C Data Direction Register bit 5RW0DDC4Port C Data Direction Register bit 4RW0DDC3Port C Data Direction Register bit 3RW0DDC2Port C Data Direction Register bit 2RW0DDC1Port C Data Direction Register bit 1RW0DDC0Port C Data Direction Register bit 0RW0PINCPort C Input PinsThe Port C Input Pins address - PINC - is not a register, and this address enables access to the physical value on each Port C pin. When reading PORTC, the Port C Data Latch is read, and when reading PINC, the logical values present on the pins are read.$06$26io_port.bmpNPINC7Port C Input Pins bit 7R0PINC6Port C Input Pins bit 6R0PINC5Port C Input Pins bit 5R0PINC4Port C Input Pins bit 4R0PINC3Port C Input Pins bit 3R0PINC2Port C Input Pins bit 2R0PINC1Port C Input Pins bit 1R0PINC0Port C Input Pins bit 0R0[PORTD:DDRD:PIND]io_port.bmpAVRSimIOPort.SimIOPortPORTDPort D Data Register$0B$2Bio_port.bmpNPORTD7Port D Data Register bit 7RW0PORTD6Port D Data Register bit 6RW0PORTD5Port D Data Register bit 5RW0PORTD4Port D Data Register bit 4RW0PORTD3Port D Data Register bit 3RW0PORTD2Port D Data Register bit 2RW0PORTD1Port D Data Register bit 1RW0PORTD0Port D Data Register bit 0RW0DDRDPort D Data Direction Register$0A$2Aio_flag.bmpNDDD7Port D Data Direction Register bit 7RW0DDD6Port D Data Direction Register bit 6RW0DDD5Port D Data Direction Register bit 5RW0DDD4Port D Data Direction Register bit 4RW0DDD3Port D Data Direction Register bit 3RW0DDD2Port D Data Direction Register bit 2RW0DDD1Port D Data Direction Register bit 1RW0DDD0Port D Data Direction Register bit 0RW0PINDPort D Input PinsThe Port D Input Pins address - PIND - is not a register, and this address enables access to the physical value on each Port D pin. When reading PORTD, the Port D Data Latch is read, and when reading PIND, the logical values present on the pins are read.$09$29io_port.bmpNPIND7Port D Input Pins bit 7R0PIND6Port D Input Pins bit 6R0PIND5Port D Input Pins bit 5R0PIND4Port D Input Pins bit 4R0PIND3Port D Input Pins bit 3R0PIND2Port D Input Pins bit 2R0PIND1Port D Input Pins bit 1R0PIND0Port D Input Pins bit 0R0[PORTE:DDRE:PINE]io_port.bmpAVRSimIOPort.SimIOPortPORTEData Register, Port E$0E$2Eio_port.bmpNPORTE7RW0PORTE6RW0PORTE5RW0PORTE4RW0PORTE3RW0PORTE2RW0PORTE1RW0PORTE0RW0DDREData Direction Register, Port E$0D$2Dio_flag.bmpNDDE7RW0DDE6RW0DDE5RW0DDE4RW0DDE3RW0DDE2RW0DDE1RW0DDE0RW0PINEInput Pins, Port E$0C$2Cio_port.bmpNPINE7R0PINE6R0PINE5R0PINE4R0PINE3R0PINE2R0PINE1R0PINE0R0[PORTF:DDRF:PINF]io_port.bmpAVRSimIOPort.SimIOPortPORTFData Register, Port F$11$31io_port.bmpNPORTF7RW0PORTF6RW0PORTF5RW0PORTF4RW0PORTF3RW0PORTF2RW0PORTF1RW0PORTF0RW0DDRFData Direction Register, Port F$10$30io_flag.bmpNDDF7RW0DDF6RW0DDF5RW0DDF4RW0DDF3RW0DDF2RW0DDF1RW0DDF0RW0PINFInput Pins, Port F$0F$2Fio_port.bmpNPINF7R0PINF6R0PINF5R0PINF4R0PINF3R0PINF2R0PINF1R0PINF0R0[PORTG:DDRG:PING]io_port.bmpAVRSimIOPort.SimIOPortPORTGData Register, Port G$14$34io_port.bmpNPORTG5RW0PORTG4RW0PORTG3RW0PORTG2RW0PORTG1RW0PORTG0RW0DDRGData Direction Register, Port G$13$33io_flag.bmpNDDG5RW0DDG4RW0DDG3RW0DDG2RW0DDG1RW0DDG0RW0PINGInput Pins, Port G$12$32io_port.bmpNPING5R0PING4R0PING3R0PING2R0PING1R0PING0R0[PORTH:DDRH:PINH]io_port.bmpAVRSimIOPort.SimIOPortPORTHPORT H Data RegisterNA$102io_port.bmpNPORTH7PORT H Data Register bit 7RW0PORTH6PORT H Data Register bit 6RW0PORTH5PORT H Data Register bit 5RW0PORTH4PORT H Data Register bit 4RW0PORTH3PORT H Data Register bit 3RW0PORTH2PORT H Data Register bit 2RW0PORTH1PORT H Data Register bit 1RW0PORTH0PORT H Data Register bit 0RW0DDRHPORT H Data Direction RegisterNA$101io_flag.bmpNDDH7PORT H Data Direction Register bit 7RW0DDH6PORT H Data Direction Register bit 6RW0DDH5PORT H Data Direction Register bit 5RW0DDH4PORT H Data Direction Register bit 4RW0DDH3PORT H Data Direction Register bit 3RW0DDH2PORT H Data Direction Register bit 2RW0DDH1PORT H Data Direction Register bit 1RW0DDH0PORT H Data Direction Register bit 0RW0PINHPORT H Input PinsThe PORT H Input Pins address - PINH - is not a register, and this address enables access to the physical value on each PORT H pin. When reading PORTH, the PORT H Data Latch is read, and when reading PINH, the logical values present on the pins are read.NA$100io_port.bmpNPINH7PORT H Input Pins bit 7R0PINH6PORT H Input Pins bit 6R0PINH5PORT H Input Pins bit 5R0PINH4PORT H Input Pins bit 4R0PINH3PORT H Input Pins bit 3R0PINH2PORT H Input Pins bit 2R0PINH1PORT H Input Pins bit 1R0PINH0PORT H Input Pins bit 0R0[PORTJ:DDRJ:PINJ]io_port.bmpAVRSimIOPort.SimIOPortPORTJPORT J Data RegisterNA$105io_port.bmpNPORTJ7PORT J Data Register bit 7RW0PORTJ6PORT J Data Register bit 6RW0PORTJ5PORT J Data Register bit 5RW0PORTJ4PORT J Data Register bit 4RW0PORTJ3PORT J Data Register bit 3RW0PORTJ2PORT J Data Register bit 2RW0PORTJ1PORT J Data Register bit 1RW0PORTJ0PORT J Data Register bit 0RW0DDRJPORT J Data Direction RegisterNA$104io_flag.bmpNDDJ7PORT J Data Direction Register bit 7RW0DDJ6PORT J Data Direction Register bit 6RW0DDJ5PORT J Data Direction Register bit 5RW0DDJ4PORT J Data Direction Register bit 4RW0DDJ3PORT J Data Direction Register bit 3RW0DDJ2PORT J Data Direction Register bit 2RW0DDJ1PORT J Data Direction Register bit 1RW0DDJ0PORT J Data Direction Register bit 0RW0PINJPORT J Input PinsThe PORT J Input Pins address - PINJ - is not a register, and this address enables access to the physical value on each PORT J pin. When reading PORTJ, the PORT J Data Latch is read, and when reading PINJ, the logical values present on the pins are read.NA$103io_port.bmpNPINJ7PORT J Input Pins bit 7R0PINJ6PORT J Input Pins bit 6R0PINJ5PORT J Input Pins bit 5R0PINJ4PORT J Input Pins bit 4R0PINJ3PORT J Input Pins bit 3R0PINJ2PORT J Input Pins bit 2R0PINJ1PORT J Input Pins bit 1R0PINJ0PORT J Input Pins bit 0R0[PORTK:DDRK:PINK]io_port.bmpAVRSimIOPort.SimIOPortPORTKPORT K Data RegisterNA$108io_port.bmpNPORTK7PORT K Data Register bit 7RW0PORTK6PORT K Data Register bit 6RW0PORTK5PORT K Data Register bit 5RW0PORTK4PORT K Data Register bit 4RW0PORTK3PORT K Data Register bit 3RW0PORTK2PORT K Data Register bit 2RW0PORTK1PORT K Data Register bit 1RW0PORTK0PORT K Data Register bit 0RW0DDRKPORT K Data Direction RegisterNA$107io_flag.bmpNDDK7PORT K Data Direction Register bit 7RW0DDK6PORT K Data Direction Register bit 6RW0DDK5PORT K Data Direction Register bit 5RW0DDK4PORT K Data Direction Register bit 4RW0DDK3PORT K Data Direction Register bit 3RW0DDK2PORT K Data Direction Register bit 2RW0DDK1PORT K Data Direction Register bit 1RW0DDK0PORT K Data Direction Register bit 0RW0PINKPORT K Input PinsThe PORT K Input Pins address - PINK - is not a register, and this address enables access to the physical value on each PORT K pin. When reading PORTK, the PORT K Data Latch is read, and when reading PINK, the logical values present on the pins are read.NA$106io_port.bmpNPINK7PORT K Input Pins bit 7R0PINK6PORT K Input Pins bit 6R0PINK5PORT K Input Pins bit 5R0PINK4PORT K Input Pins bit 4R0PINK3PORT K Input Pins bit 3R0PINK2PORT K Input Pins bit 2R0PINK1PORT K Input Pins bit 1R0PINK0PORT K Input Pins bit 0R0[PORTL:DDRL:PINL]io_port.bmpAVRSimIOPort.SimIOPortPORTLPORT L Data RegisterNA$10Bio_port.bmpNPORTL7PORT L Data Register bit 7RW0PORTL6PORT L Data Register bit 6RW0PORTL5PORT L Data Register bit 5RW0PORTL4PORT L Data Register bit 4RW0PORTL3PORT L Data Register bit 3RW0PORTL2PORT L Data Register bit 2RW0PORTL1PORT L Data Register bit 1RW0PORTL0PORT L Data Register bit 0RW0DDRLPORT L Data Direction RegisterNA$10Aio_flag.bmpNDDL7PORT L Data Direction Register bit 7RW0DDL6PORT L Data Direction Register bit 6RW0DDL5PORT L Data Direction Register bit 5RW0DDL4PORT L Data Direction Register bit 4RW0DDL3PORT L Data Direction Register bit 3RW0DDL2PORT L Data Direction Register bit 2RW0DDL1PORT L Data Direction Register bit 1RW0DDL0PORT L Data Direction Register bit 0RW0PINLPORT L Input PinsThe PORT L Input Pins address - PINL - is not a register, and this address enables access to the physical value on each PORT L pin. When reading PORTL, the PORT L Data Latch is read, and when reading PINL, the logical values present on the pins are read.NA$109io_port.bmpNPINL7PORT L Input Pins bit 7R0PINL6PORT L Input Pins bit 6R0PINL5PORT L Input Pins bit 5R0PINL4PORT L Input Pins bit 4R0PINL3PORT L Input Pins bit 3R0PINL2PORT L Input Pins bit 2R0PINL1PORT L Input Pins bit 1R0PINL0PORT L Input Pins bit 0R0[TIMSK0:TIFR0:TCCR0A:TCCR0B:TCNT0:OCR0A:OCR0B:GTCCR]io_timer.bmpAt8pwm0_01OCR0BTimer/Counter0 Output Compare RegisterThe Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC0 pin.$28$48io_timer.bmpNOCR0B_7RW0OCR0B_6RW0OCR0B_5RW0OCR0B_4RW0OCR0B_3RW0OCR0B_2RW0OCR0B_1RW0OCR0B_0RW0OCR0ATimer/Counter0 Output Compare RegisterThe Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC0 pin.$27$47io_timer.bmpNOCROA_7RW0OCROA_6RW0OCROA_5RW0OCROA_4RW0OCROA_3RW0OCROA_2RW0OCROA_1RW0OCROA_0RW0TCNT0Timer/Counter0The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT0 register blocks (removes) the compare match on the following timer clock. Modifying the counter (TCNT0) while the counter is running, introduces a risk of missing a compare match between TCNT0 the OCR0 register.$26$46io_timer.bmpNTCNT0_7RW0TCNT0_6RW0TCNT0_5RW0TCNT0_4RW0TCNT0_3RW0TCNT0_2RW0TCNT0_1RW0TCNT0_0RW0TCCR0BTimer/Counter Control Register B$25$45io_flag.bmpYFOC0AForce Output Compare AW0FOC0BForce Output Compare BW0WGM02RW0CS02Clock SelectRW0CS01Clock SelectRW0CS00Clock SelectRW0TCCR0ATimer/Counter Control Register A$24$44io_flag.bmpYCOM0A1Compare Output Mode, Phase Correct PWM ModeRW0COM0A0Compare Output Mode, Phase Correct PWM ModeRW0COM0B1Compare Output Mode, Fast PWmW0COM0B0Compare Output Mode, Fast PWmRW0WGM01Waveform Generation ModeRW0WGM00Waveform Generation ModeRW0TIMSK0Timer/Counter0 Interrupt Mask RegisterNA$6Eio_flag.bmpYOCIE0BTimer/Counter0 Output Compare Match B Interrupt EnableRW0OCIE0ATimer/Counter0 Output Compare Match A Interrupt EnableRW0TOIE0Timer/Counter0 Overflow Interrupt EnableRW0TIFR0Timer/Counter0 Interrupt Flag register$15$35io_flag.bmpYOCF0BTimer/Counter0 Output Compare Flag 0BRW0OCF0ATimer/Counter0 Output Compare Flag 0ARW0TOV0Timer/Counter0 Overflow FlagRW0GTCCRGeneral Timer/Counter Control Register$23$43io_flag.bmpYTSMTimer/Counter Synchronization ModeWriting the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSR2 and PSR10 bits is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSR2 and PSR10 bits are cleared by hardware, and the Timer/Counters start counting simultaneouslRW0PSRSYNCPSR10Prescaler Reset Timer/Counter1 and Timer/Counter0When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers.RW0[TIMSK2:TIFR2:TCCR2A:TCCR2B:TCNT2:OCR2A:OCR2B:ASSR:GTCCR]io_timer.bmpAt8pwm2_07The 8-bit Timer/Counter2 can select clock source from CK, prescaled CK, or external crystal input TOSC1. It can also be stopped as described in the section “Timer/Counter2 Control Register - TCCR2”. The status flags (overflow and compare match) are found in the Timer/Counter Interrupt Flag Register - TIFR. Control signals are found in the Timer/Counter Control Register TCCR2. The interrupt enable/disable settings are found in “The Timer/Counter Interrupt Mask Register - TIMSK”. When Timer/Counter2 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. This module features a high resolution and a high accuracy usage with the lower prescaling opportunities. Similarly, the high prescaling opportunities make this unit useful for lower speed functions or exact timing functions with infrequent actions. Timer/Counter2 can also be used as an 8-bit Pulse Width Modulator. In this mode, Timer/Counter2 and the output compare register serve as a glitch-free, stand-alone PWM with centered pulsTIMSK2Timer/Counter Interrupt Mask registerNA$70io_flag.bmpYOCIE2BTimer/Counter2 Output Compare Match B Interrupt EnableWhen the OCIE2B bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match B interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter2 occurs, i.e., when the OCF2B bit is set in the Timer/Counter 2 Interrupt Flag Register – TIFR2.RW0OCIE2ATimer/Counter2 Output Compare Match A Interrupt EnableWhen the OCIE2A bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match A interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter2 occurs, i.e., when the OCF2A bit is set in the Timer/Counter 2 Interrupt Flag Register – TIFR2.RW0TOIE2TOIE2ATimer/Counter2 Overflow Interrupt EnableWhen the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is set in the Timer/Counter2 Interrupt Flag Register – TIFR2.RW0TIFR2Timer/Counter Interrupt Flag Register$17$37io_flag.bmpYOCF2BOutput Compare Flag 2BThe OCF2B bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2B – Output Compare Register2. OCF2B is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF2B is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2B (Timer/Counter2 Compare match Interrupt Enable), and OCF2B are set (one), the Timer/Counter2 Compare match Interrupt is executed.RW0OCF2AOutput Compare Flag 2AThe OCF2A bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2A – Output Compare Register2. OCF2A is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF2A is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2A (Timer/Counter2 Compare match Interrupt Enable), and OCF2A are set (one), the Timer/Counter2 Compare match Interrupt is executed.RW0TOV2Timer/Counter2 Overflow FlagThe TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE2A (Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter2 changes counting direction at 0x00.RW0TCCR2ATimer/Counter2 Control Register ANA$B0io_flag.bmpYCOM2A1Compare Output Mode bit 1The COM21 and COM20 control bits determine any output pin action following a compare match in Timer/Counter2. Output pin actions affect pin PD7(OC2). This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. (COM21:COM20) description: (0:0) = Timer/Counter disconnected from output pin OC2. (0:1) = Toggle the OC2 output line. (1:0) = Clear the OC2 output line (to zero). (1:1) = Set the OC2 output line (to one). Note: In PWM mode, these bits have a different functionRW0COM2A0Compare Output Mode bit 1The COM21 and COM20 control bits determine any output pin action following a compare match in Timer/Counter2. Output pin actions affect pin PD7(OC2). This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. (COM21:COM20) description: (0:0) = Timer/Counter disconnected from output pin OC2. (0:1) = Toggle the OC2 output line. (1:0) = Clear the OC2 output line (to zero). (1:1) = Set the OC2 output line (to one). Note: In PWM mode, these bits have a different functionRW0COM2B1Compare Output Mode bit 1The COM21 and COM20 control bits determine any output pin action following a compare match in Timer/Counter2. Output pin actions affect pin PD7(OC2). This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. (COM21:COM20) description: (0:0) = Timer/Counter disconnected from output pin OC2. (0:1) = Toggle the OC2 output line. (1:0) = Clear the OC2 output line (to zero). (1:1) = Set the OC2 output line (to one). Note: In PWM mode, these bits have a different functionRW0COM2B0Compare Output Mode bit 0The COM21 and COM20 control bits determine any output pin action following a compare match in Timer/Counter2. Output pin actions affect pin PD7(OC2). This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. (COM21:COM20) description: (0:0) = Timer/Counter disconnected from output pin OC2. (0:1) = Toggle the OC2 output line. (1:0) = Clear the OC2 output line (to zero). (1:1) = Set the OC2 output line (to one). Note: In PWM mode, these bits have a different functioRW0WGM21Waveform Genration ModeThese bits control the counting sequence of the counter,the source for hte maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter), Clear Timer on Compare match (CTC)mode,and two types of Pulse Width Modulation (PWM)modes. Please refer to the manual for more information.RW0WGM20Waveform Genration ModeThese bits control the counting sequence of the counter,the source for hte maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter), Clear Timer on Compare match (CTC)mode,and two types of Pulse Width Modulation (PWM)modes. Please refer to the manual for more information.RW0TCCR2BTimer/Counter2 Control Register BNA$B1io_flag.bmpYFOC2AForce Output Compare AWriting a logical one to this bit, forces a change in the compare match output pin PD7 (OC2) according to the values already set in COM21 and COM20. If the COM21 and COM20 bits are written in the same cycle as FOC2, the new settings will not take effect until next compare match or forced output compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM21 and COM20 happens as if a Compare Match had occurred, but no interrupt is generated, and the Timer/Counter will not be cleared even if CTC2 is set. The corresponding I/O pin must be set as an output pin for the FOC2 bit to have effect on the pin. The FOC2 bit will always be read as zero. Setting the FOC2 bit has no effect in PWM modeRW0FOC2BForce Output Compare BWriting a logical one to this bit, forces a change in the compare match output pin PD7 (OC2) according to the values already set in COM21 and COM20. If the COM21 and COM20 bits are written in the same cycle as FOC2, the new settings will not take effect until next compare match or forced output compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM21 and COM20 happens as if a Compare Match had occurred, but no interrupt is generated, and the Timer/Counter will not be cleared even if CTC2 is set. The corresponding I/O pin must be set as an output pin for the FOC2 bit to have effect on the pin. The FOC2 bit will always be read as zero. Setting the FOC2 bit has no effect in PWM modeRW0WGM22Waveform Generation ModeThese bits control the counting sequence of the counter,the source for hte maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter), Clear Timer on Compare match (CTC)mode,and two types of Pulse Width Modulation (PWM)modes. Please refer to the manual for more information.RW0CS22Clock Select bit 2The Clock Select bits 2,1, and 0 define the prescaling source of Timer/Counter2. (CS22:CS21:CS20) Description. (0:0:0) Timer/Counter2 is stopped. (0:0:1) PCK2. (0:1:0) PCK2/8. (0:1:1) PCK2/32. (1:0:0) PCK2/64. (1:0:1) PCK2/128. (1:1:0) PCK2/256. (1:1:1) PCK2/1024. The Stop condition provides a Timer Enable/Disable function. The prescaled modes are scaled directly from the PCK2 clock.RW0CS21Clock Select bit 1The Clock Select bits 2,1, and 0 define the prescaling source of Timer/Counter2. (CS22:CS21:CS20) Description. (0:0:0) Timer/Counter2 is stopped. (0:0:1) PCK2. (0:1:0) PCK2/8. (0:1:1) PCK2/32. (1:0:0) PCK2/64. (1:0:1) PCK2/128. (1:1:0) PCK2/256. (1:1:1) PCK2/1024. The Stop condition provides a Timer Enable/Disable function. The prescaled modes are scaled directly from the PCK2 clock.RW0CS20Clock Select bit 0The Clock Select bits 2,1, and 0 define the prescaling source of Timer/Counter2. (CS22:CS21:CS20) Description. (0:0:0) Timer/Counter2 is stopped. (0:0:1) PCK2. (0:1:0) PCK2/8. (0:1:1) PCK2/32. (1:0:0) PCK2/64. (1:0:1) PCK2/128. (1:1:0) PCK2/256. (1:1:1) PCK2/1024. The Stop condition provides a Timer Enable/Disable function. The prescaled modes are scaled directly from the PCK2 clock.RW0TCNT2Timer/Counter2This 8-bit register contains the value of Timer/Counter2. Timer/Counters2 is implemented as an up or up/down (in PWM mode) counter with read and write access. If the Timer/Counter2iswritten to and a clocksourceisselected,it continues counting in the timer clock cycle following the write operation.NA$B2io_timer.bmpNTCNT2-7Timer/Counter 2 bit 7RW0TCNT2-6Timer/Counter 2 bit 6RW0TCNT2-5Timer/Counter 2 bit 5RW0TCNT2-4Timer/Counter 2 bit 4RW0TCNT2-3Timer/Counter 2 bit 3RW0TCNT2-2Timer/Counter 2 bit 2RW0TCNT2-1Timer/Counter 2 bit 1RW0TCNT2-0Timer/Counter 2 bit 0RW0OCR2BTimer/Counter2 Output Compare Register BThe output compare register is an 8-bit read/write register. The Timer/Counter Output Compare Register contains the data to be continuously compared with Timer/Counter2. Actions on compare matches are specified in TCCR2. A compare match does only occur if Timer/Counter2 counts to the OCR2 value. A software write that sets TCNT2 and OCR2 to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Timer/Counter2 in PWM Mode When PWM mode is selected, the Timer/Counter2 either wraps (overflows) when it reaches $FF or it acts as an up/down counter. If the up/down mode is selected, the Timer/Counter2 and the Output Compare Register - OCR2 form an 8-bit, free-running, glitch-free, and phase correct PWM with outputs on the PD7(OC2) pin. If the overflow mode is selected, the Timer/Counter2 and the Output Compare Register - OCR2 form an 8-bit, free-running, and glitch-free PWM, operating with twice the speed of the up/down counting mode. PWM Modes (Up/Down and Overflow). The two different PWM modes are selected by the CTC2 bit in the Timer/Counter Control Register - TCCR2. If CTC2 is cleared and PWM mode is selected, the Timer/Counter acts as an up/down counter, counting up from $00 to $FF, where it turns and counts down again to zero before the cycle is repeated. When the counter value matches the con-tents of the Output Compare Register, the PD7(OC2) pin is set or cleared according to the settings of the COM21/COM20 bits in the Timer/Counter Control Register TCCR2. If CTC2 is set and PWM mode is selected, the Timer/Counters will wrap and start counting from $00 after reaching $FF. The PD7(OC2) pin will be set or cleared according to the settings of COM21/COM20 on a Timer/Counter overflow or when the counter value matches the contents of the Output Compare Register. Note that in PWM mode, the value to be written to the Output Compare Register is first transferred to a temporary location, and then latched into OCR2 when the Timer/Counter reaches $FF. This prevents the occurrence of odd-length PWM pulses (glitches) in the event of an unsynchronized OCR2 write. (CTC2:COM21:COM20) Effect on Compare Pin Frequency: (0:0:0) = Not connected. (0:0:1) = Not connected. (0:1:0) = Cleared on compare match, up-counting. Set on compare match, down-counting (non-inverted PWM). f TCK0/2 /510. (0:1:1) = Cleared on compare match, down-counting. Set on compare match, up-counting (inverted PWM). f TCK0/2 /510. (1:0:0) = Not connected. (1:0:1) = Not connected. (1:1:0) = Cleared on compare match, set on overflow. f TCK0/2 /256. (1:1:1) = Set on compare match, cleared on overflow. f TCK0/NA$B4io_timer.bmpNOCR2-7Timer/Counter2 Output Compare Register Bit 7RW0OCR2-6Timer/Counter2 Output Compare Register Bit 6RW0OCR2-5Timer/Counter2 Output Compare Register Bit 5RW0OCR2-4Timer/Counter2 Output Compare Register Bit 4RW0OCR2-3Timer/Counter2 Output Compare Register Bit 3RW0OCR2-2Timer/Counter2 Output Compare Register Bit 2RW0OCR2-1Timer/Counter2 Output Compare Register Bit 1RW0OCR2-0Timer/Counter2 Output Compare Register Bit 0RW0OCR2ATimer/Counter2 Output Compare Register AThe output compare register is an 8-bit read/write register. The Timer/Counter Output Compare Register contains the data to be continuously compared with Timer/Counter2. Actions on compare matches are specified in TCCR2. A compare match does only occur if Timer/Counter2 counts to the OCR2 value. A software write that sets TCNT2 and OCR2 to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Timer/Counter2 in PWM Mode When PWM mode is selected, the Timer/Counter2 either wraps (overflows) when it reaches $FF or it acts as an up/down counter. If the up/down mode is selected, the Timer/Counter2 and the Output Compare Register - OCR2 form an 8-bit, free-running, glitch-free, and phase correct PWM with outputs on the PD7(OC2) pin. If the overflow mode is selected, the Timer/Counter2 and the Output Compare Register - OCR2 form an 8-bit, free-running, and glitch-free PWM, operating with twice the speed of the up/down counting mode. PWM Modes (Up/Down and Overflow). The two different PWM modes are selected by the CTC2 bit in the Timer/Counter Control Register - TCCR2. If CTC2 is cleared and PWM mode is selected, the Timer/Counter acts as an up/down counter, counting up from $00 to $FF, where it turns and counts down again to zero before the cycle is repeated. When the counter value matches the con-tents of the Output Compare Register, the PD7(OC2) pin is set or cleared according to the settings of the COM21/COM20 bits in the Timer/Counter Control Register TCCR2. If CTC2 is set and PWM mode is selected, the Timer/Counters will wrap and start counting from $00 after reaching $FF. The PD7(OC2) pin will be set or cleared according to the settings of COM21/COM20 on a Timer/Counter overflow or when the counter value matches the contents of the Output Compare Register. Note that in PWM mode, the value to be written to the Output Compare Register is first transferred to a temporary location, and then latched into OCR2 when the Timer/Counter reaches $FF. This prevents the occurrence of odd-length PWM pulses (glitches) in the event of an unsynchronized OCR2 write. (CTC2:COM21:COM20) Effect on Compare Pin Frequency: (0:0:0) = Not connected. (0:0:1) = Not connected. (0:1:0) = Cleared on compare match, up-counting. Set on compare match, down-counting (non-inverted PWM). f TCK0/2 /510. (0:1:1) = Cleared on compare match, down-counting. Set on compare match, up-counting (inverted PWM). f TCK0/2 /510. (1:0:0) = Not connected. (1:0:1) = Not connected. (1:1:0) = Cleared on compare match, set on overflow. f TCK0/2 /256. (1:1:1) = Set on compare match, cleared on overflow. f TCK0/NA$B3io_timer.bmpNOCR2-7Timer/Counter2 Output Compare Register Bit 7RW0OCR2-6Timer/Counter2 Output Compare Register Bit 6RW0OCR2-5Timer/Counter2 Output Compare Register Bit 5RW0OCR2-4Timer/Counter2 Output Compare Register Bit 4RW0OCR2-3Timer/Counter2 Output Compare Register Bit 3RW0OCR2-2Timer/Counter2 Output Compare Register Bit 2RW0OCR2-1Timer/Counter2 Output Compare Register Bit 1RW0OCR2-0Timer/Counter2 Output Compare Register Bit 0RW0ASSRAsynchronous Status RegisterNA$B6io_flag.bmpYEXCLKEnable External Clock InputWhen EXCLK is written to one, and asynchronous clock is selected, the external clock input buffer is enabled and an external clock can be input on Timer Oscillator 1 (TOSC1) pin instead of a 32 kHz crystal. Writing to EXCLK should be done before asynchronous operation is selected. Note that the crystal Oscillator will only run when this bit is zero.RW0AS2Asynchronous Timer/Counter2When AS2 is written to zero, Timer/Counter2 is clocked from the I/O clock, clkI/O. When AS2 is written to one, Timer/Counter2 is clocked from a crystal Oscillator connected to the Timer Oscillator 1 (TOSC1) pin. When the value of AS2 is changed, the contents of TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B might be corrupted.RW0TCN2UBTimer/Counter2 Update BusyWhen Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set. When TCNT2 has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCNT2 is ready to be updated with a new value.R0OCR2AUBOutput Compare Register2 Update BusyWhen Timer/Counter2 operates asynchronously and OCR2A is written, this bit becomes set. When OCR2A has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that OCR2A is ready to be updated with a new value.R0OCR2BUBOutput Compare Register 2 Update BusyWhen Timer/Counter2 operates asynchronously and OCR2B is written, this bit becomes set. When OCR2B has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that OCR2B is ready to be updated with a new value.R0TCR2AUBTimer/Counter Control Register2 Update BusyWhen Timer/Counter2 operates asynchronously and TCCR2A is written, this bit becomes set. When TCCR2A has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCCR2A is ready to be updated with a new value.R0TCR2BUBTimer/Counter Control Register2 Update BusyWhen Timer/Counter2 operates asynchronously and TCCR2B is written, this bit becomes set. When TCCR2B has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCCR2B is ready to be updated with a new value.R0GTCCRGeneral Timer Counter Control register$23$43io_flag.bmpYTSMTimer/Counter Synchronization ModeRW0PSRASYPSR2Prescaler Reset Timer/Counter2When this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally cleared immediately by hardware. If the bit is written when Timer/Counter2 is operating in asynchronous mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by hardware if the TSM bit is set. Refer to the description of the “Bit 7 – TSM: Timer/Counter Synchronization Mode” on page 107 for a description of the Timer/Counter Synchronization mode.RW0[WDTCSR]io_watch.bmpWDTCSRWatchdog Timer Control RegisterNA$60io_flag.bmpYWDIFWatchdog Timeout Interrupt FlagRW0WDIEWatchdog Timeout Interrupt EnableRW0WDP3Watchdog Timer Prescaler Bit 3RW0WDCEWatchdog Change EnableRW0WDEWatch Dog EnableWhen the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdogRW0WDP2Watch Dog Timer Prescaler bit 2RW0WDP1Watch Dog Timer Prescaler bit 1RW0WDP0Watch Dog Timer Prescaler bit 0RW0[UDR1:UCSR1A:UCSR1B:UCSR1C:UBRR1H:UBRR1L]
[UBRR1H:UBRR1L]
io_com.bmpThe Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. The main features are: • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • High Resolution Baud Rate Generator • Supports Serial Frames with 5, 6, 7, 8 or 9 Data Bits and 1 or 2 Stop Bits • Odd or Even Parity Generation and Parity Check Supported by Hardware • Data OverRun Detection • Framing Error Detection • Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter • Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete • Multi-processor Communication Mode • Double Speed Asynchronous CommunicaUDR1USART I/O Data RegisterThe UDR1 register is actually two physically separate registers sharing the same I/O address. When writing to the register, the USART Transmit Data register is written. When reading from UDR0, the USART Receive Data register is read.NA$CEio_com.bmpNUDR1-7USART I/O Data Register bit 7RW0UDR1-6USART I/O Data Register bit 6RW0UDR1-5USART I/O Data Register bit 5RW0UDR1-4USART I/O Data Register bit 4RW0UDR1-3USART I/O Data Register bit 3RW0UDR1-2USART I/O Data Register bit 2RW0UDR1-1USART I/O Data Register bit 1RW0UDR1-0USART I/O Data Register bit 0RW0UCSR1AUSART Control and Status Register ANA$C8io_flag.bmpYRXC1USART Receive CompleteThis bit is set (one) when a received character is transferred from the Receiver Shift register to UDR0. The bit is set regard-less of any detected framing errors. When the RXCIE bit in UCR is set, the USART Receive Complete interrupt will be executed when RXC is set(one). RXC is cleared by reading UDR0. When interrupt-driven data reception is used, the USART Receive Complete Interrupt routine must read UDRin order to clear RXC, otherwise a new interrupt will occur once the interrupt routine terminates.R0TXC1USART Transmitt CompleteThis bit is set (one) when the entire character (including the stop bit) in the Transmit Shift register has been shifted out and no new data has been written to UDR0. This flag is especially useful in half-duplex communications interfaces, where a transmitting application must enter receive mode and free the communications bus immediately after completing the transmission. When the TXCIE bit in UCR is set, setting of TXC causes the USART Transmit Complete interrupt to be executed. TXC is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the TXC bit is cleared (zero) by writing a logical one to the bRW0UDRE1USART Data Register EmptyThis bit is set (one) when a character written to UDRis transferred to the Transmit shift register. Setting of this bit indicates that the transmitter is ready to receive a new character for transmission. When the UDR0IE bit in UCR is set, the USART Transmit Complete interrupt to be executed as long as UDR0E is set. UDR0E is cleared by writing UDR0. When interrupt-driven data transmittal is used, the USART Data Register Empty Interrupt routine must write UDRin order to clear UDR0E, otherwise a new interrupt will occur once the interrupt routine terminates. UDR0E is set (one) during reset to indicate that the transmitter is reR1FE1Framing ErrorThis bit is set if a Framing Error condition is detected, i.e. when the stop bit of an incoming character is zero. The FE bit is cleared when the stop bit of received data is one.R0DOR1Data overRunThis bit is set if an Overrun condition is detected, i.e. when a character already present in the UDRregister is not read before the next character has been shifted into the Receiver Shift register. The OR bit is buffered, which means that it will be set once the valid data still in UDR0E is read. The OR bit is cleared (zero) when data is received and transferred to UDR0. R0UPE1Parity ErrorThis bit is set if the next character in the receive buffer had a Parity Error when received and the parity checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer (UDR0) is read. Always set this bit to zero when writing to UCSR0A.R0U2X1Double the USART transmission speedThis bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation. Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous communication.RW0MPCM1Multi-processor Communication ModeThis bit enables the Multi-processor Communication Mode. When the MPCM bit is written to one, all the incoming frames received by the USART receiver that do not contain address information will be ignored. The transmitter is unaffected by the MPCM setting. For more detailed information see “Multi-processor Communication Mode” on page 152.RW0UCSR1BUSART Control and Status Register BNA$C9io_flag.bmpYRXCIE1RX Complete Interrupt EnableWriting this bit to one enables interrupt on the RXC flag. A USART Receive Complete interrupt will be generated only if the RXCIE bit is written to one, the global interrupt flag in SREG is written to one and the RXC bit in UCSR0A is set.RW0TXCIE1TX Complete Interrupt EnableWriting this bit to one enables interrupt on the TXC flag. A USART Transmit Complete interrupt will be generated only if the TXCIE bit is written to one, the global interrupt flag in SREG is written to one and the TXC bit in UCSR0A is set.RW0UDRIE1USART Data register Empty Interrupt EnableWriting this bit to one enables interrupt on the UDR0E flag. A Data Register Empty interrupt will be generated only if the UDR0IE bit is written to one, the global interrupt flag in SREG is written to one and the UDR0E bit in UCSR0A is set.RW1RXEN1Receiver EnableWriting this bit to one enables the USART receiver. The receiver will override normal port operation for the RxD pin when enabled. Disabling the receiver will flush the receive buffer invalidating the FE, DOR and PE flags.RW0TXEN1Transmitter EnableWriting this bit to one enables the USART transmitter. The transmitter will override normal port operation for the TxD pin when enabled. The disabling of the transmitter (writing TXEN to zero) will not become effective until ongoing and pending transmissions are completed, i.e. when the transmit shift register and transmit buffer register does not contain data to be transmitted. When disabled, the transmitter will no longer override the TxD port.RW0UCSZ12Character SizeThe UCSZ2 bits combined with the UCSZ1:0 bit in UCSR0C sets the number of data bits (character size) in a frame the receiver and transmitter use.RW0RXB81Receive Data Bit 8RXB8 is the 9th data bit of the received character when operating with serial frames with 9 data bits. Must be read before reading the low bits from UDR0.R0TXB81Transmit Data Bit 8TXB8 is the 9th data bit in the character to be transmitted when operating with serial frames with 9 data bits. Must be writ-ten before writing the low bits to UDR0.W0UCSR1CUSART Control and Status Register CNA$CAio_flag.bmpYUMSEL11USART Mode SelectRW0UMSEL10USART Mode SelectRW0UPM11Parity Mode Bit 1This bit enable and set type of parity generation and check. If enabled, the transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value for the incoming data and compare it to the UPM0 setting. If a mismatch is detected, the PE flag in UCSR0A will be set.RW0UPM10Parity Mode Bit 0This bit enable and set type of parity generation and check. If enabled, the transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value for the incoming data and compare it to the UPM0 setting. If a mismatch is detected, the PE flag in UCSR0A will be set.RW0USBS1Stop Bit Select0: 1-bit. 1: 2-bit.RW0UCSZ11Character SizeCharacter Size: 0 0 0 = 5-bit. 0 0 1 = 6-bit. 0 1 0 = 7 bit. 0 1 1 = 8-bit. 1 1 1 = 9 bit.RW1UCSZ10Character SizeCharacter Size: 0 0 0 = 5-bit. 0 0 1 = 6-bit. 0 1 0 = 7 bit. 0 1 1 = 8-bit. 1 1 1 = 9 bit.RW1UCPOL1Clock PolarityThis bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOL bit sets the relationship between data output change and data input sample, and the synchronous clock (XCK).RW0UBRR1HUSART Baud Rate Register High ByteThis is a 12-bit register which contains the USART baud rate. The UBRR0H contains the 4 most significant bits, and the UBRR0L contains the 8 least significant bits of the USART baud rate. Ongoing transmissions by the transmitter and receiver will be corrupted if the baud rate is changed. Writing UBRR0L will trigger an immediate update of the baud rate prescaler.NA$CDio_com.bmpNUBRR11USART Baud Rate Register bit 11RW0UBRR10USART Baud Rate Register bit 10RW0UBRR9USART Baud Rate Register bit 9RW0UBRR8USART Baud Rate Register bit 8RW0UBRR1LUSART Baud Rate Register Low ByteThis is a 12-bit register which contains the USART baud rate. The UBRR0H contains the 4 most significant bits, and the UBRR0L contains the 8 least significant bits of the USART baud rate. Ongoing transmissions by the transmitter and receiver will be corrupted if the baud rate is changed. Writing UBRR0L will trigger an immediate update of the baud rate prescaler.NA$CCio_com.bmpNUBRR7USART Baud Rate Register bit 7RW0UBRR6USART Baud Rate Register bit 6RW0UBRR5USART Baud Rate Register bit 5RW0UBRR4USART Baud Rate Register bit 4RW0UBRR3USART Baud Rate Register bit 3RW0UBRR2USART Baud Rate Register bit 2RW0UBRR1USART Baud Rate Register bit 1RW0UBRR0USART Baud Rate Register bit 0RW0[EEARH:EEARL:EEDR:EECR]io_cpu.bmpEEPROM Read/Write Access. The EEPROM access registers are accessible in the I/O space. The write access time for the EEPROM is given in Table 1. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page 19. for details on how to avoid problems in these situations.In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When theEEPROM is written, the CPU is halted for two clock cycles before the next instruction is executeEEARHEEPROM Address Register Low ByteBits 11..0 - EEAR11..0: EEPROM Address The EEPROM Address Registers - EEARH and EEARL specify the EEPROM address in the 4K bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 4096. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed. $22$42io_cpu.bmpNEEAR11EEPROM Read/Write Access Bit 11RW0EEAR10EEPROM Read/Write Access Bit 10RW0EEAR9EEPROM Read/Write Access Bit 9RW0EEAR8EEPROM Read/Write Access Bit 8RW0EEARLEEPROM Address Register Low ByteBits 11..0 - EEAR11..0: EEPROM Address The EEPROM Address Registers - EEARH and EEARL specify the EEPROM address in the 4K bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 4096. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed. $21$41io_cpu.bmpNEEAR7EEPROM Read/Write Access Bit 7RW0EEAR6EEPROM Read/Write Access Bit 6RW0EEAR5EEPROM Read/Write Access Bit 5RW0EEAR4EEPROM Read/Write Access Bit 4RW0EEAR3EEPROM Read/Write Access Bit 3RW0EEAR2EEPROM Read/Write Access Bit 2RW0EEAR1EEPROM Read/Write Access Bit 1RW0EEAR0EEPROM Read/Write Access Bit 0RW0EEDREEPROM Data RegisterFor the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.$20$40io_cpu.bmpNEEDR7EEPROM Data Register bit 7RW0EEDR6EEPROM Data Register bit 6RW0EEDR5EEPROM Data Register bit 5RW0EEDR4EEPROM Data Register bit 4RW0EEDR3EEPROM Data Register bit 3RW0EEDR2EEPROM Data Register bit 2RW0EEDR1EEPROM Data Register bit 1RW0EEDR0EEPROM Data Register bit 0RW0EECREEPROM Control Register$1F$3Fio_flag.bmpYEEPM1EEPROM Programming Mode Bit 1The EEPROM Programming mode bit setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in Table 2. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.RWXEEPM0EEPROM Programming Mode Bit 0The EEPROM Programming mode bit setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in Table 2. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.RWXEERIEEEPROM Ready Interrupt EnableEEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared.RW0EEMPEEEPROM Master Write EnableThe EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is written to one, writing EEWE to one within 4 clock cycles will write data to the EEPROM at the selected address. If EEMWE is zero, writing EEWE to one will have no effect. When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure.RW0EEPEEEPROM Write EnableThe EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential): 1. Wait until EEWE becomes zero. 2. Wait until SPMEN in SPMCR becomes zero. 3. Write new EEPROM address to EEAR (optional). 4. Write new EEPROM data to EEDR (optional). 5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR. 6. Within four clock cycles after setting EEMWE, write a logical one to EEWE. The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a boot loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See “Boot Loader Support - Read While Write self-programming” on page 228 for details about boot programming. Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR regis-ter will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the 4 last steps to avoid these problems. When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruc-tion is executedRWXEEREEEPROM Read EnableThe EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR register. The calibrated oscillator is used to time the EEPROM accesses. Table 1 lists the typical programming time for EEPROM access from the CPURW0[TIMSK5:TIFR5:TCCR5A:TCCR5B:TCCR5C:TCNT5H:TCNT5L:OCR5AH:OCR5AL:OCR5BH:OCR5BL:ICR5H:ICR5L:OCR5CH:OCR5CL]
[TCNT5H:TCNT5L];[OCR5AH:OCR5AL];[OCR5BH:OCR5BL];[OCR5CH:OCR5CL];[ICR5H:ICR3L]
io_timer.bmpt16pwm5_00.xmlTCCR5ATimer/Counter5 Control Register ANA$120io_flag.bmpYCOM5A1Compare Output Mode 1A, bit 1The COM5A1 and COM5A0 control bits determine any output pin action following a compare match in Timer/Counter5. Any output pin actions affect pin OC5A - Output CompareA. This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10.RW0COM5A0Compare Output Mode 5A, bit 0The COM5A1 and COM5A0 control bits determine any output pin action following a compare match in Timer/Counter5. Any output pin actions affect pin OC5A - Output CompareA. This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10.RW0COM5B1Compare Output Mode 5B, bit 1The COM5B1 and COM5B0 control bits determine any output pin action following a compare match in Timer/Counter5. Any output pin actions affect pin OC5B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.RW0COM5B0Compare Output Mode 5B, bit 0The COM5B1 and COM5B0 control bits determine any output pin action following a compare match in Timer/Counter5. Any output pin actions affect pin OC5B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.RW0COM5C1Compare Output Mode 5C, bit 1The COM5C1 and COM5C0 control bits determine any output pin action following a compare match in Timer/Counter5. Any output pin actions affect pin OC5B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.RW0COM5C0Compare Output Mode 5C, bit 0The COM5C1 and COM5C0 control bits determine any output pin action following a compare match in Timer/Counter5. Any output pin actions affect pin OC5B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.RW0WGM51Waveform Generation ModeCombined with the WGM53:2 bits found in the TCCR5B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.RW0WGM50Waveform Generation ModeCombined with the WGM53:2 bits found in the TCCR5B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.RW0TCCR5BTimer/Counter5 Control Register BNA$121io_flag.bmpYICNC5Input Capture 5 Noise CancelerWhen the ICNC5 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the ICP - input capture pin - as specified. When the ICNC5 bit is set (one), four successive samples are measures on the ICP - input capture pin, and all samples must be high/low according to the input capture trigger specification in the ICES5 bit. The actual sampling frequency is XTAL clock frequency.RW0ICES5Input Capture 5 Edge SelectWhile the ICES5 bit is cleared (zero), the Timer/Counter5 contents are transferred to the Input Capture Register - ICR5 - on the falling edge of the input capture pin - ICP. While the ICES5 bit is set (one), the Timer/Counter5 contents are transferred to the Input Capture Register - ICR5 - on the rising edge of the input capture pin - ICP.RW0WGM53Waveform Generation ModeCombined with the WGM53:2 bits found in the TCCR5B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.RW0WGM52Waveform Generation ModeCombined with the WGM53:2 bits found in the TCCR5B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.RW0CS52Prescaler source of Timer/Counter 5Select Prescaling Clock Source of Timer/Counter5. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T5, falling edge. (1:1:1) = External Pin 1, rising edge.RW0CS51Prescaler source of Timer/Counter 5Select Prescaling Clock Source of Timer/Counter5. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T5, falling edge. (1:1:1) = External Pin 1, rising edge.RW0CS50Prescaler source of Timer/Counter 5Select Prescaling Clock Source of Timer/Counter5. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.RW0TCCR5CTimer/Counter 5 Control Register CNA$122io_flag.bmpYFOC5AForce Output Compare 5AWriting a logical one to this bit, forces a change in the compare match output pin PD5 according to the values already set in COM5A1 and COM5A0.If the COM5A1 and COM5A0 bits are written in the same cycle as FOC5A,the new settings will not take effect until next compare match or forced compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM5A1 and COM5A0 happens as if a Compare Match had occurred, but no interrupt is generated and it will not clear the timer even if CTC5 in TCCR5B is set. The corresponding I/O pin must be set as an output pin for the FOC5A bit to have effect on the pin. The FOC5A bit will always be read as zero. The setting of the FOC5A bit has no effect in PWM mRW0FOC5BForce Output Compare 5BWriting a logical one to this bit, forces a change in the compare match output pin PD4 according to the values already set in COM5B1 and COM5B0.If the COM5B1 and COM5B0 bits are written in the same cycle as FOC5B,the new settings will not take effect until next compare match or forced compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM5B1 and COM5B0 happens as if a Compare Match had occurred, but no interrupt is generated. The corresponding I/O pin must be set as an output pin for the FOC5B bit to have effect on the pin. The FOC5B bit will always be read as zero. The setting of the FOC5B bit has no effect in PWM moRW0FOC5CForce Output Compare 5CWriting a logical one to this bit, forces a change in the compare match output pin PD4 according to the values already set in COM5B1 and COM5B0.If the COM5B1 and COM5B0 bits are written in the same cycle as FOC5B,the new settings will not take effect until next compare match or forced compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM5B1 and COM5B0 happens as if a Compare Match had occurred, but no interrupt is generated. The corresponding I/O pin must be set as an output pin for the FOC5B bit to have effect on the pin. The FOC5B bit will always be read as zero. The setting of the FOC5B bit has no effect in PWM moRW0TCNT5HTimer/Counter5 High ByteThis 16-bit register contains the prescaled value of the 16-bit Timer/Counter5. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR5A, OCR5B and ICR5. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt rouNA$125io_timer.bmpNTCNT5H7Timer/Counter5 High Byte bit 7RW0TCNT5H6Timer/Counter5 High Byte bit 6RW0TCNT5H5Timer/Counter5 High Byte bit 5RW0TCNT5H4Timer/Counter5 High Byte bit 4RW0TCNT5H3Timer/Counter5 High Byte bit 3RW0TCNT5H2Timer/Counter5 High Byte bit 2RW0TCNT5H1Timer/Counter5 High Byte bit 1RW0TCNT5H0Timer/Counter5 High Byte bit 0RW0TCNT5LTimer/Counter5 Low ByteThis 16-bit register contains the prescaled value of the 16-bit Timer/Counter5. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR5A, OCR5B and ICR5. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interruNA$124io_timer.bmpNTCNT5L7Timer/Counter5 Low Byte bit 7RW0TCNT5L6Timer/Counter5 Low Byte bit 6RW0TCNT5L5Timer/Counter5 Low Byte bit 5RW0TCNT5L4Timer/Counter5 Low Byte bit 4RW0TCNT5L3Timer/Counter5 Low Byte bit 3RW0TCNT5L2Timer/Counter5 Low Byte bit 2RW0TCNT5L1Timer/Counter5 Low Byte bit 1RW0TCNT5L0Timer/Counter5 Low Byte bit 0RW0OCR5AHTimer/Counter5 Outbut Compare Register A High ByteThe output compare registers are 16-bit read/write registers. The Timer/Counter5 Output Compare Registers contain the data to be continuously compared with Timer/Counter5. Actions on compare matches are specified in the Timer/Counter5 Control and Status register.A compare match does only occur if Timer/Counter5 counts to the OCR value. A software write that sets TCNT5 and OCR5A or OCR5B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR5A and OCR5B - are 16-bit registers, a temporary register TEMP is used when OCR5A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR5AH or OCR5BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR5AL or OCR5BL, the TEMP register is simultaneously written to OCR5AH or OCR5BH. Consequently, the high byte OCR5AH or OCR5BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT5, and ICR5. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrNA$129io_timer.bmpNOCR5AH7Timer/Counter5 Outbut Compare Register High Byte bit 7RW0OCR5AH6Timer/Counter5 Outbut Compare Register High Byte bit 6RW0OCR5AH5Timer/Counter5 Outbut Compare Register High Byte bit 5RW0OCR5AH4Timer/Counter5 Outbut Compare Register High Byte bit 4RW0OCR5AH3Timer/Counter5 Outbut Compare Register High Byte bit 3RW0OCR5AH2Timer/Counter5 Outbut Compare Register High Byte bit 2RW0OCR5AH1Timer/Counter5 Outbut Compare Register High Byte bit 1RW0OCR5AH0Timer/Counter5 Outbut Compare Register High Byte bit 0RW0OCR5ALTimer/Counter5 Outbut Compare Register A Low ByteThe output compare registers are 16-bit read/write registers. The Timer/Counter5 Output Compare Registers contain the data to be continuously compared with Timer/Counter5. Actions on compare matches are specified in the Timer/Counter5 Control and Status register.A compare match does only occur if Timer/Counter5 counts to the OCR value. A software write that sets TCNT5 and OCR5A or OCR5B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR5A and OCR5B - are 16-bit registers, a temporary register TEMP is used when OCR5A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR5AH or OCR5BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR5AL or OCR5BL, the TEMP register is simultaneously written to OCR5AH or OCR5BH. Consequently, the high byte OCR5AH or OCR5BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT5, and ICR5. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interruNA$128io_timer.bmpNOCR5AL7Timer/Counter5 Outbut Compare Register Low Byte Bit 7RW0OCR5AL6Timer/Counter5 Outbut Compare Register Low Byte Bit 6RW0OCR5AL5Timer/Counter5 Outbut Compare Register Low Byte Bit 5RW0OCR5AL4Timer/Counter5 Outbut Compare Register Low Byte Bit 4RW0OCR5AL3Timer/Counter5 Outbut Compare Register Low Byte Bit 3RW0OCR5AL2Timer/Counter5 Outbut Compare Register Low Byte Bit 2RW0OCR5AL1Timer/Counter5 Outbut Compare Register Low Byte Bit 1RW0OCR5AL0Timer/Counter5 Outbut Compare Register Low Byte Bit 0RW0OCR5BHTimer/Counter5 Output Compare Register B High ByteThe output compare registers are 16-bit read/write registers. The Timer/Counter5 Output Compare Registers contain the data to be continuously compared with Timer/Counter5. Actions on compare matches are specified in the Timer/Counter5 Control and Status register.A compare match does only occur if Timer/Counter5 counts to the OCR value. A software write that sets TCNT5 and OCR5A or OCR5B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR5A and OCR5B - are 16-bit registers, a temporary register TEMP is used when OCR5A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR5AH or OCR5BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR5AL or OCR5BL, the TEMP register is simultaneously written to OCR5AH or OCR5BH. Consequently, the high byte OCR5AH or OCR5BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT5, and ICR5. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt rNA$12Bio_timer.bmpNOCR5BH7Timer/Counter5 Output Compare Register High Byte bit 7RW0OCR5BH6Timer/Counter5 Output Compare Register High Byte bit 6RW0OCR5BH5Timer/Counter5 Output Compare Register High Byte bit 5RW0OCR5BH4Timer/Counter5 Output Compare Register High Byte bit 4RW0OCR5BH3Timer/Counter5 Output Compare Register High Byte bit 3RW0OCR5BH2Timer/Counter5 Output Compare Register High Byte bit 2RW0OCR5BH1Timer/Counter5 Output Compare Register High Byte bit 1RW0OCR5BH0Timer/Counter5 Output Compare Register High Byte bit 0RW0OCR5BLTimer/Counter5 Output Compare Register B Low ByteThe output compare registers are 16-bit read/write registers. The Timer/Counter5 Output Compare Registers contain the data to be continuously compared with Timer/Counter5. Actions on compare matches are specified in the Timer/Counter5 Control and Status register.A compare match does only occur if Timer/Counter5 counts to the OCR value. A software write that sets TCNT5 and OCR5A or OCR5B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR5A and OCR5B - are 16-bit registers, a temporary register TEMP is used when OCR5A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR5AH or OCR5BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR5AL or OCR5BL, the TEMP register is simultaneously written to OCR5AH or OCR5BH. Consequently, the high byte OCR5AH or OCR5BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT5, and ICR5. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt routNA$12Aio_timer.bmpNOCR5BL7Timer/Counter5 Output Compare Register Low Byte bit 7R0OCR5BL6Timer/Counter5 Output Compare Register Low Byte bit 6RW0OCR5BL5Timer/Counter5 Output Compare Register Low Byte bit 5RW0OCR5BL4Timer/Counter5 Output Compare Register Low Byte bit 4RW0OCR5BL3Timer/Counter5 Output Compare Register Low Byte bit 3RW0OCR5BL2Timer/Counter5 Output Compare Register Low Byte bit 2RW0OCR5BL1Timer/Counter5 Output Compare Register Low Byte bit 1RW0OCR5BL0Timer/Counter5 Output Compare Register Low Byte bit 0RW0OCR5CHTimer/Counter5 Output Compare Register B High ByteThe output compare registers are 16-bit read/write registers. The Timer/Counter5 Output Compare Registers contain the data to be continuously compared with Timer/Counter5. Actions on compare matches are specified in the Timer/Counter5 Control and Status register.A compare match does only occur if Timer/Counter5 counts to the OCR value. A software write that sets TCNT5 and OCR5A or OCR5B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR5A and OCR5B - are 16-bit registers, a temporary register TEMP is used when OCR5A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR5AH or OCR5BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR5AL or OCR5BL, the TEMP register is simultaneously written to OCR5AH or OCR5BH. Consequently, the high byte OCR5AH or OCR5BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT5, and ICR5. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt rNA$12Dio_timer.bmpNOCR5CH7Timer/Counter5 Output Compare Register High Byte bit 7RW0OCR5CH6Timer/Counter5 Output Compare Register High Byte bit 6RW0OCR5CH5Timer/Counter5 Output Compare Register High Byte bit 5RW0OCR5CH4Timer/Counter5 Output Compare Register High Byte bit 4RW0OCR5CH3Timer/Counter5 Output Compare Register High Byte bit 3RW0OCR5CH2Timer/Counter5 Output Compare Register High Byte bit 2RW0OCR5CH1Timer/Counter5 Output Compare Register High Byte bit 1RW0OCR5CH0Timer/Counter5 Output Compare Register High Byte bit 0RW0OCR5CLTimer/Counter5 Output Compare Register B Low ByteThe output compare registers are 16-bit read/write registers. The Timer/Counter5 Output Compare Registers contain the data to be continuously compared with Timer/Counter5. Actions on compare matches are specified in the Timer/Counter5 Control and Status register.A compare match does only occur if Timer/Counter5 counts to the OCR value. A software write that sets TCNT5 and OCR5A or OCR5B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR5A and OCR5B - are 16-bit registers, a temporary register TEMP is used when OCR5A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR5AH or OCR5BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR5AL or OCR5BL, the TEMP register is simultaneously written to OCR5AH or OCR5BH. Consequently, the high byte OCR5AH or OCR5BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT5, and ICR5. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt routNA$12Cio_timer.bmpNOCR5CL7Timer/Counter5 Output Compare Register Low Byte bit 7R0OCR5CL6Timer/Counter5 Output Compare Register Low Byte bit 6RW0OCR5CL5Timer/Counter5 Output Compare Register Low Byte bit 5RW0OCR5CL4Timer/Counter5 Output Compare Register Low Byte bit 4RW0OCR5CL3Timer/Counter5 Output Compare Register Low Byte bit 3RW0OCR5CL2Timer/Counter5 Output Compare Register Low Byte bit 2RW0OCR5CL1Timer/Counter5 Output Compare Register Low Byte bit 1RW0OCR5CL0Timer/Counter5 Output Compare Register Low Byte bit 0RW0ICR5HTimer/Counter5 Input Capture Register High ByteThe input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES5) of the signal at the input capture pin -ICP - is detected, the current value of the Timer/Counter5 is transferred to the Input Capture Register - ICR5. At the same time, the input capture flag - ICF5 - is set (one). Since the Input Capture Register - ICR5 - is a 16-bit register, a temporary register TEMP is used when ICR5 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR5L, the data is sent to the CPU and the data of the high byte ICR5H is placed in the TEMP register. When the CPU reads the data in the high byte ICR5H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR5L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT5, OCR5A and OCR5B. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interruptNA$127io_timer.bmpNICR5H7Timer/Counter5 Input Capture Register High Byte bit 7RW0ICR5H6Timer/Counter5 Input Capture Register High Byte bit 6R0ICR5H5Timer/Counter5 Input Capture Register High Byte bit 5R0ICR5H4Timer/Counter5 Input Capture Register High Byte bit 4R0ICR5H3Timer/Counter5 Input Capture Register High Byte bit 3R0ICR5H2Timer/Counter5 Input Capture Register High Byte bit 2R0ICR5H1Timer/Counter5 Input Capture Register High Byte bit 1R0ICR5H0Timer/Counter5 Input Capture Register High Byte bit 0R0ICR5LTimer/Counter5 Input Capture Register Low ByteThe input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES5) of the signal at the input capture pin -ICP - is detected, the current value of the Timer/Counter5 is transferred to the Input Capture Register - ICR5. At the same time, the input capture flag - ICF5 - is set (one). Since the Input Capture Register - ICR5 - is a 16-bit register, a temporary register TEMP is used when ICR5 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR5L, the data is sent to the CPU and the data of the high byte ICR5H is placed in the TEMP register. When the CPU reads the data in the high byte ICR5H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR5L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT5, OCR5A and OCR5B. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interNA$126io_timer.bmpNICR5L7Timer/Counter5 Input Capture Register Low Byte bit 7R0ICR5L6Timer/Counter5 Input Capture Register Low Byte bit 6R0ICR5L5Timer/Counter5 Input Capture Register Low Byte bit 5R0ICR5L4Timer/Counter5 Input Capture Register Low Byte bit 4R0ICR5L3Timer/Counter5 Input Capture Register Low Byte bit 3R0ICR5L2Timer/Counter5 Input Capture Register Low Byte bit 2R0ICR5L1Timer/Counter5 Input Capture Register Low Byte bit 1R0ICR5L0Timer/Counter5 Input Capture Register Low Byte bit 0R0TIMSK5Timer/Counter5 Interrupt Mask RegisterNA$73io_flag.bmpYICIE5Timer/Counter5 Input Capture Interrupt EnableWhen the TICIE5 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter5 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on pin 31, ICP, i.e., when the ICF5 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.RW0OCIE5CTimer/Counter5 Output Compare C Match Interrupt EnableWhen the OCIE5C bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter5 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter5 occurs, i.e., when the OCF5B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.R0OCIE5BTimer/Counter5 Output Compare B Match Interrupt EnableWhen the OCIE5B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter5 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter5 occurs, i.e., when the OCF5B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.R0OCIE5ATimer/Counter5 Output Compare A Match Interrupt EnableWhen the OCIE5A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter5 CompareA Match interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a CompareA match in Timer/Counter5 occurs, i.e., when the OCF5A bit is set in the Timer/Counter Interrupt Flag Register - TIFR.RW0TOIE5Timer/Counter5 Overflow Interrupt EnableWhen the TOIE5 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter5 Overflow interrupt is enabled. The corresponding interrupt (at vector $006) is executed if an overflow in Timer/Counter5 occurs, i.e., when the TOV5 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.RW0TIFR5Timer/Counter5 Interrupt Flag register$1A$3Aio_flag.bmpYICF5Input Capture Flag 5The ICF5 bit is set (one) to flag an input capture event, indicating that the Timer/Counter5 value has been transferred to the input capture register - ICR5. ICF5 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF5 is cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE5 (Timer/Counter5 Input Capture Interrupt Enable), and ICF5 are set (one), the Timer/Counter5 Capture Interrupt is executed. RW0OCF5COutput Compare Flag 5CThe OCF5C bit is set (one) when compare match occurs between the Timer/Counter5 and the data in OCR5B - Output Compare Register 5B. OCF5B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF5B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE5B (Timer/Counter5 Compare match InterruptB Enable), and the OCF5B are set (one), the Timer/Counter5 Compare B match Interrupt is executed.RW0OCF5BOutput Compare Flag 5BThe OCF5B bit is set (one) when compare match occurs between the Timer/Counter5 and the data in OCR5B - Output Compare Register 5B. OCF5B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF5B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE5B (Timer/Counter5 Compare match InterruptB Enable), and the OCF5B are set (one), the Timer/Counter5 Compare B match Interrupt is executed.RW0OCF5AOutput Compare Flag 5AThe OCF5A bit is set (one) when compare match occurs between the Timer/Counter5 and the data in OCR5A - Output Compare Register 5A. OCF5A is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF5A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE5A (Timer/Counter5 Compare match InterruptA Enable), and the OCF5A are set (one), the Timer/Counter5 Compare A match Interrupt is executed. RW0TOV5Timer/Counter5 Overflow FlagThe TOV5 is set (one) when an overflow occurs in Timer/Counter5. TOV5 is cleared by hardware when executing the cor-responding interrupt handling vector. Alternatively, TOV5 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE5 (Timer/Counter5 Overflow Interrupt Enable), and TOV5 are set (one), the Timer/Counter5 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter5 changes counting direction at $0000.RW0[TIMSK4:TIFR4:TCCR4A:TCCR4B:TCCR4C:TCNT4H:TCNT4L:OCR4AH:OCR4AL:OCR4BH:OCR4BL:ICR4H:ICR4L:OCR4CH:OCR4CL]
[TCNT4H:TCNT4L];[OCR4AH:OCR4AL];[OCR4BH:OCR4BL];[OCR4CH:OCR4CL];[ICR4H:ICR4L]
io_timer.bmpt16pwm4_00.xmlTCCR4ATimer/Counter4 Control Register ANA$A0io_flag.bmpYCOM4A1Compare Output Mode 1A, bit 1The COM4A1 and COM4A0 control bits determine any output pin action following a compare match in Timer/Counter4. Any output pin actions affect pin OC4A - Output CompareA. This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10.RW0COM4A0Compare Output Mode 4A, bit 0The COM4A1 and COM4A0 control bits determine any output pin action following a compare match in Timer/Counter4. Any output pin actions affect pin OC4A - Output CompareA. This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10.RW0COM4B1Compare Output Mode 4B, bit 1The COM4B1 and COM4B0 control bits determine any output pin action following a compare match in Timer/Counter4. Any output pin actions affect pin OC4B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.RW0COM4B0Compare Output Mode 4B, bit 0The COM4B1 and COM4B0 control bits determine any output pin action following a compare match in Timer/Counter4. Any output pin actions affect pin OC4B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.RW0COM4C1Compare Output Mode 4C, bit 1The COM4C1 and COM4C0 control bits determine any output pin action following a compare match in Timer/Counter4. Any output pin actions affect pin OC4B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.RW0COM4C0Compare Output Mode 4C, bit 0The COM4C1 and COM4C0 control bits determine any output pin action following a compare match in Timer/Counter4. Any output pin actions affect pin OC4B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.RW0WGM41Waveform Generation ModeCombined with the WGM43:2 bits found in the TCCR4B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.RW0WGM40Waveform Generation ModeCombined with the WGM43:2 bits found in the TCCR4B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.RW0TCCR4BTimer/Counter4 Control Register BNA$A1io_flag.bmpYICNC4Input Capture 4 Noise CancelerWhen the ICNC4 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the ICP - input capture pin - as specified. When the ICNC4 bit is set (one), four successive samples are measures on the ICP - input capture pin, and all samples must be high/low according to the input capture trigger specification in the ICES4 bit. The actual sampling frequency is XTAL clock frequency.RW0ICES4Input Capture 4 Edge SelectWhile the ICES4 bit is cleared (zero), the Timer/Counter4 contents are transferred to the Input Capture Register - ICR4 - on the falling edge of the input capture pin - ICP. While the ICES4 bit is set (one), the Timer/Counter4 contents are transferred to the Input Capture Register - ICR4 - on the rising edge of the input capture pin - ICP.RW0WGM43Waveform Generation ModeCombined with the WGM43:2 bits found in the TCCR4B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.RW0WGM42Waveform Generation ModeCombined with the WGM43:2 bits found in the TCCR4B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.RW0CS42Prescaler source of Timer/Counter 4Select Prescaling Clock Source of Timer/Counter4. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T4, falling edge. (1:1:1) = External Pin 1, rising edge.RW0CS41Prescaler source of Timer/Counter 4Select Prescaling Clock Source of Timer/Counter4. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T4, falling edge. (1:1:1) = External Pin 1, rising edge.RW0CS40Prescaler source of Timer/Counter 4Select Prescaling Clock Source of Timer/Counter4. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.RW0TCCR4CTimer/Counter 4 Control Register CNA$A2io_flag.bmpYFOC4AForce Output Compare 4AWriting a logical one to this bit, forces a change in the compare match output pin PD5 according to the values already set in COM4A1 and COM4A0.If the COM4A1 and COM4A0 bits are written in the same cycle as FOC4A,the new settings will not take effect until next compare match or forced compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM4A1 and COM4A0 happens as if a Compare Match had occurred, but no interrupt is generated and it will not clear the timer even if CTC4 in TCCR4B is set. The corresponding I/O pin must be set as an output pin for the FOC4A bit to have effect on the pin. The FOC4A bit will always be read as zero. The setting of the FOC4A bit has no effect in PWM mRW0FOC4BForce Output Compare 4BWriting a logical one to this bit, forces a change in the compare match output pin PD4 according to the values already set in COM4B1 and COM4B0.If the COM4B1 and COM4B0 bits are written in the same cycle as FOC4B,the new settings will not take effect until next compare match or forced compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM4B1 and COM4B0 happens as if a Compare Match had occurred, but no interrupt is generated. The corresponding I/O pin must be set as an output pin for the FOC4B bit to have effect on the pin. The FOC4B bit will always be read as zero. The setting of the FOC4B bit has no effect in PWM moRW0FOC4CForce Output Compare 4CWriting a logical one to this bit, forces a change in the compare match output pin PD4 according to the values already set in COM4B1 and COM4B0.If the COM4B1 and COM4B0 bits are written in the same cycle as FOC4B,the new settings will not take effect until next compare match or forced compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM4B1 and COM4B0 happens as if a Compare Match had occurred, but no interrupt is generated. The corresponding I/O pin must be set as an output pin for the FOC4B bit to have effect on the pin. The FOC4B bit will always be read as zero. The setting of the FOC4B bit has no effect in PWM moRW0TCNT4HTimer/Counter4 High ByteThis 16-bit register contains the prescaled value of the 16-bit Timer/Counter4. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR4A, OCR4B and ICR4. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt rouNA$A5io_timer.bmpNTCNT4H7Timer/Counter4 High Byte bit 7RW0TCNT4H6Timer/Counter4 High Byte bit 6RW0TCNT4H5Timer/Counter4 High Byte bit 5RW0TCNT4H4Timer/Counter4 High Byte bit 4RW0TCNT4H3Timer/Counter4 High Byte bit 3RW0TCNT4H2Timer/Counter4 High Byte bit 2RW0TCNT4H1Timer/Counter4 High Byte bit 1RW0TCNT4H0Timer/Counter4 High Byte bit 0RW0TCNT4LTimer/Counter4 Low ByteThis 16-bit register contains the prescaled value of the 16-bit Timer/Counter4. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR4A, OCR4B and ICR4. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interruNA$A4io_timer.bmpNTCNT4L7Timer/Counter4 Low Byte bit 7RW0TCNT4L6Timer/Counter4 Low Byte bit 6RW0TCNT4L5Timer/Counter4 Low Byte bit 5RW0TCNT4L4Timer/Counter4 Low Byte bit 4RW0TCNT4L3Timer/Counter4 Low Byte bit 3RW0TCNT4L2Timer/Counter4 Low Byte bit 2RW0TCNT4L1Timer/Counter4 Low Byte bit 1RW0TCNT4L0Timer/Counter4 Low Byte bit 0RW0OCR4AHTimer/Counter4 Outbut Compare Register A High ByteThe output compare registers are 16-bit read/write registers. The Timer/Counter4 Output Compare Registers contain the data to be continuously compared with Timer/Counter4. Actions on compare matches are specified in the Timer/Counter4 Control and Status register.A compare match does only occur if Timer/Counter4 counts to the OCR value. A software write that sets TCNT4 and OCR4A or OCR4B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR4A and OCR4B - are 16-bit registers, a temporary register TEMP is used when OCR4A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR4AH or OCR4BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR4AL or OCR4BL, the TEMP register is simultaneously written to OCR4AH or OCR4BH. Consequently, the high byte OCR4AH or OCR4BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT4, and ICR4. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrNA$A9io_timer.bmpNOCR4AH7Timer/Counter4 Outbut Compare Register High Byte bit 7RW0OCR4AH6Timer/Counter4 Outbut Compare Register High Byte bit 6RW0OCR4AH5Timer/Counter4 Outbut Compare Register High Byte bit 5RW0OCR4AH4Timer/Counter4 Outbut Compare Register High Byte bit 4RW0OCR4AH3Timer/Counter4 Outbut Compare Register High Byte bit 3RW0OCR4AH2Timer/Counter4 Outbut Compare Register High Byte bit 2RW0OCR4AH1Timer/Counter4 Outbut Compare Register High Byte bit 1RW0OCR4AH0Timer/Counter4 Outbut Compare Register High Byte bit 0RW0OCR4ALTimer/Counter4 Outbut Compare Register A Low ByteThe output compare registers are 16-bit read/write registers. The Timer/Counter4 Output Compare Registers contain the data to be continuously compared with Timer/Counter4. Actions on compare matches are specified in the Timer/Counter4 Control and Status register.A compare match does only occur if Timer/Counter4 counts to the OCR value. A software write that sets TCNT4 and OCR4A or OCR4B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR4A and OCR4B - are 16-bit registers, a temporary register TEMP is used when OCR4A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR4AH or OCR4BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR4AL or OCR4BL, the TEMP register is simultaneously written to OCR4AH or OCR4BH. Consequently, the high byte OCR4AH or OCR4BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT4, and ICR4. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interruNA$A8io_timer.bmpNOCR4AL7Timer/Counter4 Outbut Compare Register Low Byte Bit 7RW0OCR4AL6Timer/Counter4 Outbut Compare Register Low Byte Bit 6RW0OCR4AL5Timer/Counter4 Outbut Compare Register Low Byte Bit 5RW0OCR4AL4Timer/Counter4 Outbut Compare Register Low Byte Bit 4RW0OCR4AL3Timer/Counter4 Outbut Compare Register Low Byte Bit 3RW0OCR4AL2Timer/Counter4 Outbut Compare Register Low Byte Bit 2RW0OCR4AL1Timer/Counter4 Outbut Compare Register Low Byte Bit 1RW0OCR4AL0Timer/Counter4 Outbut Compare Register Low Byte Bit 0RW0OCR4BHTimer/Counter4 Output Compare Register B High ByteThe output compare registers are 16-bit read/write registers. The Timer/Counter4 Output Compare Registers contain the data to be continuously compared with Timer/Counter4. Actions on compare matches are specified in the Timer/Counter4 Control and Status register.A compare match does only occur if Timer/Counter4 counts to the OCR value. A software write that sets TCNT4 and OCR4A or OCR4B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR4A and OCR4B - are 16-bit registers, a temporary register TEMP is used when OCR4A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR4AH or OCR4BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR4AL or OCR4BL, the TEMP register is simultaneously written to OCR4AH or OCR4BH. Consequently, the high byte OCR4AH or OCR4BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT4, and ICR4. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt rNA$ABio_timer.bmpNOCR4BH7Timer/Counter4 Output Compare Register High Byte bit 7RW0OCR4BH6Timer/Counter4 Output Compare Register High Byte bit 6RW0OCR4BH5Timer/Counter4 Output Compare Register High Byte bit 5RW0OCR4BH4Timer/Counter4 Output Compare Register High Byte bit 4RW0OCR4BH3Timer/Counter4 Output Compare Register High Byte bit 3RW0OCR4BH2Timer/Counter4 Output Compare Register High Byte bit 2RW0OCR4BH1Timer/Counter4 Output Compare Register High Byte bit 1RW0OCR4BH0Timer/Counter4 Output Compare Register High Byte bit 0RW0OCR4BLTimer/Counter4 Output Compare Register B Low ByteThe output compare registers are 16-bit read/write registers. The Timer/Counter4 Output Compare Registers contain the data to be continuously compared with Timer/Counter4. Actions on compare matches are specified in the Timer/Counter4 Control and Status register.A compare match does only occur if Timer/Counter4 counts to the OCR value. A software write that sets TCNT4 and OCR4A or OCR4B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR4A and OCR4B - are 16-bit registers, a temporary register TEMP is used when OCR4A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR4AH or OCR4BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR4AL or OCR4BL, the TEMP register is simultaneously written to OCR4AH or OCR4BH. Consequently, the high byte OCR4AH or OCR4BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT4, and ICR4. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt routNA$AAio_timer.bmpNOCR4BL7Timer/Counter4 Output Compare Register Low Byte bit 7R0OCR4BL6Timer/Counter4 Output Compare Register Low Byte bit 6RW0OCR4BL5Timer/Counter4 Output Compare Register Low Byte bit 5RW0OCR4BL4Timer/Counter4 Output Compare Register Low Byte bit 4RW0OCR4BL3Timer/Counter4 Output Compare Register Low Byte bit 3RW0OCR4BL2Timer/Counter4 Output Compare Register Low Byte bit 2RW0OCR4BL1Timer/Counter4 Output Compare Register Low Byte bit 1RW0OCR4BL0Timer/Counter4 Output Compare Register Low Byte bit 0RW0OCR4CHTimer/Counter4 Output Compare Register B High ByteThe output compare registers are 16-bit read/write registers. The Timer/Counter4 Output Compare Registers contain the data to be continuously compared with Timer/Counter4. Actions on compare matches are specified in the Timer/Counter4 Control and Status register.A compare match does only occur if Timer/Counter4 counts to the OCR value. A software write that sets TCNT4 and OCR4A or OCR4B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR4A and OCR4B - are 16-bit registers, a temporary register TEMP is used when OCR4A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR4AH or OCR4BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR4AL or OCR4BL, the TEMP register is simultaneously written to OCR4AH or OCR4BH. Consequently, the high byte OCR4AH or OCR4BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT4, and ICR4. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt rNA$ADio_timer.bmpNOCR4CH7Timer/Counter4 Output Compare Register High Byte bit 7RW0OCR4CH6Timer/Counter4 Output Compare Register High Byte bit 6RW0OCR4CH5Timer/Counter4 Output Compare Register High Byte bit 5RW0OCR4CH4Timer/Counter4 Output Compare Register High Byte bit 4RW0OCR4CH3Timer/Counter4 Output Compare Register High Byte bit 3RW0OCR4CH2Timer/Counter4 Output Compare Register High Byte bit 2RW0OCR4CH1Timer/Counter4 Output Compare Register High Byte bit 1RW0OCR4CH0Timer/Counter4 Output Compare Register High Byte bit 0RW0OCR4CLTimer/Counter4 Output Compare Register B Low ByteThe output compare registers are 16-bit read/write registers. The Timer/Counter4 Output Compare Registers contain the data to be continuously compared with Timer/Counter4. Actions on compare matches are specified in the Timer/Counter4 Control and Status register.A compare match does only occur if Timer/Counter4 counts to the OCR value. A software write that sets TCNT4 and OCR4A or OCR4B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR4A and OCR4B - are 16-bit registers, a temporary register TEMP is used when OCR4A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR4AH or OCR4BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR4AL or OCR4BL, the TEMP register is simultaneously written to OCR4AH or OCR4BH. Consequently, the high byte OCR4AH or OCR4BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT4, and ICR4. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt routNA$ACio_timer.bmpNOCR4CL7Timer/Counter4 Output Compare Register Low Byte bit 7R0OCR4CL6Timer/Counter4 Output Compare Register Low Byte bit 6RW0OCR4CL5Timer/Counter4 Output Compare Register Low Byte bit 5RW0OCR4CL4Timer/Counter4 Output Compare Register Low Byte bit 4RW0OCR4CL3Timer/Counter4 Output Compare Register Low Byte bit 3RW0OCR4CL2Timer/Counter4 Output Compare Register Low Byte bit 2RW0OCR4CL1Timer/Counter4 Output Compare Register Low Byte bit 1RW0OCR4CL0Timer/Counter4 Output Compare Register Low Byte bit 0RW0ICR4HTimer/Counter4 Input Capture Register High ByteThe input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES4) of the signal at the input capture pin -ICP - is detected, the current value of the Timer/Counter4 is transferred to the Input Capture Register - ICR4. At the same time, the input capture flag - ICF4 - is set (one). Since the Input Capture Register - ICR4 - is a 16-bit register, a temporary register TEMP is used when ICR4 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR4L, the data is sent to the CPU and the data of the high byte ICR4H is placed in the TEMP register. When the CPU reads the data in the high byte ICR4H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR4L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT4, OCR4A and OCR4B. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interruptNA$A7io_timer.bmpNICR4H7Timer/Counter4 Input Capture Register High Byte bit 7RW0ICR4H6Timer/Counter4 Input Capture Register High Byte bit 6R0ICR4H5Timer/Counter4 Input Capture Register High Byte bit 5R0ICR4H4Timer/Counter4 Input Capture Register High Byte bit 4R0ICR4H3Timer/Counter4 Input Capture Register High Byte bit 3R0ICR4H2Timer/Counter4 Input Capture Register High Byte bit 2R0ICR4H1Timer/Counter4 Input Capture Register High Byte bit 1R0ICR4H0Timer/Counter4 Input Capture Register High Byte bit 0R0ICR4LTimer/Counter4 Input Capture Register Low ByteThe input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES4) of the signal at the input capture pin -ICP - is detected, the current value of the Timer/Counter4 is transferred to the Input Capture Register - ICR4. At the same time, the input capture flag - ICF4 - is set (one). Since the Input Capture Register - ICR4 - is a 16-bit register, a temporary register TEMP is used when ICR4 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR4L, the data is sent to the CPU and the data of the high byte ICR4H is placed in the TEMP register. When the CPU reads the data in the high byte ICR4H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR4L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT4, OCR4A and OCR4B. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interNA$A6io_timer.bmpNICR4L7Timer/Counter4 Input Capture Register Low Byte bit 7R0ICR4L6Timer/Counter4 Input Capture Register Low Byte bit 6R0ICR4L5Timer/Counter4 Input Capture Register Low Byte bit 5R0ICR4L4Timer/Counter4 Input Capture Register Low Byte bit 4R0ICR4L3Timer/Counter4 Input Capture Register Low Byte bit 3R0ICR4L2Timer/Counter4 Input Capture Register Low Byte bit 2R0ICR4L1Timer/Counter4 Input Capture Register Low Byte bit 1R0ICR4L0Timer/Counter4 Input Capture Register Low Byte bit 0R0TIMSK4Timer/Counter4 Interrupt Mask RegisterNA$72io_flag.bmpYICIE4Timer/Counter4 Input Capture Interrupt EnableWhen the TICIE4 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter4 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on pin 31, ICP, i.e., when the ICF4 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.RW0OCIE4CTimer/Counter4 Output Compare C Match Interrupt EnableWhen the OCIE4C bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter4 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter4 occurs, i.e., when the OCF4B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.R0OCIE4BTimer/Counter4 Output Compare B Match Interrupt EnableWhen the OCIE4B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter4 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter4 occurs, i.e., when the OCF4B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.R0OCIE4ATimer/Counter4 Output Compare A Match Interrupt EnableWhen the OCIE4A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter4 CompareA Match interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a CompareA match in Timer/Counter4 occurs, i.e., when the OCF4A bit is set in the Timer/Counter Interrupt Flag Register - TIFR.RW0TOIE4Timer/Counter4 Overflow Interrupt EnableWhen the TOIE4 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter4 Overflow interrupt is enabled. The corresponding interrupt (at vector $006) is executed if an overflow in Timer/Counter4 occurs, i.e., when the TOV4 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.RW0TIFR4Timer/Counter4 Interrupt Flag register$19$39io_flag.bmpYICF4Input Capture Flag 4The ICF4 bit is set (one) to flag an input capture event, indicating that the Timer/Counter4 value has been transferred to the input capture register - ICR4. ICF4 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF4 is cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE4 (Timer/Counter4 Input Capture Interrupt Enable), and ICF4 are set (one), the Timer/Counter4 Capture Interrupt is executed. RW0OCF4COutput Compare Flag 4CThe OCF4C bit is set (one) when compare match occurs between the Timer/Counter4 and the data in OCR4B - Output Compare Register 4B. OCF4B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF4B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE4B (Timer/Counter4 Compare match InterruptB Enable), and the OCF4B are set (one), the Timer/Counter4 Compare B match Interrupt is executed.RW0OCF4BOutput Compare Flag 4BThe OCF4B bit is set (one) when compare match occurs between the Timer/Counter4 and the data in OCR4B - Output Compare Register 4B. OCF4B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF4B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE4B (Timer/Counter4 Compare match InterruptB Enable), and the OCF4B are set (one), the Timer/Counter4 Compare B match Interrupt is executed.RW0OCF4AOutput Compare Flag 4AThe OCF4A bit is set (one) when compare match occurs between the Timer/Counter4 and the data in OCR4A - Output Compare Register 4A. OCF4A is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF4A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE4A (Timer/Counter4 Compare match InterruptA Enable), and the OCF4A are set (one), the Timer/Counter4 Compare A match Interrupt is executed. RW0TOV4Timer/Counter4 Overflow FlagThe TOV4 is set (one) when an overflow occurs in Timer/Counter4. TOV4 is cleared by hardware when executing the cor-responding interrupt handling vector. Alternatively, TOV4 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE4 (Timer/Counter4 Overflow Interrupt Enable), and TOV4 are set (one), the Timer/Counter4 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter4 changes counting direction at $0000.RW0[TIMSK3:TIFR3:TCCR3A:TCCR3B:TCCR3C:TCNT3H:TCNT3L:OCR3AH:OCR3AL:OCR3BH:OCR3BL:ICR3H:ICR3L:OCR3CH:OCR3CL]
[TCNT3H:TCNT3L];[OCR3AH:OCR3AL];[OCR3BH:OCR3BL];[OCR3CH:OCR3CL];[ICR3H:ICR3L]
io_timer.bmpt16pwm3_03.xmlTCCR3ATimer/Counter3 Control Register ANA$90io_flag.bmpYCOM3A1Compare Output Mode 1A, bit 1The COM3A1 and COM3A0 control bits determine any output pin action following a compare match in Timer/Counter3. Any output pin actions affect pin OC3A - Output CompareA. This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10.RW0COM3A0Compare Output Mode 3A, bit 0The COM3A1 and COM3A0 control bits determine any output pin action following a compare match in Timer/Counter3. Any output pin actions affect pin OC3A - Output CompareA. This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10.RW0COM3B1Compare Output Mode 3B, bit 1The COM3B1 and COM3B0 control bits determine any output pin action following a compare match in Timer/Counter3. Any output pin actions affect pin OC3B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.RW0COM3B0Compare Output Mode 3B, bit 0The COM3B1 and COM3B0 control bits determine any output pin action following a compare match in Timer/Counter3. Any output pin actions affect pin OC3B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.RW0COM3C1Compare Output Mode 3C, bit 1The COM3C1 and COM3C0 control bits determine any output pin action following a compare match in Timer/Counter3. Any output pin actions affect pin OC3B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.RW0COM3C0Compare Output Mode 3C, bit 0The COM3C1 and COM3C0 control bits determine any output pin action following a compare match in Timer/Counter3. Any output pin actions affect pin OC3B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.RW0WGM31Waveform Generation ModeCombined with the WGM33:2 bits found in the TCCR3B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.RW0WGM30Waveform Generation ModeCombined with the WGM33:2 bits found in the TCCR3B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.RW0TCCR3BTimer/Counter3 Control Register BNA$91io_flag.bmpYICNC3Input Capture 3 Noise CancelerWhen the ICNC3 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the ICP - input capture pin - as specified. When the ICNC3 bit is set (one), four successive samples are measures on the ICP - input capture pin, and all samples must be high/low according to the input capture trigger specification in the ICES3 bit. The actual sampling frequency is XTAL clock frequency.RW0ICES3Input Capture 3 Edge SelectWhile the ICES3 bit is cleared (zero), the Timer/Counter3 contents are transferred to the Input Capture Register - ICR3 - on the falling edge of the input capture pin - ICP. While the ICES3 bit is set (one), the Timer/Counter3 contents are transferred to the Input Capture Register - ICR3 - on the rising edge of the input capture pin - ICP.RW0WGM33Waveform Generation ModeCombined with the WGM33:2 bits found in the TCCR3B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.RW0WGM32Waveform Generation ModeCombined with the WGM33:2 bits found in the TCCR3B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.RW0CS32Prescaler source of Timer/Counter 3Select Prescaling Clock Source of Timer/Counter3. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T3, falling edge. (1:1:1) = External Pin 1, rising edge.RW0CS31Prescaler source of Timer/Counter 3Select Prescaling Clock Source of Timer/Counter3. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T3, falling edge. (1:1:1) = External Pin 1, rising edge.RW0CS30Prescaler source of Timer/Counter 3Select Prescaling Clock Source of Timer/Counter3. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.RW0TCCR3CTimer/Counter 3 Control Register CNA$92io_flag.bmpYFOC3AForce Output Compare 3AWriting a logical one to this bit, forces a change in the compare match output pin PD5 according to the values already set in COM3A1 and COM3A0.If the COM3A1 and COM3A0 bits are written in the same cycle as FOC3A,the new settings will not take effect until next compare match or forced compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM3A1 and COM3A0 happens as if a Compare Match had occurred, but no interrupt is generated and it will not clear the timer even if CTC3 in TCCR3B is set. The corresponding I/O pin must be set as an output pin for the FOC3A bit to have effect on the pin. The FOC3A bit will always be read as zero. The setting of the FOC3A bit has no effect in PWM mRW0FOC3BForce Output Compare 3BWriting a logical one to this bit, forces a change in the compare match output pin PD4 according to the values already set in COM3B1 and COM3B0.If the COM3B1 and COM3B0 bits are written in the same cycle as FOC3B,the new settings will not take effect until next compare match or forced compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM3B1 and COM3B0 happens as if a Compare Match had occurred, but no interrupt is generated. The corresponding I/O pin must be set as an output pin for the FOC3B bit to have effect on the pin. The FOC3B bit will always be read as zero. The setting of the FOC3B bit has no effect in PWM moRW0FOC3CForce Output Compare 3CWriting a logical one to this bit, forces a change in the compare match output pin PD4 according to the values already set in COM3B1 and COM3B0.If the COM3B1 and COM3B0 bits are written in the same cycle as FOC3B,the new settings will not take effect until next compare match or forced compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM3B1 and COM3B0 happens as if a Compare Match had occurred, but no interrupt is generated. The corresponding I/O pin must be set as an output pin for the FOC3B bit to have effect on the pin. The FOC3B bit will always be read as zero. The setting of the FOC3B bit has no effect in PWM moRW0TCNT3HTimer/Counter3 High ByteThis 16-bit register contains the prescaled value of the 16-bit Timer/Counter3. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR3A, OCR3B and ICR3. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt rouNA$95io_timer.bmpNTCNT3H7Timer/Counter3 High Byte bit 7RW0TCNT3H6Timer/Counter3 High Byte bit 6RW0TCNT3H5Timer/Counter3 High Byte bit 5RW0TCNT3H4Timer/Counter3 High Byte bit 4RW0TCNT3H3Timer/Counter3 High Byte bit 3RW0TCNT3H2Timer/Counter3 High Byte bit 2RW0TCNT3H1Timer/Counter3 High Byte bit 1RW0TCNT3H0Timer/Counter3 High Byte bit 0RW0TCNT3LTimer/Counter3 Low ByteThis 16-bit register contains the prescaled value of the 16-bit Timer/Counter3. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR3A, OCR3B and ICR3. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interruNA$94io_timer.bmpNTCNT3L7Timer/Counter3 Low Byte bit 7RW0TCNT3L6Timer/Counter3 Low Byte bit 6RW0TCNT3L5Timer/Counter3 Low Byte bit 5RW0TCNT3L4Timer/Counter3 Low Byte bit 4RW0TCNT3L3Timer/Counter3 Low Byte bit 3RW0TCNT3L2Timer/Counter3 Low Byte bit 2RW0TCNT3L1Timer/Counter3 Low Byte bit 1RW0TCNT3L0Timer/Counter3 Low Byte bit 0RW0OCR3AHTimer/Counter3 Outbut Compare Register A High ByteThe output compare registers are 16-bit read/write registers. The Timer/Counter3 Output Compare Registers contain the data to be continuously compared with Timer/Counter3. Actions on compare matches are specified in the Timer/Counter3 Control and Status register.A compare match does only occur if Timer/Counter3 counts to the OCR value. A software write that sets TCNT3 and OCR3A or OCR3B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR3A and OCR3B - are 16-bit registers, a temporary register TEMP is used when OCR3A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR3AH or OCR3BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR3AL or OCR3BL, the TEMP register is simultaneously written to OCR3AH or OCR3BH. Consequently, the high byte OCR3AH or OCR3BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT3, and ICR3. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrNA$99io_timer.bmpNOCR3AH7Timer/Counter3 Outbut Compare Register High Byte bit 7RW0OCR3AH6Timer/Counter3 Outbut Compare Register High Byte bit 6RW0OCR3AH5Timer/Counter3 Outbut Compare Register High Byte bit 5RW0OCR3AH4Timer/Counter3 Outbut Compare Register High Byte bit 4RW0OCR3AH3Timer/Counter3 Outbut Compare Register High Byte bit 3RW0OCR3AH2Timer/Counter3 Outbut Compare Register High Byte bit 2RW0OCR3AH1Timer/Counter3 Outbut Compare Register High Byte bit 1RW0OCR3AH0Timer/Counter3 Outbut Compare Register High Byte bit 0RW0OCR3ALTimer/Counter3 Outbut Compare Register A Low ByteThe output compare registers are 16-bit read/write registers. The Timer/Counter3 Output Compare Registers contain the data to be continuously compared with Timer/Counter3. Actions on compare matches are specified in the Timer/Counter3 Control and Status register.A compare match does only occur if Timer/Counter3 counts to the OCR value. A software write that sets TCNT3 and OCR3A or OCR3B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR3A and OCR3B - are 16-bit registers, a temporary register TEMP is used when OCR3A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR3AH or OCR3BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR3AL or OCR3BL, the TEMP register is simultaneously written to OCR3AH or OCR3BH. Consequently, the high byte OCR3AH or OCR3BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT3, and ICR3. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interruNA$98io_timer.bmpNOCR3AL7Timer/Counter3 Outbut Compare Register Low Byte Bit 7RW0OCR3AL6Timer/Counter3 Outbut Compare Register Low Byte Bit 6RW0OCR3AL5Timer/Counter3 Outbut Compare Register Low Byte Bit 5RW0OCR3AL4Timer/Counter3 Outbut Compare Register Low Byte Bit 4RW0OCR3AL3Timer/Counter3 Outbut Compare Register Low Byte Bit 3RW0OCR3AL2Timer/Counter3 Outbut Compare Register Low Byte Bit 2RW0OCR3AL1Timer/Counter3 Outbut Compare Register Low Byte Bit 1RW0OCR3AL0Timer/Counter3 Outbut Compare Register Low Byte Bit 0RW0OCR3BHTimer/Counter3 Output Compare Register B High ByteThe output compare registers are 16-bit read/write registers. The Timer/Counter3 Output Compare Registers contain the data to be continuously compared with Timer/Counter3. Actions on compare matches are specified in the Timer/Counter3 Control and Status register.A compare match does only occur if Timer/Counter3 counts to the OCR value. A software write that sets TCNT3 and OCR3A or OCR3B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR3A and OCR3B - are 16-bit registers, a temporary register TEMP is used when OCR3A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR3AH or OCR3BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR3AL or OCR3BL, the TEMP register is simultaneously written to OCR3AH or OCR3BH. Consequently, the high byte OCR3AH or OCR3BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT3, and ICR3. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt rNA$9Bio_timer.bmpNOCR3BH7Timer/Counter3 Output Compare Register High Byte bit 7RW0OCR3BH6Timer/Counter3 Output Compare Register High Byte bit 6RW0OCR3BH5Timer/Counter3 Output Compare Register High Byte bit 5RW0OCR3BH4Timer/Counter3 Output Compare Register High Byte bit 4RW0OCR3BH3Timer/Counter3 Output Compare Register High Byte bit 3RW0OCR3BH2Timer/Counter3 Output Compare Register High Byte bit 2RW0OCR3BH1Timer/Counter3 Output Compare Register High Byte bit 1RW0OCR3BH0Timer/Counter3 Output Compare Register High Byte bit 0RW0OCR3BLTimer/Counter3 Output Compare Register B Low ByteThe output compare registers are 16-bit read/write registers. The Timer/Counter3 Output Compare Registers contain the data to be continuously compared with Timer/Counter3. Actions on compare matches are specified in the Timer/Counter3 Control and Status register.A compare match does only occur if Timer/Counter3 counts to the OCR value. A software write that sets TCNT3 and OCR3A or OCR3B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR3A and OCR3B - are 16-bit registers, a temporary register TEMP is used when OCR3A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR3AH or OCR3BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR3AL or OCR3BL, the TEMP register is simultaneously written to OCR3AH or OCR3BH. Consequently, the high byte OCR3AH or OCR3BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT3, and ICR3. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt routNA$9Aio_timer.bmpNOCR3BL7Timer/Counter3 Output Compare Register Low Byte bit 7R0OCR3BL6Timer/Counter3 Output Compare Register Low Byte bit 6RW0OCR3BL5Timer/Counter3 Output Compare Register Low Byte bit 5RW0OCR3BL4Timer/Counter3 Output Compare Register Low Byte bit 4RW0OCR3BL3Timer/Counter3 Output Compare Register Low Byte bit 3RW0OCR3BL2Timer/Counter3 Output Compare Register Low Byte bit 2RW0OCR3BL1Timer/Counter3 Output Compare Register Low Byte bit 1RW0OCR3BL0Timer/Counter3 Output Compare Register Low Byte bit 0RW0OCR3CHTimer/Counter3 Output Compare Register B High ByteThe output compare registers are 16-bit read/write registers. The Timer/Counter3 Output Compare Registers contain the data to be continuously compared with Timer/Counter3. Actions on compare matches are specified in the Timer/Counter3 Control and Status register.A compare match does only occur if Timer/Counter3 counts to the OCR value. A software write that sets TCNT3 and OCR3A or OCR3B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR3A and OCR3B - are 16-bit registers, a temporary register TEMP is used when OCR3A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR3AH or OCR3BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR3AL or OCR3BL, the TEMP register is simultaneously written to OCR3AH or OCR3BH. Consequently, the high byte OCR3AH or OCR3BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT3, and ICR3. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt rNA$9Dio_timer.bmpNOCR3CH7Timer/Counter3 Output Compare Register High Byte bit 7RW0OCR3CH6Timer/Counter3 Output Compare Register High Byte bit 6RW0OCR3CH5Timer/Counter3 Output Compare Register High Byte bit 5RW0OCR3CH4Timer/Counter3 Output Compare Register High Byte bit 4RW0OCR3CH3Timer/Counter3 Output Compare Register High Byte bit 3RW0OCR3CH2Timer/Counter3 Output Compare Register High Byte bit 2RW0OCR3CH1Timer/Counter3 Output Compare Register High Byte bit 1RW0OCR3CH0Timer/Counter3 Output Compare Register High Byte bit 0RW0OCR3CLTimer/Counter3 Output Compare Register B Low ByteThe output compare registers are 16-bit read/write registers. The Timer/Counter3 Output Compare Registers contain the data to be continuously compared with Timer/Counter3. Actions on compare matches are specified in the Timer/Counter3 Control and Status register.A compare match does only occur if Timer/Counter3 counts to the OCR value. A software write that sets TCNT3 and OCR3A or OCR3B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR3A and OCR3B - are 16-bit registers, a temporary register TEMP is used when OCR3A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR3AH or OCR3BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR3AL or OCR3BL, the TEMP register is simultaneously written to OCR3AH or OCR3BH. Consequently, the high byte OCR3AH or OCR3BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT3, and ICR3. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt routNA$9Cio_timer.bmpNOCR3CL7Timer/Counter3 Output Compare Register Low Byte bit 7R0OCR3CL6Timer/Counter3 Output Compare Register Low Byte bit 6RW0OCR3CL5Timer/Counter3 Output Compare Register Low Byte bit 5RW0OCR3CL4Timer/Counter3 Output Compare Register Low Byte bit 4RW0OCR3CL3Timer/Counter3 Output Compare Register Low Byte bit 3RW0OCR3CL2Timer/Counter3 Output Compare Register Low Byte bit 2RW0OCR3CL1Timer/Counter3 Output Compare Register Low Byte bit 1RW0OCR3CL0Timer/Counter3 Output Compare Register Low Byte bit 0RW0ICR3HTimer/Counter3 Input Capture Register High ByteThe input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES3) of the signal at the input capture pin -ICP - is detected, the current value of the Timer/Counter3 is transferred to the Input Capture Register - ICR3. At the same time, the input capture flag - ICF3 - is set (one). Since the Input Capture Register - ICR3 - is a 16-bit register, a temporary register TEMP is used when ICR3 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR3L, the data is sent to the CPU and the data of the high byte ICR3H is placed in the TEMP register. When the CPU reads the data in the high byte ICR3H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR3L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT3, OCR3A and OCR3B. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interruptNA$97io_timer.bmpNICR3H7Timer/Counter3 Input Capture Register High Byte bit 7RW0ICR3H6Timer/Counter3 Input Capture Register High Byte bit 6R0ICR3H5Timer/Counter3 Input Capture Register High Byte bit 5R0ICR3H4Timer/Counter3 Input Capture Register High Byte bit 4R0ICR3H3Timer/Counter3 Input Capture Register High Byte bit 3R0ICR3H2Timer/Counter3 Input Capture Register High Byte bit 2R0ICR3H1Timer/Counter3 Input Capture Register High Byte bit 1R0ICR3H0Timer/Counter3 Input Capture Register High Byte bit 0R0ICR3LTimer/Counter3 Input Capture Register Low ByteThe input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES3) of the signal at the input capture pin -ICP - is detected, the current value of the Timer/Counter3 is transferred to the Input Capture Register - ICR3. At the same time, the input capture flag - ICF3 - is set (one). Since the Input Capture Register - ICR3 - is a 16-bit register, a temporary register TEMP is used when ICR3 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR3L, the data is sent to the CPU and the data of the high byte ICR3H is placed in the TEMP register. When the CPU reads the data in the high byte ICR3H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR3L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT3, OCR3A and OCR3B. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interNA$96io_timer.bmpNICR3L7Timer/Counter3 Input Capture Register Low Byte bit 7R0ICR3L6Timer/Counter3 Input Capture Register Low Byte bit 6R0ICR3L5Timer/Counter3 Input Capture Register Low Byte bit 5R0ICR3L4Timer/Counter3 Input Capture Register Low Byte bit 4R0ICR3L3Timer/Counter3 Input Capture Register Low Byte bit 3R0ICR3L2Timer/Counter3 Input Capture Register Low Byte bit 2R0ICR3L1Timer/Counter3 Input Capture Register Low Byte bit 1R0ICR3L0Timer/Counter3 Input Capture Register Low Byte bit 0R0TIMSK3Timer/Counter3 Interrupt Mask RegisterNA$71io_flag.bmpYICIE3Timer/Counter3 Input Capture Interrupt EnableWhen the TICIE3 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter3 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on pin 31, ICP, i.e., when the ICF3 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.RW0OCIE3CTimer/Counter3 Output Compare C Match Interrupt EnableWhen the OCIE3C bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter3 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter3 occurs, i.e., when the OCF3B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.R0OCIE3BTimer/Counter3 Output Compare B Match Interrupt EnableWhen the OCIE3B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter3 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter3 occurs, i.e., when the OCF3B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.R0OCIE3ATimer/Counter3 Output Compare A Match Interrupt EnableWhen the OCIE3A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter3 CompareA Match interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a CompareA match in Timer/Counter3 occurs, i.e., when the OCF3A bit is set in the Timer/Counter Interrupt Flag Register - TIFR.RW0TOIE3Timer/Counter3 Overflow Interrupt EnableWhen the TOIE3 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter3 Overflow interrupt is enabled. The corresponding interrupt (at vector $006) is executed if an overflow in Timer/Counter3 occurs, i.e., when the TOV3 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.RW0TIFR3Timer/Counter3 Interrupt Flag register$18$38io_flag.bmpYICF3Input Capture Flag 3The ICF3 bit is set (one) to flag an input capture event, indicating that the Timer/Counter3 value has been transferred to the input capture register - ICR3. ICF3 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF3 is cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE3 (Timer/Counter3 Input Capture Interrupt Enable), and ICF3 are set (one), the Timer/Counter3 Capture Interrupt is executed. RW0OCF3COutput Compare Flag 3CThe OCF3C bit is set (one) when compare match occurs between the Timer/Counter3 and the data in OCR3B - Output Compare Register 3B. OCF3B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF3B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE3B (Timer/Counter3 Compare match InterruptB Enable), and the OCF3B are set (one), the Timer/Counter3 Compare B match Interrupt is executed.RW0OCF3BOutput Compare Flag 3BThe OCF3B bit is set (one) when compare match occurs between the Timer/Counter3 and the data in OCR3B - Output Compare Register 3B. OCF3B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF3B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE3B (Timer/Counter3 Compare match InterruptB Enable), and the OCF3B are set (one), the Timer/Counter3 Compare B match Interrupt is executed.RW0OCF3AOutput Compare Flag 3AThe OCF3A bit is set (one) when compare match occurs between the Timer/Counter3 and the data in OCR3A - Output Compare Register 3A. OCF3A is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF3A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE3A (Timer/Counter3 Compare match InterruptA Enable), and the OCF3A are set (one), the Timer/Counter3 Compare A match Interrupt is executed. RW0TOV3Timer/Counter3 Overflow FlagThe TOV3 is set (one) when an overflow occurs in Timer/Counter3. TOV3 is cleared by hardware when executing the cor-responding interrupt handling vector. Alternatively, TOV3 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE3 (Timer/Counter3 Overflow Interrupt Enable), and TOV3 are set (one), the Timer/Counter3 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter3 changes counting direction at $0000.RW0[TIMSK1:TIFR1:TCCR1A:TCCR1B:TCCR1C:TCNT1H:TCNT1L:OCR1AH:OCR1AL:OCR1BH:OCR1BL:ICR1H:ICR1L:OCR1CH:OCR1CL]
[TCNT1H:TCNT1L];[OCR1AH:OCR1AL];[OCR1BH:OCR1BL];[OCR1CH:OCR1CL];[ICR1H:ICR1L]
io_timer.bmpt16pwm1_14.xmlTCCR1ATimer/Counter1 Control Register ANA$80io_flag.bmpYCOM1A1Compare Output Mode 1A, bit 1The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA. This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10.RW0COM1A0Compare Output Mode 1A, bit 0The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA. This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10.RW0COM1B1Compare Output Mode 1B, bit 1The COM1B1 and COM1B0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.RW0COM1B0Compare Output Mode 1B, bit 0The COM1B1 and COM1B0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.RW0COM1C1Compare Output Mode 1C, bit 1The COM1C1 and COM1C0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.RW0COM1C0Compare Output Mode 1C, bit 0The COM1C1 and COM1C0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.RW0WGM11Waveform Generation ModeCombined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.RW0WGM10Waveform Generation ModeCombined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.RW0TCCR1BTimer/Counter1 Control Register BNA$81io_flag.bmpYICNC1Input Capture 1 Noise CancelerWhen the ICNC1 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the ICP - input capture pin - as specified. When the ICNC1 bit is set (one), four successive samples are measures on the ICP - input capture pin, and all samples must be high/low according to the input capture trigger specification in the ICES1 bit. The actual sampling frequency is XTAL clock frequency.RW0ICES1Input Capture 1 Edge SelectWhile the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the falling edge of the input capture pin - ICP. While the ICES1 bit is set (one), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the rising edge of the input capture pin - ICP.RW0WGM13Waveform Generation ModeCombined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.RW0WGM12Waveform Generation ModeCombined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.RW0CS12Prescaler source of Timer/Counter 1Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.RW0CS11Prescaler source of Timer/Counter 1Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.RW0CS10Prescaler source of Timer/Counter 1Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.RW0TCCR1CTimer/Counter 1 Control Register CNA$82io_flag.bmpYFOC1AForce Output Compare 1AWriting a logical one to this bit, forces a change in the compare match output pin PD5 according to the values already set in COM1A1 and COM1A0.If the COM1A1 and COM1A0 bits are written in the same cycle as FOC1A,the new settings will not take effect until next compare match or forced compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM1A1 and COM1A0 happens as if a Compare Match had occurred, but no interrupt is generated and it will not clear the timer even if CTC1 in TCCR1B is set. The corresponding I/O pin must be set as an output pin for the FOC1A bit to have effect on the pin. The FOC1A bit will always be read as zero. The setting of the FOC1A bit has no effect in PWM mRW0FOC1BForce Output Compare 1BWriting a logical one to this bit, forces a change in the compare match output pin PD4 according to the values already set in COM1B1 and COM1B0.If the COM1B1 and COM1B0 bits are written in the same cycle as FOC1B,the new settings will not take effect until next compare match or forced compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM1B1 and COM1B0 happens as if a Compare Match had occurred, but no interrupt is generated. The corresponding I/O pin must be set as an output pin for the FOC1B bit to have effect on the pin. The FOC1B bit will always be read as zero. The setting of the FOC1B bit has no effect in PWM moRW0FOC1CForce Output Compare 1CWriting a logical one to this bit, forces a change in the compare match output pin PD4 according to the values already set in COM1B1 and COM1B0.If the COM1B1 and COM1B0 bits are written in the same cycle as FOC1B,the new settings will not take effect until next compare match or forced compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM1B1 and COM1B0 happens as if a Compare Match had occurred, but no interrupt is generated. The corresponding I/O pin must be set as an output pin for the FOC1B bit to have effect on the pin. The FOC1B bit will always be read as zero. The setting of the FOC1B bit has no effect in PWM moRW0TCNT1HTimer/Counter1 High ByteThis 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR1A, OCR1B and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt rouNA$85io_timer.bmpNTCNT1H7Timer/Counter1 High Byte bit 7RW0TCNT1H6Timer/Counter1 High Byte bit 6RW0TCNT1H5Timer/Counter1 High Byte bit 5RW0TCNT1H4Timer/Counter1 High Byte bit 4RW0TCNT1H3Timer/Counter1 High Byte bit 3RW0TCNT1H2Timer/Counter1 High Byte bit 2RW0TCNT1H1Timer/Counter1 High Byte bit 1RW0TCNT1H0Timer/Counter1 High Byte bit 0RW0TCNT1LTimer/Counter1 Low ByteThis 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR1A, OCR1B and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interruNA$84io_timer.bmpNTCNT1L7Timer/Counter1 Low Byte bit 7RW0TCNT1L6Timer/Counter1 Low Byte bit 6RW0TCNT1L5Timer/Counter1 Low Byte bit 5RW0TCNT1L4Timer/Counter1 Low Byte bit 4RW0TCNT1L3Timer/Counter1 Low Byte bit 3RW0TCNT1L2Timer/Counter1 Low Byte bit 2RW0TCNT1L1Timer/Counter1 Low Byte bit 1RW0TCNT1L0Timer/Counter1 Low Byte bit 0RW0OCR1AHTimer/Counter1 Outbut Compare Register A High ByteThe output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrNA$89io_timer.bmpNOCR1AH7Timer/Counter1 Outbut Compare Register High Byte bit 7RW0OCR1AH6Timer/Counter1 Outbut Compare Register High Byte bit 6RW0OCR1AH5Timer/Counter1 Outbut Compare Register High Byte bit 5RW0OCR1AH4Timer/Counter1 Outbut Compare Register High Byte bit 4RW0OCR1AH3Timer/Counter1 Outbut Compare Register High Byte bit 3RW0OCR1AH2Timer/Counter1 Outbut Compare Register High Byte bit 2RW0OCR1AH1Timer/Counter1 Outbut Compare Register High Byte bit 1RW0OCR1AH0Timer/Counter1 Outbut Compare Register High Byte bit 0RW0OCR1ALTimer/Counter1 Outbut Compare Register A Low ByteThe output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interruNA$88io_timer.bmpNOCR1AL7Timer/Counter1 Outbut Compare Register Low Byte Bit 7RW0OCR1AL6Timer/Counter1 Outbut Compare Register Low Byte Bit 6RW0OCR1AL5Timer/Counter1 Outbut Compare Register Low Byte Bit 5RW0OCR1AL4Timer/Counter1 Outbut Compare Register Low Byte Bit 4RW0OCR1AL3Timer/Counter1 Outbut Compare Register Low Byte Bit 3RW0OCR1AL2Timer/Counter1 Outbut Compare Register Low Byte Bit 2RW0OCR1AL1Timer/Counter1 Outbut Compare Register Low Byte Bit 1RW0OCR1AL0Timer/Counter1 Outbut Compare Register Low Byte Bit 0RW0OCR1BHTimer/Counter1 Output Compare Register B High ByteThe output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt rNA$8Bio_timer.bmpNOCR1BH7Timer/Counter1 Output Compare Register High Byte bit 7RW0OCR1BH6Timer/Counter1 Output Compare Register High Byte bit 6RW0OCR1BH5Timer/Counter1 Output Compare Register High Byte bit 5RW0OCR1BH4Timer/Counter1 Output Compare Register High Byte bit 4RW0OCR1BH3Timer/Counter1 Output Compare Register High Byte bit 3RW0OCR1BH2Timer/Counter1 Output Compare Register High Byte bit 2RW0OCR1BH1Timer/Counter1 Output Compare Register High Byte bit 1RW0OCR1BH0Timer/Counter1 Output Compare Register High Byte bit 0RW0OCR1BLTimer/Counter1 Output Compare Register B Low ByteThe output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt routNA$8Aio_timer.bmpNOCR1BL7Timer/Counter1 Output Compare Register Low Byte bit 7R0OCR1BL6Timer/Counter1 Output Compare Register Low Byte bit 6RW0OCR1BL5Timer/Counter1 Output Compare Register Low Byte bit 5RW0OCR1BL4Timer/Counter1 Output Compare Register Low Byte bit 4RW0OCR1BL3Timer/Counter1 Output Compare Register Low Byte bit 3RW0OCR1BL2Timer/Counter1 Output Compare Register Low Byte bit 2RW0OCR1BL1Timer/Counter1 Output Compare Register Low Byte bit 1RW0OCR1BL0Timer/Counter1 Output Compare Register Low Byte bit 0RW0OCR1CHTimer/Counter1 Output Compare Register B High ByteThe output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt rNA$8Dio_timer.bmpNOCR1CH7Timer/Counter1 Output Compare Register High Byte bit 7RW0OCR1CH6Timer/Counter1 Output Compare Register High Byte bit 6RW0OCR1CH5Timer/Counter1 Output Compare Register High Byte bit 5RW0OCR1CH4Timer/Counter1 Output Compare Register High Byte bit 4RW0OCR1CH3Timer/Counter1 Output Compare Register High Byte bit 3RW0OCR1CH2Timer/Counter1 Output Compare Register High Byte bit 2RW0OCR1CH1Timer/Counter1 Output Compare Register High Byte bit 1RW0OCR1CH0Timer/Counter1 Output Compare Register High Byte bit 0RW0OCR1CLTimer/Counter1 Output Compare Register B Low ByteThe output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt routNA$8Cio_timer.bmpNOCR1CL7Timer/Counter1 Output Compare Register Low Byte bit 7R0OCR1CL6Timer/Counter1 Output Compare Register Low Byte bit 6RW0OCR1CL5Timer/Counter1 Output Compare Register Low Byte bit 5RW0OCR1CL4Timer/Counter1 Output Compare Register Low Byte bit 4RW0OCR1CL3Timer/Counter1 Output Compare Register Low Byte bit 3RW0OCR1CL2Timer/Counter1 Output Compare Register Low Byte bit 2RW0OCR1CL1Timer/Counter1 Output Compare Register Low Byte bit 1RW0OCR1CL0Timer/Counter1 Output Compare Register Low Byte bit 0RW0ICR1HTimer/Counter1 Input Capture Register High ByteThe input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES1) of the signal at the input capture pin -ICP - is detected, the current value of the Timer/Counter1 is transferred to the Input Capture Register - ICR1. At the same time, the input capture flag - ICF1 - is set (one). Since the Input Capture Register - ICR1 - is a 16-bit register, a temporary register TEMP is used when ICR1 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR1L, the data is sent to the CPU and the data of the high byte ICR1H is placed in the TEMP register. When the CPU reads the data in the high byte ICR1H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR1L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT1, OCR1A and OCR1B. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interruptNA$87io_timer.bmpNICR1H7Timer/Counter1 Input Capture Register High Byte bit 7RW0ICR1H6Timer/Counter1 Input Capture Register High Byte bit 6R0ICR1H5Timer/Counter1 Input Capture Register High Byte bit 5R0ICR1H4Timer/Counter1 Input Capture Register High Byte bit 4R0ICR1H3Timer/Counter1 Input Capture Register High Byte bit 3R0ICR1H2Timer/Counter1 Input Capture Register High Byte bit 2R0ICR1H1Timer/Counter1 Input Capture Register High Byte bit 1R0ICR1H0Timer/Counter1 Input Capture Register High Byte bit 0R0ICR1LTimer/Counter1 Input Capture Register Low ByteThe input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES1) of the signal at the input capture pin -ICP - is detected, the current value of the Timer/Counter1 is transferred to the Input Capture Register - ICR1. At the same time, the input capture flag - ICF1 - is set (one). Since the Input Capture Register - ICR1 - is a 16-bit register, a temporary register TEMP is used when ICR1 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR1L, the data is sent to the CPU and the data of the high byte ICR1H is placed in the TEMP register. When the CPU reads the data in the high byte ICR1H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR1L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT1, OCR1A and OCR1B. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interNA$86io_timer.bmpNICR1L7Timer/Counter1 Input Capture Register Low Byte bit 7R0ICR1L6Timer/Counter1 Input Capture Register Low Byte bit 6R0ICR1L5Timer/Counter1 Input Capture Register Low Byte bit 5R0ICR1L4Timer/Counter1 Input Capture Register Low Byte bit 4R0ICR1L3Timer/Counter1 Input Capture Register Low Byte bit 3R0ICR1L2Timer/Counter1 Input Capture Register Low Byte bit 2R0ICR1L1Timer/Counter1 Input Capture Register Low Byte bit 1R0ICR1L0Timer/Counter1 Input Capture Register Low Byte bit 0R0TIMSK1Timer/Counter1 Interrupt Mask RegisterNA$6Fio_flag.bmpYICIE1Timer/Counter1 Input Capture Interrupt EnableWhen the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on pin 31, ICP, i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.RW0OCIE1CTimer/Counter1 Output Compare C Match Interrupt EnableWhen the OCIE1C bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter1 occurs, i.e., when the OCF1B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.R0OCIE1BTimer/Counter1 Output Compare B Match Interrupt EnableWhen the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter1 occurs, i.e., when the OCF1B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.R0OCIE1ATimer/Counter1 Output Compare A Match Interrupt EnableWhen the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a CompareA match in Timer/Counter1 occurs, i.e., when the OCF1A bit is set in the Timer/Counter Interrupt Flag Register - TIFR.RW0TOIE1Timer/Counter1 Overflow Interrupt EnableWhen the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $006) is executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.RW0TIFR1Timer/Counter1 Interrupt Flag register$16$36io_flag.bmpYICF1Input Capture Flag 1The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to the input capture register - ICR1. ICF1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF1 is cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable), and ICF1 are set (one), the Timer/Counter1 Capture Interrupt is executed. RW0OCF1COutput Compare Flag 1CThe OCF1C bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1B - Output Compare Register 1B. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1B (Timer/Counter1 Compare match InterruptB Enable), and the OCF1B are set (one), the Timer/Counter1 Compare B match Interrupt is executed.RW0OCF1BOutput Compare Flag 1BThe OCF1B bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1B - Output Compare Register 1B. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1B (Timer/Counter1 Compare match InterruptB Enable), and the OCF1B are set (one), the Timer/Counter1 Compare B match Interrupt is executed.RW0OCF1AOutput Compare Flag 1AThe OCF1A bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare match InterruptA Enable), and the OCF1A are set (one), the Timer/Counter1 Compare A match Interrupt is executed. RW0TOV1Timer/Counter1 Overflow FlagThe TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the cor-responding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter1 changes counting direction at $0000.RW0[OCDR:MCUCR:MCUSR]io_com.bmp00JTAG Features: JTAG (IEEE std. 1149.1 compliant) Interface. Boundary-Scan Capabilities According to the IEEE std. 1149.1 (JTAG) Standard. Debugger Access to: – All Internal Peripheral Units – Internal and External RAM – The Internal Register File –Program Counter – EEPROM and Flash Memories. Extensive On-Chip Debug Support for Break Conditions, Including: –AVR Break Instruction – Break on Change of Program Memory Flow –Single Step Break –Program Memory Breakpoints on Single Address or Address Range – Data Memory Breakpoints on Single Address or Address Range. Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface. On-Chip Debugging Supported by AVR StuOCDROn-Chip Debug Related Register in I/O MemoryThe OCDR register provides a communication channel from the running program in the microcontroller to the debugger. The CPU can transfer a byte to the debugger by writing to this location. At the same time, an internal flag; I/O Debug Reg-ister Dirty - IDRD - is set to indicate to the debugger that the register has been written. When the CPU reads the OCDR reg-ister the 7 LSB will be from the OCDR register, while the MSB is the IDRD bit. The debugger clears the IDRD bit when it has read the information. In some AVR devices, this register is shared with a standard I/O location. In this case, the OCDR register can only be accessed if the OCDEN fuse is programmed, and the debugger enables access to the OCDR register. In all other cases, the standard I/O location is accessed. Refer to the debugger documentation for further information on how to use this registe$31$51io_com.bmpNOCDR7IDRDOn-Chip Debug Register Bit 7RW0OCDR6On-Chip Debug Register Bit 6RW0OCDR5On-Chip Debug Register Bit 5RW0OCDR4On-Chip Debug Register Bit 4RW0OCDR3On-Chip Debug Register Bit 3RW0OCDR2On-Chip Debug Register Bit 2RW0OCDR1On-Chip Debug Register Bit 1RW0OCDR0On-Chip Debug Register Bit 0RW0MCUCRMCU Control RegisterThe MCU Control Register contains control bits for general MCU functions.$35$55io_flag.bmpYJTDJTAG Interface DisableWhen this bit is written to zero, the JTAG interface is enabled if the JTAGEN fuse is programmed. If this bit is written to one, the JTAG interface is disabled. In order to avoid unintentional disabling or enabling of the JTAG interface, a timed sequence must be followed: The application software must write this to the desired value twice within four cycles to change the bit.RW0MCUSRMCU Status RegisterThe MCU Status Register provides information on which reset source caused an MCU reset.$34$54io_flag.bmpYJTRFJTAG Reset FlagThis bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET.This bit is reset by a Power-on reset,or by writing a logic zero to the flag. RW0[EICRA:EICRB:EIMSK:EIFR:PCICR:PCIFR:PCMSK2:PCMSK1:PCMSK0]
[PCMSK2:PCMSK1:PCMSK0]
io_ext.bmpThe external interrupts are triggered by the INT7:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT7:0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The external inter-rupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the Exter-nal Interrupt Control Registers - EICRA (INT3:0) and EICRB (INT7:4). When the external interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT7:4 requires the presence of an I/O clock, described in “Clock Systems and their Distribution” on page 29. Low level interrupts and the edge interrupt on INT3:0 are detected asynchronously. This implies that these inter-rupts can be used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode. Note that if a level triggered interrupt is used for wake-up from Power Down Mode, the changed level must be held for some time to wake up the MCU. This makes the MCU less sensitive to noise. The changed level is sampled twice by the watchdog oscillator clock. The period of the watchdog oscillator is 1 µs (nominal) at 5.0V and 25°C. The frequency of the watchdog oscillator is voltage dependent as shown in the Electrical Characteristics section. The MCU will wake up if the input has the required level during this sampling or if it is held until the end of the start-up time. The start-up time is defined by the SUT fuses as described in “Clock Systems and their Distribution” on page 29. If the level is sampled twice by the watchdog oscillator clock but disappears before the end of the start-up time, the MCU will still wake up, but no interrupt will be generated. The required level must be held long enough for the MCU to complete the wake up to trigger the level interruptEICRAExternal Interrupt Control Register AThis Register can not be reached in ATmega103 compatibility mode, but the initial value defines INT3:0 as low level inter-rupts,as in ATmega103. • Bits 7..0 - ISC31, ISC30 - ISC00, ISC00: External Interrupt 3-0 Sense Control bits The External Interrupts 3 - 0 are activated by the external pins INT3:0 if the SREG I-flag and the corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that activate the interrupts are defined in Table 47. Edges on INT3..INT0 are registered asynchronously. Pulses on INT3:0 pins wider than the minimum pulse width given in Table 48 will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an interrupt request as long as the pin is held low. When changing the ISCn bit, an interrupt can occur. Therefore, it is recommended to first disable INTn by clearing its Interrupt Enable bit in the EIMSK register. Then, the ISCn bit can be changed. Finally, the INTn interrupt flag should be cleared by writing a logical one to its Interrupt Flag bit (INTFn) in the EIFR register before the interrupt is re-enableNA$69io_flag.bmpYISC31External Interrupt Sense Control BitRW0ISC30External Interrupt Sense Control BitRW0ISC21External Interrupt Sense Control BitRW0ISC20External Interrupt Sense Control BitRW0ISC11External Interrupt Sense Control BitRW0ISC10External Interrupt Sense Control BitRW0ISC01External Interrupt Sense Control BitRW0ISC00External Interrupt Sense Control BitRW0EICRBExternal Interrupt Control Register BThe External Interrupts 7 - 4 are activated by the external pins INT7:4 if the SREG I-flag and the corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that activate the interrupts are defined in Table 49. The value on the INT7:4 pins are sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL divider is enabled. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an interrupt request as long as the pin is held lowNA$6Aio_flag.bmpYISC71External Interrupt 7-4 Sense Control BitRW0ISC70External Interrupt 7-4 Sense Control BitRW0ISC61External Interrupt 7-4 Sense Control BitRW0ISC60External Interrupt 7-4 Sense Control BitRW0ISC51External Interrupt 7-4 Sense Control BitRW0ISC50External Interrupt 7-4 Sense Control BitRW0ISC41External Interrupt 7-4 Sense Control BitRW0ISC40External Interrupt 7-4 Sense Control BitRW0EIMSKExternal Interrupt Mask RegisterWhen an INT7- INT4 bit is written to one and the I-bit in the Status Register (SREG) is set (one), the corresponding external pin interrupt is enabled. The Interrupt Sense Control bits in the External Interrupt Control Registers - EICRA and EICRB defines whether the external interrupt is activated on rising or falling edge or level sensed. Activity on any of these pins will trigger an interrupt request even if the pin is enabled as an output. This provides a way of generating a software interrupt. $1D$3Dio_flag.bmpYINT7External Interrupt Request 7 EnableRW0INT6External Interrupt Request 6 EnableRW0INT5External Interrupt Request 5 EnableRW0INT4External Interrupt Request 4 EnableRW0INT3External Interrupt Request 3 EnableRW0INT2External Interrupt Request 2 EnableRW0INT1External Interrupt Request 1 EnableRW0INT0External Interrupt Request 0 EnableRW0EIFRExternal Interrupt Flag RegisterWhen an event on the INT7 - INT0 pins triggers an interrupt request, the corresponding interrupt flag, INTF7 - INTF0 becomes set (one). If the I-bit in SREG and the corresponding interrupt enable bit, INT7 - INT0 in EIMSK, are set (one), the MCU will jump to the interrupt vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag is cleared by writing a logical one to it. Note that when entering some sleep modes with the INT3:0 interrupts disabled, the input buffers on these pin will be disabled. This may cause a logic change in internal signals which will set the INTF3:0 flags. See “Digital Input Enable and Sleep Modes” on page 54 for more informa$1C$3Cio_flag.bmpYINTF7External Interrupt Flag 7RW0INTF6External Interrupt Flag 6RW0INTF5External Interrupt Flag 5RW0INTF4External Interrupt Flag 4RW0INTF3External Interrupt Flag 3RW0INTF2External Interrupt Flag 2RW0INTF1External Interrupt Flag 1RW0INTF0External Interrupt Flag 0RW0PCMSK2Pin Change Mask Register 2Each PCINT23..16 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT15..8 is set and the PCIE1 bit in EIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT23..16 is cleared, pin change interrupt on the corresponding I/O pin is disabled.NA$6Dio_flag.bmpNPCINT23Pin Change Enable Mask 23RW0PCINT22Pin Change Enable Mask 22RW0PCINT21Pin Change Enable Mask 21RW0PCINT20Pin Change Enable Mask 20RW0PCINT19Pin Change Enable Mask 19RW0PCINT18Pin Change Enable Mask 18RW0PCINT17Pin Change Enable Mask 17RW0PCINT16Pin Change Enable Mask 16RW0PCMSK1Pin Change Mask Register 1Each PCINT15..8 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT15..8 is set and the PCIE1 bit in EIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT15..8 is cleared, pin change interrupt on the corresponding I/O pin is disabled.NA$6Cio_flag.bmpNPCINT15Pin Change Enable Mask 15RW0PCINT14Pin Change Enable Mask 14RW0PCINT13Pin Change Enable Mask 13RW0PCINT12Pin Change Enable Mask 12RW0PCINT11Pin Change Enable Mask 11RW0PCINT10Pin Change Enable Mask 10RW0PCINT9Pin Change Enable Mask 9RW0PCINT8Pin Change Enable Mask 8RW0PCMSK0Pin Change Mask Register 0Each PCINT bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is set and the PCIE0 bit in EIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is cleared, pin change interrupt on the corresponding I/O pin is disabled.NA$6Bio_flag.bmpNPCINT7Pin Change Enable Mask 7RW0PCINT6Pin Change Enable Mask 6RW0PCINT5Pin Change Enable Mask 5RW0PCINT4Pin Change Enable Mask 4RW0PCINT3Pin Change Enable Mask 3RW0PCINT2Pin Change Enable Mask 2RW0PCINT1Pin Change Enable Mask 1RW0PCINT0Pin Change Enable Mask 0RW0PCIFRPin Change Interrupt Flag Register$1B$3Bio_flag.bmpYPCIF2Pin Change Interrupt Flag 2When a logic change on any PCINT23..16 pin triggers an interrupt request, PCIF2 becomes set (one). If the I-bit in SREG and the PCIE2 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.RW0PCIF1Pin Change Interrupt Flag 1When a logic change on any PCINT14..8 pin triggers an interrupt request, PCIF1 becomes set (one). If the I-bit in SREG and the PCIE1 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.RW0PCIF0Pin Change Interrupt Flag 0When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0 becomes set (one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.RW0PCICRPin Change Interrupt Control RegisterNA$68io_flag.bmpYPCIE2Pin Change Interrupt Enable 2RW0PCIE1Pin Change Interrupt Enable 1RW0PCIE0Pin Change Interrupt Enable 0RW0[SREG:SPH:SPL:MCUCR:MCUSR:XMCRA:XMCRB:OSCCAL:CLKPR:SMCR:RAMPZ:EIND:GPIOR2:GPIOR1:GPIOR0:PRR1:PRR0]
[SPH:SPL]
io_cpu.bmpSREGStatus Register$3F$5Fio_sreg.bmpYIGlobal Interrupt EnableThe global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable bit is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts.RW0TBit Copy StorageThe bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction.RW0HHalf Carry FlagThe half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed information.RW0SSign BitThe S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruc-tion Set Description for detailed information.RW0VTwo's Complement Overflow FlagThe two’s complement overflow flag V supports two’s complement arithmetics. See the Instruction Set Description for detailed information.RW0NNegative FlagThe negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.RW0ZZero FlagThe zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.RW0CCarry FlagThe carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software.RW0SPHStack Pointer HighThe general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the AT90S4414/8515 supports up to 64 kB external SRAM, all 16-bits are used. The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or return from interrupt R$3E$5Eio_sph.bmpNSP15Stack pointer bit 15RW0SP14Stack pointer bit 14RW0SP13Stack pointer bit 13RW1SP12Stack pointer bit 12RW0SP11Stack pointer bit 11RW0SP10Stack pointer bit 10RW0SP9Stack pointer bit 9RW0SP8Stack pointer bit 8RW1SPLStack Pointer LowThe general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the AT90S4414/8515 supports up to 64 kB external SRAM, all 16-bits are used. The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or return from interrupt $3D$5Dio_sph.bmpNSP7Stack pointer bit 7RW1SP6Stack pointer bit 6RW1SP5Stack pointer bit 5RW1SP4Stack pointer bit 4RW1SP3Stack pointer bit 3RW1SP2Stack pointer bit 2RW1SP1Stack pointer bit 1RW1SP0Stack pointer bit 0RW1MCUCRMCU Control RegisterThe MCU Control Register contains control bits for general MCU functions.$35$55io_flag.bmpYJTDJTAG Interface DisableWhen this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is programmed.RW0PUDPull-up disableWhen this bit is written to one,the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn registers are configured to enable the pull-ups ({DDxn,PORTxn}=0b01). RW0IVSELInterrupt Vector SelectWhen the IVSEL bit is cleared (zero),the interrupt vectors are placed at the start of the Flash memory.When this bit is set (one),the interrupt vectors are moved to the beginning of the Boot Loader section of the flash.The actual address of the start of the boot flash section is determined by the BOOTSZ fuses. RW0IVCEInterrupt Vector Change EnableThe IVCE bit must be written to logic one to enable change of the IVSEL bit.IVCE is cleared by hardware four cycles after it is written or when IVSEL is written.Setting the IVCE bit will disable interrupts. RW0MCUSRMCU Status RegisterThe MCU Status Register provides information on which reset source caused an MCU reset.$34$54io_flag.bmpYJTRFJTAG Reset FlagThis bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on reset, or by writing a logic zero to the flag. • Bit 3 - WDRF: Watchdog Reset FlagR/W0WDRFWatchdog Reset FlagThis bit is set if a watchdog reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.R/W0BORFBrown-out Reset FlagThis bit is set if a brown-out reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.R/W0EXTRFExternal Reset FlagThis bit is set if an external reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.R/W0PORFPower-on reset flagThis bit is set if a power-on reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the reset flags to identify a reset condition, the user should read and then reset the MCUCSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags.R/W0XMCRAExternal Memory Control Register ANA$74io_cpu.bmpYSREExternal SRAM EnableWriting SRE to one enables the External Memory Interface.RW0SRL2Wait state page limitIt is possible to configure different wait-states for different external memory addresses.RW0SRL1Wait state page limitIt is possible to configure different wait-states for different external memory addresses.RW0SRL0Wait state page limitIt is possible to configure different wait-states for different external memory addresses.RW0SRW11Wait state select bit upper pageRW0SRW10Wait state select bit upper pageRW0SRW01Wait state select bit lower pageRW0SRW00Wait state select bit lower pageRW0XMCRBExternal Memory Control Register BNA$75io_cpu.bmpYXMBKExternal Memory Bus Keeper EnablePort C pins release command.RW0XMM2External Memory High MaskPort C pins released.RW0XMM1External Memory High MaskPort C pins released.RW0XMM0External Memory High MaskPort C pins released.RW0OSCCALOscillator Calibration ValueWriting the calibration byte to this address will trim the internal oscillator to remove process variations from the oscillator frequency. This is done automatically during chip reset. When OSCCAL is zero, the lowest available frequency is chosen. Writing non-zero values to this register will increase the frequency of the internal oscillator. Writing $FF to the register gives the highest available frequency. The calibrated oscillator is used to time EEPROM and Flash access. If EEPROM or Flash is written, do not calibrate to more than 10% above the nominal frequency. Otherwise, the EEPROM or Flash write may fail. Note that the Oscillator is intended for calibration to 1.0 MHz, 2.0 MHz, 4.0 MHz, or 8.0MHz. Tuning to other values is not guaranteed, as indicated in Table 14NA$66io_cpu.bmpNCAL7Oscillator Calibration Value Bit7R/W0CAL6Oscillator Calibration Value Bit6R/W0CAL5Oscillator Calibration Value Bit5R/W0CAL4Oscillator Calibration Value Bit4R/W0CAL3Oscillator Calibration Value Bit3R/W0CAL2Oscillator Calibration Value Bit2R/W0CAL1Oscillator Calibration Value Bit1R/W0CAL0Oscillator Calibration Value Bit0R/W0CLKPRNA$61io_cpu.bmpYCLKPCECLKPS3CLKPS2CLKPS1CLKPS0SMCRSleep Mode Control RegisterThe Sleep Mode Control Register contains control bits for power management.$33$53io_cpu.bmpYSM2Sleep Mode Select bit 2These bits select between the five available sleep modes.RW0SM1Sleep Mode Select bit 1These bits select between the five available sleep modes.RW0SM0Sleep Mode Select bit 0These bits select between the five available sleep modes.RW0SESleep EnableThe SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed.ToRW0EINDExtended Indirect Register$3C$5Cio_cpu.bmpNEIND0Bit 0For EICALL/EIJMP instructions.RW0RAMPZRAM Page Z Select Register$3B$5Bio_cpu.bmpNRAMPZ1RAM Page Z Select Register Bit 1The RAMPZ register is normally used to select which 64K RAM Page is accessed by the Z pointer.RW0RAMPZ0RAM Page Z Select Register Bit 0The RAMPZ register is normally used to select which 64K RAM Page is accessed by the Z pointer.RW0GPIOR2General Purpose IO Register 2The ATmega169 contains three General Purpose I/O Registers.These registers can be used for storing any information, and they are particularly useful for storing global variables and status flags.General Purpose I/O Registers within the address range $00 -$1F are directly bit-accessible using the SBI,CBI,SBIS,and SBIC instructions. $2B$4Bio_cpu.bmpYGPIOR27General Purpose IO Register 2 bit 7RW0GPIOR26General Purpose IO Register 2 bit 6RW0GPIOR25General Purpose IO Register 2 bit 5RW0GPIOR24General Purpose IO Register 2 bit 4RW0GPIOR23General Purpose IO Register 2 bit 3RW0GPIOR22General Purpose IO Register 2 bit 2RW0GPIOR21General Purpose IO Register 2 bit 1RW0GPIOR20General Purpose IO Register 2 bit 0RW0GPIOR1General Purpose IO Register 1The ATmega169 contains three General Purpose I/O Registers.These registers can be used for storing any information, and they are particularly useful for storing global variables and status flags.General Purpose I/O Registers within the address range $00 -$1F are directly bit-accessible using the SBI,CBI,SBIS,and SBIC instructions. $2A$4Aio_cpu.bmpYGPIOR17General Purpose IO Register 1 bit 7RW0GPIOR16General Purpose IO Register 1 bit 6RW0GPIOR15General Purpose IO Register 1 bit 5RW0GPIOR14General Purpose IO Register 1 bit 4RW0GPIOR13General Purpose IO Register 1 bit 3RW0GPIOR12General Purpose IO Register 1 bit 2RW0GPIOR11General Purpose IO Register 1 bit 1RW0GPIOR10General Purpose IO Register 1 bit 0RW0GPIOR0General Purpose IO Register 0The ATmega169 contains three General Purpose I/O Registers.These registers can be used for storing any information, and they are particularly useful for storing global variables and status flags.General Purpose I/O Registers within the address range $00 -$1F are directly bit-accessible using the SBI,CBI,SBIS,and SBIC instructions. $1E$3Eio_cpu.bmpYGPIOR07General Purpose IO Register 0 bit 7RW0GPIOR06General Purpose IO Register 0 bit 6RW0GPIOR05General Purpose IO Register 0 bit 5RW0GPIOR04General Purpose IO Register 0 bit 4RW0GPIOR03General Purpose IO Register 0 bit 3RW0GPIOR02General Purpose IO Register 0 bit 2RW0GPIOR01General Purpose IO Register 0 bit 1RW0GPIOR00General Purpose IO Register 0 bit 0RW0PRR1Power Reduction Register1The Power Reduction Register, PRR1, provides a method to stop the clock to individual peripherals to reduce power consumption.NA$65io_cpu.bmpYPRTIM5Power Reduction Timer/Counter5R/W0PRTIM4Power Reduction Timer/Counter4R/W0PRTIM3Power Reduction Timer/Counter3R/W0PRUSART3Power Reduction USART3R/W0PRUSART2Power Reduction USART2R/W0PRUSART1Power Reduction USART1R/W0PRR0Power Reduction Register0The Power Reduction Register, PRR, provides a method to stop the clock to individual peripherals to reduce power consumption.NA$64io_cpu.bmpYPRTWIPower Reduction TWIR/W0PRTIM2Power Reduction Timer/Counter2R/W0PRTIM0Power Reduction Timer/Counter0R/W0PRTIM1Power Reduction Timer/Counter1R/W0PRSPIPower Reduction Serial Peripheral InterfaceR/W0PRUSART0Power Reduction USARTR/W0PRADCPower Reduction ADCR/W0[ADMUX:ADCSRA:ADCSRB:ADCH:ADCL:DIDR0:DIDR2]((IF ADMUX.ADLAR = 1) LINK [ADCH(1:0):ADCL(7:0)]); (IF ADMUX.ADLAR = 0) LINK [ADCH(7:0):ADCL(7:6)]);io_analo.bmpAD Converter Feature list: 10-bit Resolution. 0.5 LSB Integral Non-Linearity. +-2 LSB Absolute Accuracy. TBD - 260 µs Conversion Time. Up to TBD kSPS at maximum resolution. 8 Multiplexed Single Ended Input Channels. 7 Differential input channels (TQFP package only). 2 Differential input channels with optional gain of 10x and 200x (TQFP package only). Optional left adjustment for ADC result readout. 0 - VCC ADC Input Voltage Range. Selectable 2.56 V ADC reference voltage. Free Running or Single Conversion Mode. Interrupt on ADC Conversion Complete. Sleep Mode NoADMUXThe ADC multiplexer Selection RegisterNA$7Cio_analo.bmpYREFS1Reference Selection Bit 1These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin.RW0REFS0Reference Selection Bit 0These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin.RW0ADLARLeft Adjust ResultThe ADLAR bit affects the presentation of the ADC conversion result in the ADC data register. If ADLAR is cleared, the result is right adjusted. If ADLAR is set, the result is left adjusted. Changing the ADLAR bit will affect the ADC data register immediately, regardless of any ongoing conversions. For a complete description of this bit, see “The ADC Data Register -ADCL and ADCH” on page 198. RW0MUX4Analog Channel and Gain Selection BitsThe value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).RW0MUX3Analog Channel and Gain Selection BitsThe value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).RW0MUX2Analog Channel and Gain Selection BitsThe value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).RW0MUX1Analog Channel and Gain Selection BitsThe value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).RW0MUX0Analog Channel and Gain Selection BitsThe value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).RW0ADCHADC Data Register High ByteWhen an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. The selected channel is differential if MUX4..0 are between ‘01000’ and ‘11101’, otherwise the selected channel is single ended. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8 bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUX4..0 bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adjuNA$79io_analo.bmpNADCH7ADC Data Register High Byte Bit 7RW0ADCH6ADC Data Register High Byte Bit 6RW0ADCH5ADC Data Register High Byte Bit 5RW0ADCH4ADC Data Register High Byte Bit 4RW0ADCH3ADC Data Register High Byte Bit 3RW0ADCH2ADC Data Register High Byte Bit 2RW0ADCH1ADC Data Register High Byte Bit 1RW0ADCH0ADC Data Register High Byte Bit 0RW0ADCLADC Data Register Low ByteWhen an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. The selected channel is differential if MUX4..0 are between ‘01000’ and ‘11101’, otherwise the selected channel is single ended. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8 bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUX4..0 bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adNA$78io_analo.bmpNADCL7ADC Data Register Low Byte Bit 7RW0ADCL6ADC Data Register Low Byte Bit 6RW0ADCL5ADC Data Register Low Byte Bit 5RW0ADCL4ADC Data Register Low Byte Bit 4RW0ADCL3ADC Data Register Low Byte Bit 3RW0ADCL2ADC Data Register Low Byte Bit 2RW0ADCL1ADC Data Register Low Byte Bit 1RW0ADCL0ADC Data Register Low Byte Bit 0RW0ADCSRAThe ADC Control and Status register ANA$7Aio_flag.bmpYADENADC EnableWriting a logical ‘1’ to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.RW0ADSCADC Start ConversionIn Single Conversion Mode, a logical ‘1’ must be written to this bit to start each conversion. In Free Running Mode, a logical ‘1’ must be written to this bit to start the first conversion. The first time ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, an extended conversion will result. This extended conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. When a dummy conversion precedes a real conversion, ADSC will stay high until the real conversion completes. Writing a 0 to this bit has no effectRW0ADATEADC Auto Trigger EnableWhen this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a conversion on a positive edge of the selected trigger signal. The trigger source is selected by setting the ADC Trigger Select bits, ADTS in ADCSRB.RW0ADIFADC Interrupt FlagThis bit is set (one) when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set (one). ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a read-modify-write on ADCSR, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used.RW0ADIEADC Interrupt EnableWhen this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Complete Interrupt is activated.RW0ADPS2ADC Prescaler Select BitsThese bits determine the division factor between the XTAL frequency and the input clock to the ADC.RW0ADPS1ADC Prescaler Select BitsThese bits determine the division factor between the XTAL frequency and the input clock to the ADC.RW0ADPS0ADC Prescaler Select BitsThese bits determine the division factor between the XTAL frequency and the input clock to the ADC.RW0ADCSRBThe ADC Control and Status register BNA$7Bio_flag.bmpYACMERW0MUX5Analog Channel and Gain Selection BitsThe value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).RW0ADTS2ADC Auto Trigger Source bit 2Please refer to table on page 240 in datasheet for trigger selection.RW0ADTS1ADC Auto Trigger Source bit 1Please refer to table on page 240 in datasheet for trigger selection.RW0ADTS0ADC Auto Trigger Source bit 0Please refer to table on page 240 in datasheet for trigger selection.RW0DIDR2Digital Input Disable RegisterWhen this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer.NA$7Dio_analo.bmpYADC15DRW0ADC14DRW0ADC13DRW0ADC12DRW0ADC11DRW0ADC10DRW0ADC9DRW0ADC8DRW0DIDR0Digital Input Disable RegisterWhen this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer.NA$7Eio_analo.bmpYADC7DRW0ADC6DRW0ADC5DRW0ADC4DRW0ADC3DRW0ADC2DRW0ADC1DRW0ADC0DRW0[SPMCSR]io_cpu.bmpAVRSimIOSPM.SimIOSPMThe Boot Loader Support provides a real Read While Write self-programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program. The Boot Loader program can use any available data interface and associated proto-col to read code and write (program) that code into the Flash memory, or read the code from the program memory. The program code within the Boot Loader section has the capability to write into the entire Flash, including the Boot Loader Memory. The Boot Loader can thus even modify itself, and it can also erase itself from the code if the feature is not needed anymore. The size of the Boot Loader Memory is configurable with fuses and the Boot Loader has two separate sets of Boot Lock Bits which can be set independently. This gives the user a unique flexibility to select different levels of protection. Boot Loader Features: Read While Write self-programming. Flexibl Boot Memory size. High security (separate Boot Lock bits for a flexible protection). Separate fuse to select reset vector Optimized page (1) size. Code efficient algorithm Efficient read-modify-write supporSPMCSRStore Program Memory Control RegisterThe Store Program Memory Control Register contains the control bits needed to control the Boot Loader operations.$37$57io_flag.bmpYSPMIESPM Interrupt EnableWhen the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN bit in the SPMCR register is cleared.RW0RWWSBRead While Write Section BusyWhen a self-programming (page erase or page write) operation to the RWW section is initiated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a self-programming operation is completed. Alternatively the RWWSB bit will auto-matically be cleared if a page load operation is initiated.R0SIGRDSignature Row ReadIf this bit is written to one at the same time as SPMEN, the next LPM instruction within three clock cycles will read a byte from the signature row into the destination register. see “Reading the Signature Row from Software” in the datasheet for details. An SPM instruction within four cycles after SIGRD and SPMEN are set will have no effect. This operation is reserved for future use and should not be used.RW0RWWSRERead While Write section read enableWhen programming (page erase or page write) to the RWW section, the RWW section is blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW section, the user software must wait until the programming is completed (SPMEN will be cleared). Then, if the RWWSRE bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles re-enables the RWW section. The RWW section cannot be re-enabled while Flash is busy with a page erase or a page write (SPMEN is set). If the RWWSRE bit is written while the Flash is being loaded, the Flash load operation will abort and the data loaded will be loRW0BLBSETBoot Lock Bit SetIf this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles sets Boot Lock bits, according to the data in R0. The data in R1 and the address in the Z pointer are ignored. The BLBSET bit will automatically be cleared upon completion of the lock bit set, or if no SPM instruction is executed within four clock cycles. An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCR register, will read either the Lock-bits or the Fuse bits (depending on Z0 in the Z pointer) into the destination register. See “Reading the Fuse and Lock Bits from Software” on page 235 for detailsRW0PGWRTPage WriteIf this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPM instruction is exe-cuted within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.RW0PGERSPage EraseIf this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page erase. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a page erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.RW0SPMENStore Program Memory EnableThis bit enables the SPM instruction for the next four clock cycles. If written to one together with either RWWSRE, BLB-SET, PGWRT or PGERS, the following SPM instruction will have a special meaning, see description above. If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z pointer. The LSB of the Z pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During page erase and page write, the SPMEN bit remain high until the operation is completed. Writing any other combination than “10001”, "01001", "00101", "00011" or "00001" in the lower five bits will have no effecRW0[UDR2:UCSR2A:UCSR2B:UCSR2C:UBRR2H:UBRR2L]
[UBRR2H:UBRR2L]
io_com.bmpThe Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. The main features are: • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • High Resolution Baud Rate Generator • Supports Serial Frames with 5, 6, 7, 8 or 9 Data Bits and 1 or 2 Stop Bits • Odd or Even Parity Generation and Parity Check Supported by Hardware • Data OverRun Detection • Framing Error Detection • Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter • Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete • Multi-processor Communication Mode • Double Speed Asynchronous CommunicaUDR2USART I/O Data RegisterThe UDR2 register is actually two physically separate registers sharing the same I/O address. When writing to the register, the USART Transmit Data register is written. When reading from UDR0, the USART Receive Data register is read.NA$D6io_com.bmpNUDR2-7USART I/O Data Register bit 7RW0UDR2-6USART I/O Data Register bit 6RW0UDR2-5USART I/O Data Register bit 5RW0UDR2-4USART I/O Data Register bit 4RW0UDR2-3USART I/O Data Register bit 3RW0UDR2-2USART I/O Data Register bit 2RW0UDR2-1USART I/O Data Register bit 1RW0UDR2-0USART I/O Data Register bit 0RW0UCSR2AUSART Control and Status Register ANA$D0io_flag.bmpYRXC2USART Receive CompleteThis bit is set (one) when a received character is transferred from the Receiver Shift register to UDR0. The bit is set regard-less of any detected framing errors. When the RXCIE bit in UCR is set, the USART Receive Complete interrupt will be executed when RXC is set(one). RXC is cleared by reading UDR0. When interrupt-driven data reception is used, the USART Receive Complete Interrupt routine must read UDRin order to clear RXC, otherwise a new interrupt will occur once the interrupt routine terminates.R0TXC2USART Transmitt CompleteThis bit is set (one) when the entire character (including the stop bit) in the Transmit Shift register has been shifted out and no new data has been written to UDR0. This flag is especially useful in half-duplex communications interfaces, where a transmitting application must enter receive mode and free the communications bus immediately after completing the transmission. When the TXCIE bit in UCR is set, setting of TXC causes the USART Transmit Complete interrupt to be executed. TXC is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the TXC bit is cleared (zero) by writing a logical one to the bRW0UDRE2USART Data Register EmptyThis bit is set (one) when a character written to UDRis transferred to the Transmit shift register. Setting of this bit indicates that the transmitter is ready to receive a new character for transmission. When the UDR0IE bit in UCR is set, the USART Transmit Complete interrupt to be executed as long as UDR0E is set. UDR0E is cleared by writing UDR0. When interrupt-driven data transmittal is used, the USART Data Register Empty Interrupt routine must write UDRin order to clear UDR0E, otherwise a new interrupt will occur once the interrupt routine terminates. UDR0E is set (one) during reset to indicate that the transmitter is reR1FE2Framing ErrorThis bit is set if a Framing Error condition is detected, i.e. when the stop bit of an incoming character is zero. The FE bit is cleared when the stop bit of received data is one.R0DOR2Data overRunThis bit is set if an Overrun condition is detected, i.e. when a character already present in the UDRregister is not read before the next character has been shifted into the Receiver Shift register. The OR bit is buffered, which means that it will be set once the valid data still in UDR0E is read. The OR bit is cleared (zero) when data is received and transferred to UDR0. R0UPE2Parity ErrorThis bit is set if the next character in the receive buffer had a Parity Error when received and the parity checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer (UDR0) is read. Always set this bit to zero when writing to UCSR0A.R0U2X2Double the USART transmission speedThis bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation. Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous communication.RW0MPCM2Multi-processor Communication ModeThis bit enables the Multi-processor Communication Mode. When the MPCM bit is written to one, all the incoming frames received by the USART receiver that do not contain address information will be ignored. The transmitter is unaffected by the MPCM setting. For more detailed information see “Multi-processor Communication Mode” on page 152.RW0UCSR2BUSART Control and Status Register BNA$D1io_flag.bmpYRXCIE2RX Complete Interrupt EnableWriting this bit to one enables interrupt on the RXC flag. A USART Receive Complete interrupt will be generated only if the RXCIE bit is written to one, the global interrupt flag in SREG is written to one and the RXC bit in UCSR0A is set.RW0TXCIE2TX Complete Interrupt EnableWriting this bit to one enables interrupt on the TXC flag. A USART Transmit Complete interrupt will be generated only if the TXCIE bit is written to one, the global interrupt flag in SREG is written to one and the TXC bit in UCSR0A is set.RW0UDRIE2USART Data register Empty Interrupt EnableWriting this bit to one enables interrupt on the UDR0E flag. A Data Register Empty interrupt will be generated only if the UDR0IE bit is written to one, the global interrupt flag in SREG is written to one and the UDR0E bit in UCSR0A is set.RW1RXEN2Receiver EnableWriting this bit to one enables the USART receiver. The receiver will override normal port operation for the RxD pin when enabled. Disabling the receiver will flush the receive buffer invalidating the FE, DOR and PE flags.RW0TXEN2Transmitter EnableWriting this bit to one enables the USART transmitter. The transmitter will override normal port operation for the TxD pin when enabled. The disabling of the transmitter (writing TXEN to zero) will not become effective until ongoing and pending transmissions are completed, i.e. when the transmit shift register and transmit buffer register does not contain data to be transmitted. When disabled, the transmitter will no longer override the TxD port.RW0UCSZ22Character SizeThe UCSZ2 bits combined with the UCSZ1:0 bit in UCSR0C sets the number of data bits (character size) in a frame the receiver and transmitter use.RW0RXB82Receive Data Bit 8RXB8 is the 9th data bit of the received character when operating with serial frames with 9 data bits. Must be read before reading the low bits from UDR0.R0TXB82Transmit Data Bit 8TXB8 is the 9th data bit in the character to be transmitted when operating with serial frames with 9 data bits. Must be writ-ten before writing the low bits to UDR0.W0UCSR2CUSART Control and Status Register CNA$D2io_flag.bmpYUMSEL21USART Mode SelectRW0UMSEL20USART Mode SelectRW0UPM21Parity Mode Bit 1This bit enable and set type of parity generation and check. If enabled, the transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value for the incoming data and compare it to the UPM0 setting. If a mismatch is detected, the PE flag in UCSR0A will be set.RW0UPM20Parity Mode Bit 0This bit enable and set type of parity generation and check. If enabled, the transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value for the incoming data and compare it to the UPM0 setting. If a mismatch is detected, the PE flag in UCSR0A will be set.RW0USBS2Stop Bit Select0: 1-bit. 1: 2-bit.RW0UCSZ21Character SizeCharacter Size: 0 0 0 = 5-bit. 0 0 1 = 6-bit. 0 1 0 = 7 bit. 0 1 1 = 8-bit. 1 1 1 = 9 bit.RW1UCSZ20Character SizeCharacter Size: 0 0 0 = 5-bit. 0 0 1 = 6-bit. 0 1 0 = 7 bit. 0 1 1 = 8-bit. 1 1 1 = 9 bit.RW1UCPOL2Clock PolarityThis bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOL bit sets the relationship between data output change and data input sample, and the synchronous clock (XCK).RW0UBRR2HUSART Baud Rate Register High ByteThis is a 12-bit register which contains the USART baud rate. The UBRR0H contains the 4 most significant bits, and the UBRR0L contains the 8 least significant bits of the USART baud rate. Ongoing transmissions by the transmitter and receiver will be corrupted if the baud rate is changed. Writing UBRR0L will trigger an immediate update of the baud rate prescaler.NA$D5io_com.bmpNUBRR11USART Baud Rate Register bit 11RW0UBRR10USART Baud Rate Register bit 10RW0UBRR9USART Baud Rate Register bit 9RW0UBRR8USART Baud Rate Register bit 8RW0UBRR2LUSART Baud Rate Register Low ByteThis is a 12-bit register which contains the USART baud rate. The UBRR0H contains the 4 most significant bits, and the UBRR0L contains the 8 least significant bits of the USART baud rate. Ongoing transmissions by the transmitter and receiver will be corrupted if the baud rate is changed. Writing UBRR0L will trigger an immediate update of the baud rate prescaler.NA$D4io_com.bmpNUBRR7USART Baud Rate Register bit 7RW0UBRR6USART Baud Rate Register bit 6RW0UBRR5USART Baud Rate Register bit 5RW0UBRR4USART Baud Rate Register bit 4RW0UBRR3USART Baud Rate Register bit 3RW0UBRR2USART Baud Rate Register bit 2RW0UBRR1USART Baud Rate Register bit 1RW0UBRR0USART Baud Rate Register bit 0RW0[UDR3:UCSR3A:UCSR3B:UCSR3C:UBRR3H:UBRR3L]
[UBRR3H:UBRR3L]
io_com.bmpThe Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. The main features are: • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • High Resolution Baud Rate Generator • Supports Serial Frames with 5, 6, 7, 8 or 9 Data Bits and 1 or 2 Stop Bits • Odd or Even Parity Generation and Parity Check Supported by Hardware • Data OverRun Detection • Framing Error Detection • Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter • Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete • Multi-processor Communication Mode • Double Speed Asynchronous CommunicaUDR3USART I/O Data RegisterThe UDR3 register is actually two physically separate registers sharing the same I/O address. When writing to the register, the USART Transmit Data register is written. When reading from UDR0, the USART Receive Data register is read.NA$136io_com.bmpNUDR3-7USART I/O Data Register bit 7RW0UDR3-6USART I/O Data Register bit 6RW0UDR3-5USART I/O Data Register bit 5RW0UDR3-4USART I/O Data Register bit 4RW0UDR3-3USART I/O Data Register bit 3RW0UDR3-2USART I/O Data Register bit 2RW0UDR3-1USART I/O Data Register bit 1RW0UDR3-0USART I/O Data Register bit 0RW0UCSR3AUSART Control and Status Register ANA$130io_flag.bmpYRXC3USART Receive CompleteThis bit is set (one) when a received character is transferred from the Receiver Shift register to UDR0. The bit is set regard-less of any detected framing errors. When the RXCIE bit in UCR is set, the USART Receive Complete interrupt will be executed when RXC is set(one). RXC is cleared by reading UDR0. When interrupt-driven data reception is used, the USART Receive Complete Interrupt routine must read UDRin order to clear RXC, otherwise a new interrupt will occur once the interrupt routine terminates.R0TXC3USART Transmitt CompleteThis bit is set (one) when the entire character (including the stop bit) in the Transmit Shift register has been shifted out and no new data has been written to UDR0. This flag is especially useful in half-duplex communications interfaces, where a transmitting application must enter receive mode and free the communications bus immediately after completing the transmission. When the TXCIE bit in UCR is set, setting of TXC causes the USART Transmit Complete interrupt to be executed. TXC is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the TXC bit is cleared (zero) by writing a logical one to the bRW0UDRE3USART Data Register EmptyThis bit is set (one) when a character written to UDRis transferred to the Transmit shift register. Setting of this bit indicates that the transmitter is ready to receive a new character for transmission. When the UDR0IE bit in UCR is set, the USART Transmit Complete interrupt to be executed as long as UDR0E is set. UDR0E is cleared by writing UDR0. When interrupt-driven data transmittal is used, the USART Data Register Empty Interrupt routine must write UDRin order to clear UDR0E, otherwise a new interrupt will occur once the interrupt routine terminates. UDR0E is set (one) during reset to indicate that the transmitter is reR1FE3Framing ErrorThis bit is set if a Framing Error condition is detected, i.e. when the stop bit of an incoming character is zero. The FE bit is cleared when the stop bit of received data is one.R0DOR3Data overRunThis bit is set if an Overrun condition is detected, i.e. when a character already present in the UDRregister is not read before the next character has been shifted into the Receiver Shift register. The OR bit is buffered, which means that it will be set once the valid data still in UDR0E is read. The OR bit is cleared (zero) when data is received and transferred to UDR0. R0UPE3Parity ErrorThis bit is set if the next character in the receive buffer had a Parity Error when received and the parity checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer (UDR0) is read. Always set this bit to zero when writing to UCSR0A.R0U2X3Double the USART transmission speedThis bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation. Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous communication.RW0MPCM3Multi-processor Communication ModeThis bit enables the Multi-processor Communication Mode. When the MPCM bit is written to one, all the incoming frames received by the USART receiver that do not contain address information will be ignored. The transmitter is unaffected by the MPCM setting. For more detailed information see “Multi-processor Communication Mode” on page 152.RW0UCSR3BUSART Control and Status Register BNA$131io_flag.bmpYRXCIE3RX Complete Interrupt EnableWriting this bit to one enables interrupt on the RXC flag. A USART Receive Complete interrupt will be generated only if the RXCIE bit is written to one, the global interrupt flag in SREG is written to one and the RXC bit in UCSR0A is set.RW0TXCIE3TX Complete Interrupt EnableWriting this bit to one enables interrupt on the TXC flag. A USART Transmit Complete interrupt will be generated only if the TXCIE bit is written to one, the global interrupt flag in SREG is written to one and the TXC bit in UCSR0A is set.RW0UDRIE3USART Data register Empty Interrupt EnableWriting this bit to one enables interrupt on the UDR0E flag. A Data Register Empty interrupt will be generated only if the UDR0IE bit is written to one, the global interrupt flag in SREG is written to one and the UDR0E bit in UCSR0A is set.RW1RXEN3Receiver EnableWriting this bit to one enables the USART receiver. The receiver will override normal port operation for the RxD pin when enabled. Disabling the receiver will flush the receive buffer invalidating the FE, DOR and PE flags.RW0TXEN3Transmitter EnableWriting this bit to one enables the USART transmitter. The transmitter will override normal port operation for the TxD pin when enabled. The disabling of the transmitter (writing TXEN to zero) will not become effective until ongoing and pending transmissions are completed, i.e. when the transmit shift register and transmit buffer register does not contain data to be transmitted. When disabled, the transmitter will no longer override the TxD port.RW0UCSZ32Character SizeThe UCSZ3 bits combined with the UCSZ1:0 bit in UCSR0C sets the number of data bits (character size) in a frame the receiver and transmitter use.RW0RXB83Receive Data Bit 8RXB8 is the 9th data bit of the received character when operating with serial frames with 9 data bits. Must be read before reading the low bits from UDR0.R0TXB83Transmit Data Bit 8TXB8 is the 9th data bit in the character to be transmitted when operating with serial frames with 9 data bits. Must be writ-ten before writing the low bits to UDR0.W0UCSR3CUSART Control and Status Register CNA$132io_flag.bmpYUMSEL31USART Mode SelectRW0UMSEL30USART Mode SelectRW0UPM31Parity Mode Bit 1This bit enable and set type of parity generation and check. If enabled, the transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value for the incoming data and compare it to the UPM0 setting. If a mismatch is detected, the PE flag in UCSR0A will be set.RW0UPM30Parity Mode Bit 0This bit enable and set type of parity generation and check. If enabled, the transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value for the incoming data and compare it to the UPM0 setting. If a mismatch is detected, the PE flag in UCSR0A will be set.RW0USBS3Stop Bit Select0: 1-bit. 1: 2-bit.RW0UCSZ31Character SizeCharacter Size: 0 0 0 = 5-bit. 0 0 1 = 6-bit. 0 1 0 = 7 bit. 0 1 1 = 8-bit. 1 1 1 = 9 bit.RW1UCSZ30Character SizeCharacter Size: 0 0 0 = 5-bit. 0 0 1 = 6-bit. 0 1 0 = 7 bit. 0 1 1 = 8-bit. 1 1 1 = 9 bit.RW1UCPOL3Clock PolarityThis bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOL bit sets the relationship between data output change and data input sample, and the synchronous clock (XCK).RW0UBRR3HUSART Baud Rate Register High ByteThis is a 12-bit register which contains the USART baud rate. The UBRR0H contains the 4 most significant bits, and the UBRR0L contains the 8 least significant bits of the USART baud rate. Ongoing transmissions by the transmitter and receiver will be corrupted if the baud rate is changed. Writing UBRR0L will trigger an immediate update of the baud rate prescaler.NA$135io_com.bmpNUBRR11USART Baud Rate Register bit 11RW0UBRR10USART Baud Rate Register bit 10RW0UBRR9USART Baud Rate Register bit 9RW0UBRR8USART Baud Rate Register bit 8RW0UBRR3LUSART Baud Rate Register Low ByteThis is a 12-bit register which contains the USART baud rate. The UBRR0H contains the 4 most significant bits, and the UBRR0L contains the 8 least significant bits of the USART baud rate. Ongoing transmissions by the transmitter and receiver will be corrupted if the baud rate is changed. Writing UBRR0L will trigger an immediate update of the baud rate prescaler.NA$134io_com.bmpNUBRR7USART Baud Rate Register bit 7RW0UBRR6USART Baud Rate Register bit 6RW0UBRR5USART Baud Rate Register bit 5RW0UBRR4USART Baud Rate Register bit 4RW0UBRR3USART Baud Rate Register bit 3RW0UBRR2USART Baud Rate Register bit 2RW0UBRR1USART Baud Rate Register bit 1RW0UBRR0USART Baud Rate Register bit 0RW0[SIMULATOR:STK500_2:JTAGICEmkII:AVRISPmkII]AVRSimCoreV2.SimCoreV2AVRSimMemory8bit.SimMemory8bitAVRSimInterrupt.SimInterrupt0x3c035AVRSimIOPort.SimIOPortYAVRSimIOPort.SimIOPortYAVRSimIOPort.SimIOPortYAVRSimIOPort.SimIOPortYAVRSimIOPort.SimIOPortYAVRSimIOPort.SimIOPortYAVRSimIOPort.SimIOPortYAVRSimIOPort.SimIOPortYAVRSimIOPort.SimIOPortYAVRSimIOPort.SimIOPortYAVRSimIOPort.SimIOPortYAVRSimIOPinChangeInterrupt.SimIOPinChangeInterrupt0x120x480x010x1B0x010x4b0x030xffAVRSimIOPinChangeInterrupt.SimIOPinChangeInterrupt0x140x480x020x1B0x020xe30xff0x4cAVRSimIOPinChangeInterrupt.SimIOPinChangeInterrupt0x160x480x040x1B0x040xe60xff0x4dAVRSimIOExtInterrupt.SimIOExtInterrupt0x020x1d0x010x1c0x010x090x010x490x03AVRSimIOExtInterrupt.SimIOExtInterrupt0x040x1d0x020x1c0x020x090x020x490x0cAVRSimIOExtInterrupt.SimIOExtInterrupt0x060x1d0x040x1c0x040x090x040x490x30AVRSimIOExtInterrupt.SimIOExtInterrupt0x080x1d0x080x1c0x080x090x080x490xc0AVRSimIOExtInterrupt.SimIOExtInterrupt0x0a0x1d0x100x1c0x100x0C0x100x4a0x03AVRSimIOExtInterrupt.SimIOExtInterrupt0x0c0x1d0x200x1c0x200x0C0x200x4a0x0cAVRSimIOExtInterrupt.SimIOExtInterrupt0x0e0x1d0x400x1c0x400x0C0x400x4a0x30AVRSimIOExtInterrupt.SimIOExtInterrupt0x100x1d0x800x1c0x800x0C0x800x4a0xc0AvrSimIOtim8pwmsync2.tim8pwmsync20x2A0x2C0x2EPORTB7PORTG5AvrMasterTimer.MasterTimer0x200x220x240x260x280x090x400x090x100x050x200x050x400x050x80TIFR1/OCF1ATIFR1/OCF1BTIFR1/OCF1C1:8:64:256:10240x230x01AvrMasterTimer.MasterTimer0x1a0x1c0x1ePORTB4PORTH61:8:64:256:1024AvrMasterTimer.MasterTimer0x3E0x400x420x440x460x0C0x400x0C0x800x0e0x080x0e0x100x0e0x20TIFR3/OCF3ATIFR3/OCF3BTIFR3/OCF3C1:8:64:256:10240x230x01AvrMasterTimer.MasterTimer0x520x540x560x580x5a0xe20x800xe90x010xe00x100xe00x200xe00x40TIFR4/OCF4ATIFR4/OCF4BTIFR4/OCF4C1:8:64:256:10240x230x01AvrMasterTimer.MasterTimer0x5c0x5e0x600x620x640xe90x040xe90x020xe90x800xe90x100xe90x20TIFR5/OCF5ATIFR5/OCF5BTIFR5/OCF5C1:8:64:256:10240x230x01AVRSimIOSPM.SimIOSPM0x50AVRSimIOSpi.SimIOSpi0x300x030x020x030x080x030x040x030x040x01AVRSimIOUsart.SimIOUsart0x320x360x340x0c0x020x0c0x01AVRSimIOUsart.SimIOUsart0x480x4C0x4A0x090x080x090x04AVRSimIOUsart.SimIOUsart0x660x6a0x680xe00x020xe00x01AVRSimIOUsart.SimIOUsart0x6c0x700x6e0xe30x020xe30x01AVRSimAC.SimIOAC0x38AVRSimADC.SimADC0x3AAvrSimTWI.SimTWI0x4EAvrMasterTimer.MasterTimer016384:32768:65536:131072:262144:524288:1048576:20971520xFF0xff0xFF0xFF2001002532030x53115510x41256100x400x4C0x000x000x000x418100xC10xC20x000x000x0025625644440x0E 0x1E 0x0F 0x1F 0x2E 0x3E 0x2F 0x3F 0x4E 0x5E 0x4F 0x5F 0x6E 0x7E 0x6F 0x7F 0x66 0x76 0x67 0x77 0x6A 0x7A 0x6B 0x7B 0xBE 0xFD 0x00 0x01 0x00 0x00 0x00 0x001000511510151501050x0125625650x0725625605050x0970303FJTAG0xFF,0xFF,0xFF,0xFF,0xFF,0x3D,0xB9,0xF80xFF,0xFF,0x1F,0xE0,0xFF,0x1D,0xA9,0xF80X00,0X00,0X00,0X00,0X00,0X00,0X00,0X000X00,0X00,0X00,0X00,0X00,0X00,0X00,0X000x73,0xFF,0x3F,0xFF,0xF7,0x3F,0xF7,0x3F,0xF7,0x3F,0x5F,0x3F,0x37,0x37,0x37,0x00,0x00,0x00,0x00,0x00,0xFF,0x0F,0x00,0x00,0xF7, 0x3F, 0x36,0x000x73,0xFF,0x3F,0xF8,0xF7,0x3F,0xF7,0x3F,0xF7,0x3F,0x5F,0x2F,0x36,0x36,0x36,0x00,0x00,0x00,0x00,0x00,0xFF,0x0F,0x00,0x00,0xF7, 0x3F, 0x36,0x000x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x000x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x000x310x570x01000x00080xFE000x01360x0000,320x0020,640x000x000x000x000x000x000x00000x000x000x000x010x3F1001