[ADMIN:PACKAGE:MEMORY:CORE:INTERRUPT_VECTOR:LOCKBIT:FUSE:PROGRAMMING:IO_MODULE:ICE_SETTINGS]ATmega16820MHZ183RELEASED$1E$94$06[TQFP:MLF:PDIP]32[PD3:PCINT19:OC2B:INT1]INT1,External Interrupt source 1:The PD3 pin can serve as an external interrupt source.[PD4:XCK:T0:PCINT20]XCK, USART external clock. T0,Timer/Counter0 counter source.[GND][VCC][GND][VCC][PB6:XTAL1:TOSC1:PCINT6]XTAL1:Chipclock oscillator pin 1.Used for all chipclock sources except internal calibratable RC oscillator.When used as a clock pin,the pin can not be used as an I/O pin.When using internal calibratable RC oscillator as chip clock source,PB6 functions as an ordinary I/O pin. TOSC1:Timer Oscillator pin 1.Used only if internal calibratable RC oscillator is selected as chip clock source,and the asynchronous timer is enabled by the correct setting in ASSR.When the AS2 bit in ASSR is set (one)to enable asynchronous clocking of Timer/Counter1,pin PB6 is disconnected from the port,and becomes the input of the inverting oscillator amplifier.In this mode,a crystal oscillator is connected to this pin,and the pin can not be used as an I/O pin. If PB6 is used as a clock pin,DDB6,PORTB6 and PINB6 will all rea[PB7:XTAL2:TOSC2:PCINT7]XTAL2:Chip clock oscillator pin 2.Used as clock pin for all chip clock sources except internal calibratable RC oscillator and external clock.When used as a clock pin,the pin can not be used as an I/O pin.When using internal calibratable RC oscillator or external clock as chipclock sources,PB7 functions as an ordinary I/O pin. TOSC2:Timer Oscillator pin 2.Used only if internal calibratable RC oscillator is selected as chip clock source,and the asynchronous timer is enabled by the correct setting in ASSR.When the AS2 bit in ASSR is set (one)to enable asynchro- nous clocking of Timer/Counter2,pin PB7 is disconnected from the port,and becomes the inverting output of the oscillator amplifier.In this mode,a crystal oscillator is connected to this pin,and the pin can not be used as an I/O pin. If PB7 is used as a clock pin,DDB7,PORTB7 and PINB7 will all read[PD5:T1:OC0B:PCINT21]T1,Timer/Counter1 counter source.[PD6:AIN0:OC0A:PCINT22]AIN0,Analog Comparator Positive Input.Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the analog comparator.[PD7:AIN1:PCINT23]AIN1,Analog Comparator Negative Input.Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the analog comparator.[PB0:ICP1:CLKO:PCINT0]ICP1 -Input Capture Pin:The PB0 pin can act as an input capture pin for Timer/Counter1.[PB1:OC1A:PCINT1]OC1A,Output compare match output:The PB1 pin can serve as an external output for the Timer/Counter1 compare match A.The PB1 pin has to be configured as an output (DDB1 set (one))to serve this function.The OC1A pin is also the output pin for the PWM mode timer function.[PB2:'SS:OC1B:PCINT2]SS:Slave Select input.When the SPI is enabled as a slave,this pin is configured as an input regardless of the setting of DDB4.As a slave,the SPI is activated when this pin is driven low.When the SPI is enabled as a master,the data direction of this pin is controlled by DDB4.When the pin is forced by the SPI to be an input,the pull-up can still be controlled by the PORTB4 bit. OC1B,Output compare match output:The PB2 pin can serve as an external output for the Timer/Counter1 compare match B.The PB2 pin has to be configured as an output (DDB2 set (one))to serve this function.The OC1B pin is also the output pin for the PWM mode timer fu[PB3:MOSI:OC2A:PCINT3]MOSI:SPI Master data output,slave data input for SPI channel.When the SPI is enabled as a slave,this pin is configured as an input regardless of the setting of DDB5.When the SPI is enabled as a master,the data direction of this pin is controlled by DDB5.When the pin is forced by the SPI to be an input,the pull-up can still be controlled by the PORTB bit.[PB4:MISO:PCINT4]MISO:Master data Input,Slave data Output pin for SPI channel.When the SPI is enabled as a master,this pin is configured as an input regardless of the setting of DDB6.When the SPI is enabled as a slave,the data direction of this pin is controlled by DDB6.When the pin is forced by the SPI to be an input,the pull-up can still be controlled by the PORTB6 bit.[PB5:SCK:PCINT5]SCK:Master clock output,slave clock input pin for SPI channel.When the SPI is enabled as a slave,this pin is configured as an input regardless of the setting of DDB7.When the SPI is enabled as a master,the data direction of this pin is controlled by DDB7.When the pin is forced by the SPI to be an input,the pull-up can still be controlled by the PORTB7 bit.[AVCC][ADC6][AREF][GND][ADC7][PC0:ADC0:PCINT8]PC0 can also be used as ADC input Channel 0.Note that ADC input channel 0 uses analog ground.[PC1:ADC1:PCINT9]PC1 can also be used as ADC input Channel 1.Note that ADC input channel 1 uses analog ground.[PC2:ADC2:PCINT10]PC2 can also be used as ADC input Channel 2.Note that ADC input channel 2 uses analog ground.[PC3:ADC3:PCINT11]PC3 can also be used as ADC input Channel 3.Note that ADC input channel 3 uses analog ground.[PC4:ADC4:SDA:PCINT12]SDA,2-wire Serial Interface Data:When the TWEN bit in TWCR is set (one)to enable the 2-wire Serial Interface,pin PC1 is disconnected from the port and becomes the Serial Data I/O pin for the 2-wire Serial Interface.In this mode,there is a spike filter on the pin to suppress spikes shorter than 0 ns on the input signal,and the pin is driven by an open drain driver with slew-rate limitation. PC4 can also be used as ADC input Channel 4.Note that ADC input channel 4 uses digital ground.[PC5:ADC5:SCL:PCINT13]SCL,2-wire Serial Interface Clock:When the TWEN bit in TWCR is set (one)to enable the 2-wire Serial Interface,pin PC1 is disconnected from the port and becomes the Serial Clock I/O pin for the 2-wire Serial Interface.In this mode,there is a spike filter on the pin to suppress spikes shorter than 0 ns on the input signal,and the pin is driven by an open drain driver with slew-rate limitation. PC can also be used as ADC input Channel 5.Note that ADC input channel uses digital ground.[PC6:'RESET:PCINT14]RESET, Reset pin: When the RSTDISBL fuse is set,this pin functions as a normal I/O pin,and the part will have to rely on Power-On Reset and Brown-Out Reset as its reset sources.When the RSTDISBL fuse is cleared,the reset circuitry is connected to the pin,and the pin can not be used as an I/O pin. If PC6 is used as a reset pin,DDC6,PORTC6 and PINC6 will all read 0.[PD0:RXD:PCINT16]RXD,Receive Data (Data input pin for the USART).When the USART receiver is enabled this pin is configured as an input regardless of the value of DDD0.When the USART forces this pin to be an input,the pull-up can still be controlled by the PORTD0 bit.[PD1:TXD:PCINT17]TXD,Transmit Data (Data output pin for the USART).When the USART transmitter is enabled,this pin is configured as an output regardless of the value of DDD1.[PD2:INT0:PCINT18]INT0,External Interrupt source 0:The PD2 pin can serve as an external interrupt source.32[PD3:PCINT19:OC2B:INT1]INT1,External Interrupt source 1:The PD3 pin can serve as an external interrupt source.[PD4:XCK:T0:PCINT20]XCK, USART external clock. T0,Timer/Counter0 counter source.[GND][VCC][GND][VCC][PB6:XTAL1:TOSC1:PCINT6]XTAL1:Chipclock oscillator pin 1.Used for all chipclock sources except internal calibratable RC oscillator.When used as a clock pin,the pin can not be used as an I/O pin.When using internal calibratable RC oscillator as chip clock source,PB6 functions as an ordinary I/O pin. TOSC1:Timer Oscillator pin 1.Used only if internal calibratable RC oscillator is selected as chip clock source,and the asynchronous timer is enabled by the correct setting in ASSR.When the AS2 bit in ASSR is set (one)to enable asynchronous clocking of Timer/Counter1,pin PB6 is disconnected from the port,and becomes the input of the inverting oscillator amplifier.In this mode,a crystal oscillator is connected to this pin,and the pin can not be used as an I/O pin. If PB6 is used as a clock pin,DDB6,PORTB6 and PINB6 will all rea[PB7:XTAL2:TOSC2:PCINT7]XTAL2:Chip clock oscillator pin 2.Used as clock pin for all chip clock sources except internal calibratable RC oscillator and external clock.When used as a clock pin,the pin can not be used as an I/O pin.When using internal calibratable RC oscillator or external clock as chipclock sources,PB7 functions as an ordinary I/O pin. TOSC2:Timer Oscillator pin 2.Used only if internal calibratable RC oscillator is selected as chip clock source,and the asynchronous timer is enabled by the correct setting in ASSR.When the AS2 bit in ASSR is set (one)to enable asynchro- nous clocking of Timer/Counter2,pin PB7 is disconnected from the port,and becomes the inverting output of the oscillator amplifier.In this mode,a crystal oscillator is connected to this pin,and the pin can not be used as an I/O pin. If PB7 is used as a clock pin,DDB7,PORTB7 and PINB7 will all read[PD5:T1:OC0B:PCINT21]T1,Timer/Counter1 counter source.[PD6:AIN0:OC0A:PCINT22]AIN0,Analog Comparator Positive Input.Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the analog comparator.[PD7:AIN1:PCINT23]AIN1,Analog Comparator Negative Input.Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the analog comparator.[PB0:ICP:CLKO:PCINT0]ICP -Input Capture Pin:The PB0 pin can act as an input capture pin for Timer/Counter1.[PB1:OC1A:PCINT1]OC1A,Output compare match output:The PB1 pin can serve as an external output for the Timer/Counter1 compare match A.The PB1 pin has to be configured as an output (DDB1 set (one))to serve this function.The OC1A pin is also the output pin for the PWM mode timer function.[PB2:'SS:OC1B:PCINT2]SS:Slave Select input.When the SPI is enabled as a slave,this pin is configured as an input regardless of the setting of DDB4.As a slave,the SPI is activated when this pin is driven low.When the SPI is enabled as a master,the data direction of this pin is controlled by DDB4.When the pin is forced by the SPI to be an input,the pull-up can still be controlled by the PORTB4 bit. OC1B,Output compare match output:The PB2 pin can serve as an external output for the Timer/Counter1 compare match B.The PB2 pin has to be configured as an output (DDB2 set (one))to serve this function.The OC1B pin is also the output pin for the PWM mode timer fu[PB3:MOSI:OC2A:PCINT3]MOSI:SPI Master data output,slave data input for SPI channel.When the SPI is enabled as a slave,this pin is configured as an input regardless of the setting of DDB5.When the SPI is enabled as a master,the data direction of this pin is controlled by DDB5.When the pin is forced by the SPI to be an input,the pull-up can still be controlled by the PORTB bit.[PB4:MISO:PCINT4]MISO:Master data Input,Slave data Output pin for SPI channel.When the SPI is enabled as a master,this pin is configured as an input regardless of the setting of DDB6.When the SPI is enabled as a slave,the data direction of this pin is controlled by DDB6.When the pin is forced by the SPI to be an input,the pull-up can still be controlled by the PORTB6 bit.[PB5:SCK:PCINT5]SCK:Master clock output,slave clock input pin for SPI channel.When the SPI is enabled as a slave,this pin is configured as an input regardless of the setting of DDB7.When the SPI is enabled as a master,the data direction of this pin is controlled by DDB7.When the pin is forced by the SPI to be an input,the pull-up can still be controlled by the PORTB7 bit.[AVCC][ADC6][AREF][GND][ADC7][PC0:ADC0:PCINT8]PC0 can also be used as ADC input Channel 0.Note that ADC input channel 0 uses analog ground.[PC1:ADC1:PCINT9]PC1 can also be used as ADC input Channel 1.Note that ADC input channel 1 uses analog ground.[PC2:ADC2:PCINT10]PC2 can also be used as ADC input Channel 2.Note that ADC input channel 2 uses analog ground.[PC3:ADC3:PCINT11]PC3 can also be used as ADC input Channel 3.Note that ADC input channel 3 uses analog ground.[PC4:ADC4:SDA:PCINT12]SDA,2-wire Serial Interface Data:When the TWEN bit in TWCR is set (one)to enable the 2-wire Serial Interface,pin PC1 is disconnected from the port and becomes the Serial Data I/O pin for the 2-wire Serial Interface.In this mode,there is a spike filter on the pin to suppress spikes shorter than 0 ns on the input signal,and the pin is driven by an open drain driver with slew-rate limitation. PC4 can also be used as ADC input Channel 4.Note that ADC input channel 4 uses digital ground.[PC5:ADC5:SCL:PCINT13]SCL,2-wire Serial Interface Clock:When the TWEN bit in TWCR is set (one)to enable the 2-wire Serial Interface,pin PC1 is disconnected from the port and becomes the Serial Clock I/O pin for the 2-wire Serial Interface.In this mode,there is a spike filter on the pin to suppress spikes shorter than 0 ns on the input signal,and the pin is driven by an open drain driver with slew-rate limitation. PC can also be used as ADC input Channel 5.Note that ADC input channel uses digital ground.[PC6:'RESET:PCINT14]RESET, Reset pin: When the RSTDISBL fuse is set,this pin functions as a normal I/O pin,and the part will have to rely on Power-On Reset and Brown-Out Reset as its reset sources.When the RSTDISBL fuse is cleared,the reset circuitry is connected to the pin,and the pin can not be used as an I/O pin. If PC6 is used as a reset pin,DDC6,PORTC6 and PINC6 will all read 0.[PD0:RXD:PCINT16]RXD,Receive Data (Data input pin for the USART).When the USART receiver is enabled this pin is configured as an input regardless of the value of DDD0.When the USART forces this pin to be an input,the pull-up can still be controlled by the PORTD0 bit.[PD1:TXD:PCINT17]TXD,Transmit Data (Data output pin for the USART).When the USART transmitter is enabled,this pin is configured as an output regardless of the value of DDD1.[PD2:INT0:PCINT18]INT0,External Interrupt source 0:The PD2 pin can serve as an external interrupt source.28[PC6:'RESET:PCINT14]RESET, Reset pin: When the RSTDISBL fuse is set,this pin functions as a normal I/O pin,and the part will have to rely on Power-On Reset and Brown-Out Reset as its reset sources.When the RSTDISBL fuse is cleared,the reset circuitry is connected to the pin,and the pin can not be used as an I/O pin. If PC6 is used as a reset pin,DDC6,PORTC6 and PINC6 will all read 0.[PD0:RXD:PCINT16]RXD,Receive Data (Data input pin for the USART).When the USART receiver is enabled this pin is configured as an input regardless of the value of DDD0.When the USART forces this pin to be an input,the pull-up can still be controlled by the PORTD0 bit.[PD1:TXD:PCINT17]TXD,Transmit Data (Data output pin for the USART).When the USART transmitter is enabled,this pin is configured as an output regardless of the value of DDD1.[PD2:INT0:PCINT18]INT0,External Interrupt source 0:The PD2 pin can serve as an external interrupt source.[PD3:PCINT19:OC2B:INT1]INT1,External Interrupt source 1:The PD3 pin can serve as an external interrupt source.[PD4:XCK:T0:PCINT20]XCK, USART external clock. T0,Timer/Counter0 counter source.[VCC][GND][PB6:XTAL1:TOSC1:PCINT6]XTAL1:Chipclock oscillator pin 1.Used for all chipclock sources except internal calibratable RC oscillator.When used as a clock pin,the pin can not be used as an I/O pin.When using internal calibratable RC oscillator as chip clock source,PB6 functions as an ordinary I/O pin. TOSC1:Timer Oscillator pin 1.Used only if internal calibratable RC oscillator is selected as chip clock source,and the asynchronous timer is enabled by the correct setting in ASSR.When the AS2 bit in ASSR is set (one)to enable asynchronous clocking of Timer/Counter1,pin PB6 is disconnected from the port,and becomes the input of the inverting oscillator amplifier.In this mode,a crystal oscillator is connected to this pin,and the pin can not be used as an I/O pin. If PB6 is used as a clock pin,DDB6,PORTB6 and PINB6 will all rea[PB7:XTAL2:TOSC2:PCINT7]XTAL2:Chip clock oscillator pin 2.Used as clock pin for all chip clock sources except internal calibratable RC oscillator and external clock.When used as a clock pin,the pin can not be used as an I/O pin.When using internal calibratable RC oscillator or external clock as chipclock sources,PB7 functions as an ordinary I/O pin. TOSC2:Timer Oscillator pin 2.Used only if internal calibratable RC oscillator is selected as chip clock source,and the asynchronous timer is enabled by the correct setting in ASSR.When the AS2 bit in ASSR is set (one)to enable asynchro- nous clocking of Timer/Counter2,pin PB7 is disconnected from the port,and becomes the inverting output of the oscillator amplifier.In this mode,a crystal oscillator is connected to this pin,and the pin can not be used as an I/O pin. If PB7 is used as a clock pin,DDB7,PORTB7 and PINB7 will all read[PD5:T1:OC0B:PCINT21]T1,Timer/Counter1 counter source.[PD6:AIN0:OC0A:PCINT22]AIN0,Analog Comparator Positive Input.Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the analog comparator.[PD7:AIN1:PCINT23]AIN1,Analog Comparator Negative Input.Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the analog comparator.[PB0:ICP1:CLKO:PCINT0]ICP1 -Input Capture Pin1:The PB0 pin can act as an input capture pin for Timer/Counter1.[PB1:OC1A:PCINT1]OC1A,Output compare match output:The PB1 pin can serve as an external output for the Timer/Counter1 compare match A.The PB1 pin has to be configured as an output (DDB1 set (one))to serve this function.The OC1A pin is also the output pin for the PWM mode timer function.[PB2:'SS:OC1B:PCINT2]SS:Slave Select input.When the SPI is enabled as a slave,this pin is configured as an input regardless of the setting of DDB4.As a slave,the SPI is activated when this pin is driven low.When the SPI is enabled as a master,the data direction of this pin is controlled by DDB4.When the pin is forced by the SPI to be an input,the pull-up can still be controlled by the PORTB4 bit. OC1B,Output compare match output:The PB2 pin can serve as an external output for the Timer/Counter1 compare match B.The PB2 pin has to be configured as an output (DDB2 set (one))to serve this function.The OC1B pin is also the output pin for the PWM mode timer fun[PB3:MOSI:OC2A:PCINT3]MOSI:SPI Master data output,slave data input for SPI channel.When the SPI is enabled as a slave,this pin is configured as an input regardless of the setting of DDB5.When the SPI is enabled as a master,the data direction of this pin is controlled by DDB5.When the pin is forced by the SPI to be an input,the pull-up can still be controlled by the PORTB bit.[PB4:MISO:PCINT4]MISO:Master data Input,Slave data Output pin for SPI channel.When the SPI is enabled as a master,this pin is configured as an input regardless of the setting of DDB6.When the SPI is enabled as a slave,the data direction of this pin is controlled by DDB6.When the pin is forced by the SPI to be an input,the pull-up can still be controlled by the PORTB6 bit.[PB5:SCK:PCINT5]SCK:Master clock output,slave clock input pin for SPI channel.When the SPI is enabled as a slave,this pin is configured as an input regardless of the setting of DDB7.When the SPI is enabled as a master,the data direction of this pin is controlled by DDB7.When the pin is forced by the SPI to be an input,the pull-up can still be controlled by the PORTB7 bit.[AVCC][AREF][GND][PC0:ADC0:PCINT8]PC0 can also be used as ADC input Channel 0.Note that ADC input channel 0 uses analog ground.[PC1:ADC1:PCINT9]PC1 can also be used as ADC input Channel 1.Note that ADC input channel 1 uses analog ground.[PC2:ADC2:PCINT10]PC2 can also be used as ADC input Channel 2.Note that ADC input channel 2 uses analog ground.[PC3:ADC3:PCINT11]PC3 can also be used as ADC input Channel 3.Note that ADC input channel 3 uses analog ground.[PC4:ADC4:SDA:PCINT12]SDA,2-wire Serial Interface Data:When the TWEN bit in TWCR is set (one)to enable the 2-wire Serial Interface,pin PC1 is disconnected from the port and becomes the Serial Data I/O pin for the 2-wire Serial Interface.In this mode,there is a spike filter on the pin to suppress spikes shorter than 0 ns on the input signal,and the pin is driven by an open drain driver with slew-rate limitation. PC4 can also be used as ADC input Channel 4.Note that ADC input channel 4 uses digital ground.[PC5:ADC5:SCL:PCINT13]SCL,2-wire Serial Interface Clock:When the TWEN bit in TWCR is set (one)to enable the 2-wire Serial Interface,pin PC1 is disconnected from the port and becomes the Serial Clock I/O pin for the 2-wire Serial Interface.In this mode,there is a spike filter on the pin to suppress spikes shorter than 0 ns on the input signal,and the pin is driven by an open drain driver with slew-rate limitation. PC can also be used as ADC input Channel 5.Note that ADC input channel uses digital ground.AVRSimMemory8bit.SimMemory8bit163845121024$1000NA$00$3F$60$FF$20$FFNA0xC60x010x020x040x080x100x200x400x80NA0xC50x010x020x040x08NA0xC40x010x020x040x080x100x200x400x80NA0xC20x010x020x040x080x100x200x400x80NA0xC10x010x020x040x080x100x200x400x80NA0xC00x010x020x040x080x100x200x400x80NA0xBD0x020x040x080x100x200x400x80NA0xBC0x010x040x080x100x200x400x80NA0xBB0x010x020x040x080x100x200x400x80NA0xBA0x010x020x040x080x100x200x400x80NA0xB90x010x020x080x100x200x400x80NA0xB80x010x020x040x080x100x200x400x80NA0xB60x010x020x040x080x100x200x40NA0xB40x010x020x040x080x100x200x400x80NA0xB30x010x020x040x080x100x200x400x80NA0xB20x010x020x040x080x100x200x400x80NA0xB10x010x020x040x080x400x80NA0xB00x010x020x100x200x400x80NA0x8B0x010x020x040x080x100x200x400x80NA0x8A0x010x020x040x080x100x200x400x80NA0x890x010x020x040x080x100x200x400x80NA0x880x010x020x040x080x100x200x400x80NA0x870x010x020x040x080x100x200x400x80NA0x860x010x020x040x080x100x200x400x80NA0x850x010x020x040x080x100x200x400x80NA0x840x010x020x040x080x100x200x400x80NA0x820x400x80NA0x810x010x020x040x080x100x400x80NA0x800x010x020x100x200x400x80NA0x7F0x010x02NA0x7E0x010x020x040x080x100x20NA0x7C0x010x020x040x080x200x400x80NA0x7B0x010x020x040x40NA0x7A0x010x020x040x080x100x200x400x80NA0x790x010x020x040x080x100x200x400x80NA0x780x010x020x040x080x100x200x400x80NA0x700x010x020x04NA0x6F0x010x020x040x20NA0x6E0x010x020x04NA0x6D0x010x020x040x080x100x200x400x80NA0x6C0x010x020x040x080x100x200x40NA0x6B0x010x020x040x080x100x200x400x80NA0x690x010x020x040x08NA0x680x010x020x04NA0x660x010x020x040x080x100x200x400x80NA0x640x010x020x040x080x200x400x80NA0x610x010x020x040x080x80NA0x600x010x020x040x080x100x200x400x800x3F0x5F0x010x020x040x080x100x200x400x800x3E0x5E0x040x010x020x040x3D0x5D0xFF0x010x020x040x080x100x200x400x800x370x570x010x020x040x080x100x400x800x350x550x010x020x100x340x540x010x020x040x080x330x530x010x020x040x080x300x500x010x020x040x080x100x200x400x800x2E0x4E0x010x020x040x080x100x200x400x800x2D0x4D0x010x400x800x2c0x4C0x010x020x040x080x100x200x400x800x2B0x4B0x010x020x040x080x100x200x400x800x2A0x4A0x010x020x040x080x100x200x400x800x280x480x010x020x040x080x100x200x400x800x270x470x010x020x040x080x100x200x400x800x260x460x010x020x040x080x100x200x400x800x250x450x010x020x040x080x400x800x240x440x010x020x100x200x400x800x230x430x010x800x020x220x420x010x210x410x010x020x040x080x100x200x400x800x200x400x010x020x040x080x100x200x400x800x1F0x3F0x010x020x040x080x100x200x1E0x3E0x010x020x040x080x100x200x400x800x1D0x3D0x010x020x1C0x3C0x010x020x1B0x3B0x010x020x040x170x370x010x020x040x160x360x010x020x040x200x150x350x010x020x040x0B0x2B0x010x020x040x080x100x200x400x800x0A0x2A0x010x020x040x080x100x200x400x800x090x290x010x020x040x080x100x200x400x800x080x280x010x020x040x080x100x200x400x070x270x010x020x040x080x100x200x400x060x260x010x020x040x080x100x200x400x050x250x010x020x040x080x100x200x400x800x040x240x010x020x040x080x100x200x400x800x030x230x010x020x040x080x100x200x400x80$1C00$1FFF$0$1BFF641282$0$1F80$1F802564$0$1F00$1F005128$0$1E00$1E00102416$0$1C00$1C00V2EAVRSimCoreV2.SimCoreV2[][][]32$00$1B$1A$1D$1C$1F$1E26AVRSimInterrupt.SimInterrupt$000External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset$002External Interrupt Request 0$004External Interrupt Request 1$006Pin Change Interrupt Request 0$008Pin Change Interrupt Request 0$00APin Change Interrupt Request 1$00CWatchdog Time-out Interrupt$00ETimer/Counter2 Compare Match A$0010Timer/Counter2 Compare Match A$0012Timer/Counter2 Overflow$0014Timer/Counter1 Capture Event$0016Timer/Counter1 Compare Match A$0018Timer/Counter1 Compare Match B$001ATimer/Counter1 Overflow$001CTimerCounter0 Compare Match A$001ETimerCounter0 Compare Match B$020Timer/Couner0 Overflow$022SPI Serial Transfer Complete$024USART Rx Complete$026USART, Data Register Empty$028USART Tx Complete$02AADC Conversion Complete$02CEEPROM Ready$02EAnalog Comparator$030Two-wire Serial Interface$032Store Program Memory Read[LB1 = 1 : LB2 = 1] No memory lock features enabled. [LB1 = 0 : LB2 = 1] Further programming of Flash and EEPROM is enabled. [LB1 = 0 : LB2 = 0] Same as previous, but verify is also disabled6110x030x03Mode 1: No memory lock features enabled0x030x02Mode 2: Further programming disabled0x030x00Mode 3: Further programming and verification disabled0x0C0x0CApplication Protection Mode 1: No lock on SPM and LPM in Application Section0x0C0x08Application Protection Mode 2: SPM prohibited in Application Section0x0C0x00Application Protection Mode 3: LPM and SPM prohibited in Application Section0x0C0x04Application Protection Mode 4: LPM prohibited in Application Section0x300x30Boot Loader Protection Mode 1: No lock on SPM and LPM in Boot Loader Section0x300x20Boot Loader Protection Mode 2: SPM prohibited in Boot Loader Section0x300x00Boot Loader Protection Mode 3: LPM and SPM prohibited in Boot Loader Section0x300x10Boot Loader Protection Mode 4: LPM prohibited in Boot Loader SectionLB1Lock bitLB2Lock bitBLB01Boot Lock bitBLB02Boot Lock bitBLB11Boot lock bitBLB12Boot lock bit[LOW:HIGH:EXTENDED]8CKDIV8Divide clock by 80CKOUTClock output1SUT1Select start-up time1SUT0Select start-up time0CKSEL3Select Clock Source0CKSEL2Select Clock Source0CKSEL1Select Clock Source1CKSEL0Select Clock Source0570x800x00Divide clock by 8 internally; [CKDIV8=0]0x400x00Clock output on PORTB0; [CKOUT=0]0x3F0x00Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms; [CKSEL=0000 SUT=00]0x3F0x10Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms; [CKSEL=0000 SUT=01]0x3F0x20Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms; [CKSEL=0000 SUT=10]0x3F0x02Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms; [CKSEL=0010 SUT=00]0x3F0x12Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms; [CKSEL=0010 SUT=01]0x3F0x22Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms; [CKSEL=0010 SUT=10]; default value0x3F0x03Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms; [CKSEL=0011 SUT=00]0x3F0x13Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms; [CKSEL=0011 SUT=01]0x3F0x23Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms; [CKSEL=0011 SUT=10]0x3F0x04Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 0 ms; [CKSEL=0100 SUT=00] 0x3F0x14Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4.1 ms; [CKSEL=0100 SUT=01] 0x3F0x24Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 65 ms; [CKSEL=0100 SUT=10] 0x3F0x05Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 0 ms; [CKSEL=0101 SUT=00] 0x3F0x15Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 4.1 ms; [CKSEL=0101 SUT=01] 0x3F0x25Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 65 ms; [CKSEL=0101 SUT=10] 0x3F0x06Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms;[CKSEL=0110 SUT=00] 0x3F0x16Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms; [CKSEL=0110 SUT=01] 0x3F0x26Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms; [CKSEL=0110 SUT=10] 0x3F0x36Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms;[CKSEL=0110 SUT=11] 0x3F0x07Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms; [CKSEL=0111 SUT=00] 0x3F0x17Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms; [CKSEL=0111 SUT=01] 0x3F0x27Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms;[CKSEL=0111 SUT=10] 0x3F0x37Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms; [CKSEL=0111 SUT=11] 0x3F0x08Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms; [CKSEL=1000 SUT=00] 0x3F0x18Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms; [CKSEL=1000 SUT=01] 0x3F0x28Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms; [CKSEL=1000 SUT=10] 0x3F0x38Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms; [CKSEL=1000 SUT=11] 0x3F0x09Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms; [CKSEL=1001 SUT=00] 0x3F0x19Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms; [CKSEL=1001 SUT=01] 0x3F0x29Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms; [CKSEL=1001 SUT=10] 0x3F0x39Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms; [CKSEL=1001 SUT=11] 0x3F0x0AExt. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms; [CKSEL=1010 SUT=00] 0x3F0x1AExt. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms; [CKSEL=1010 SUT=01] 0x3F0x2AExt. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms; [CKSEL=1010 SUT=10] 0x3F0x3AExt. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms; [CKSEL=1010 SUT=11] 0x3F0x0BExt. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms; [CKSEL=1011 SUT=00] 0x3F0x1BExt. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms; [CKSEL=1011 SUT=01] 0x3F0x2BExt. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms; [CKSEL=1011 SUT=10] 0x3F0x3BExt. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms; [CKSEL=1011 SUT=11] 0x3F0x0CExt. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms; [CKSEL=1100 SUT=00] 0x3F0x1CExt. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms; [CKSEL=1100 SUT=01] 0x3F0x2CExt. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms; [CKSEL=1100 SUT=10] 0x3F0x3CExt. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms; [CKSEL=1100 SUT=11] 0x3F0x0DExt. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms; [CKSEL=1101 SUT=00] 0x3F0x1DExt. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms; [CKSEL=1101 SUT=01] 0x3F0x2DExt. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms; [CKSEL=1101 SUT=10] 0x3F0x3DExt. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms; [CKSEL=1101 SUT=11] 0x3F0x0EExt. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms; [CKSEL=1110 SUT=00] 0x3F0x1EExt. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms; [CKSEL=1110 SUT=01] 0x3F0x2EExt. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms; [CKSEL=1110 SUT=10] 0x3F0x3EExt. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms; [CKSEL=1110 SUT=11] 0x3F0x0FExt. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms; [CKSEL=1111 SUT=00] 0x3F0x1FExt. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms; [CKSEL=1111 SUT=01] 0x3F0x2FExt. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms; [CKSEL=1111 SUT=10] 0x3F0x3FExt. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms; [CKSEL=1111 SUT=11] 8RSTDISBLExternal reset disable1DWENdebugWIRE Enable1SPIENEnable Serial programming and Data Downloading0WDTONWatchdog Timer Always On1EESAVEEEPROM memory is preserved through chip erase1BODLEVEL2Brown-out Detector trigger level1BODLEVEL1Brown-out Detector trigger level1BODLEVEL0Brown-out Detector trigger level190x800x00Reset Disabled (Enable PC6 as i/o pin); [RSTDISBL=0]0x400x00Debug Wire enable; [DWEN=0]0x200x00Serial program downloading (SPI) enabled; [SPIEN=0]0x100x00Watch-dog Timer always on; [WDTON=0]0x080x00Preserve EEPROM memory through the Chip Erase cycle; [EESAVE=0]0x070x04Brown-out detection level at VCC=4.3 V; [BODLEVEL=100] 0x070x05Brown-out detection level at VCC=2.7 V; [BODLEVEL=101] 0x070x06Brown-out detection level at VCC=1.8 V; [BODLEVEL=110] 0x070x07Brown-out detection disabled; [BODLEVEL=111] 3BOOTSZ1Select boot size0BOOTSZ0Select boot size0BOOTRSTSelect reset vector150x060x06Boot Flash section size=128 words Boot start address=$1F80; [BOOTSZ=11]0x060x04Boot Flash section size=256 words Boot start address=$1F00; [BOOTSZ=10]0x060x02Boot Flash section size=512 words Boot start address=$1E00; [BOOTSZ=01]0x060x00Boot Flash section size=1024 words Boot start address=$1C00; [BOOTSZ=00] ; default value0x010x00Boot Reset vector Enabled (default address=$0000); [BOOTRST=0]0xff,0xdf,0xff0xff,0xdf,0xff1,0x20,0x20,WARNING! These fuse settings will disable the ISP interface!1,0x80,0x00,WARNING! Disabling external reset will make the ISP interface inaccessible!1,0x40,0x00,WARNING! Enabling DEBUGWIRE will make the ISP interface inaccessible!0,0x3F,0x03,WARNING! Using this clock option together with the CKDIV8 fuse bit will require a slow ISP speed ~2kHz.0,0x3F,0x13,WARNING! Using this clock option together with the CKDIV8 fuse bit will require a slow ISP speed ~2kHz.0,0x3F,0x23,WARNING! Using this clock option together with the CKDIV8 fuse bit will require a slow ISP speed ~2kHz.1,0x20,0x20,WARNING! These fuse settings will disable the ISP interface!1,0x80,0x00,WARNING! Disabling external reset will make the ISP interface inaccessible!1,0x40,0x00,WARNING! Enabling DEBUGWIRE will make the ISP interface inaccessible!0,0x3F,0x03,WARNING! Using this clock option together with the CKDIV8 fuse bit will require a slow ISP speed ~2kHz.0,0x3F,0x13,WARNING! Using this clock option together with the CKDIV8 fuse bit will require a slow ISP speed ~2kHz.0,0x3F,0x23,WARNING! Using this clock option together with the CKDIV8 fuse bit will require a slow ISP speed ~2kHz.0x00,8.0 MHz1284[USART0:TWI:TIMER_COUNTER_1:TIMER_COUNTER_2:AD_CONVERTER:ANALOG_COMPARATOR:PORTB:PORTC:PORTD:TIMER_COUNTER_0:EXTERNAL_INTERRUPT:SPI:CPU:WATCHDOG:EEPROM][UDR0:UCSR0A:UCSR0B:UCSR0C:UBRR0H:UBRR0L]
[UBRR0H:UBRR0L]
io_com.bmpThe Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. The main features are: • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • High Resolution Baud Rate Generator • Supports Serial Frames with 5, 6, 7, 8 or 9 Data Bits and 1 or 2 Stop Bits • Odd or Even Parity Generation and Parity Check Supported by Hardware • Data OverRun Detection • Framing Error Detection • Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter • Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete • Multi-processor Communication Mode • Double Speed Asynchronous CommunicaUDR0USART I/O Data RegisterThe UDR0 register is actually two physically separate registers sharing the same I/O address. When writing to the register, the USART Transmit Data register is written. When reading from UDR0, the USART Receive Data register is read.NA0xC6io_com.bmpNUDR0-7USART I/O Data Register bit 7RW0UDR0-6USART I/O Data Register bit 6RW0UDR0-5USART I/O Data Register bit 5RW0UDR0-4USART I/O Data Register bit 4RW0UDR0-3USART I/O Data Register bit 3RW0UDR0-2USART I/O Data Register bit 2RW0UDR0-1USART I/O Data Register bit 1RW0UDR0-0USART I/O Data Register bit 0RW0UCSR0AUSART Control and Status Register ANA0xC0io_flag.bmpYRXC0USART Receive CompleteThis bit is set (one) when a received character is transferred from the Receiver Shift register to UDR0. The bit is set regard-less of any detected framing errors. When the RXCIE bit in UCR is set, the USART Receive Complete interrupt will be executed when RXC is set(one). RXC is cleared by reading UDR0. When interrupt-driven data reception is used, the USART Receive Complete Interrupt routine must read UDRin order to clear RXC, otherwise a new interrupt will occur once the interrupt routine terminates.R0TXC0USART Transmitt CompleteThis bit is set (one) when the entire character (including the stop bit) in the Transmit Shift register has been shifted out and no new data has been written to UDR0. This flag is especially useful in half-duplex communications interfaces, where a transmitting application must enter receive mode and free the communications bus immediately after completing the transmission. When the TXCIE bit in UCR is set, setting of TXC causes the USART Transmit Complete interrupt to be executed. TXC is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the TXC bit is cleared (zero) by writing a logical one to the bRW0UDRE0USART Data Register EmptyThis bit is set (one) when a character written to UDRis transferred to the Transmit shift register. Setting of this bit indicates that the transmitter is ready to receive a new character for transmission. When the UDR0IE bit in UCR is set, the USART Transmit Complete interrupt to be executed as long as UDR0E is set. UDR0E is cleared by writing UDR0. When interrupt-driven data transmittal is used, the USART Data Register Empty Interrupt routine must write UDRin order to clear UDR0E, otherwise a new interrupt will occur once the interrupt routine terminates. UDR0E is set (one) during reset to indicate that the transmitter is reR1FE0Framing ErrorThis bit is set if a Framing Error condition is detected, i.e. when the stop bit of an incoming character is zero. The FE bit is cleared when the stop bit of received data is one.R0DOR0Data overRunThis bit is set if an Overrun condition is detected, i.e. when a character already present in the UDRregister is not read before the next character has been shifted into the Receiver Shift register. The OR bit is buffered, which means that it will be set once the valid data still in UDR0E is read. The OR bit is cleared (zero) when data is received and transferred to UDR0. R0UPE0Parity ErrorThis bit is set if the next character in the receive buffer had a Parity Error when received and the parity checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer (UDR0) is read. Always set this bit to zero when writing to UCSR0A.R0U2X0Double the USART transmission speedThis bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation. Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous communication.RW0MPCM0Multi-processor Communication ModeThis bit enables the Multi-processor Communication Mode. When the MPCM bit is written to one, all the incoming frames received by the USART receiver that do not contain address information will be ignored. The transmitter is unaffected by the MPCM setting. For more detailed information see “Multi-processor Communication Mode” on page 152.RW0UCSR0BUSART Control and Status Register BNA0xC1io_flag.bmpYRXCIE0RX Complete Interrupt EnableWriting this bit to one enables interrupt on the RXC flag. A USART Receive Complete interrupt will be generated only if the RXCIE bit is written to one, the global interrupt flag in SREG is written to one and the RXC bit in UCSR0A is set.RW0TXCIE0TX Complete Interrupt EnableWriting this bit to one enables interrupt on the TXC flag. A USART Transmit Complete interrupt will be generated only if the TXCIE bit is written to one, the global interrupt flag in SREG is written to one and the TXC bit in UCSR0A is set.RW0UDRIE0USART Data register Empty Interrupt EnableWriting this bit to one enables interrupt on the UDR0E flag. A Data Register Empty interrupt will be generated only if the UDR0IE bit is written to one, the global interrupt flag in SREG is written to one and the UDR0E bit in UCSR0A is set.RW1RXEN0Receiver EnableWriting this bit to one enables the USART receiver. The receiver will override normal port operation for the RxD pin when enabled. Disabling the receiver will flush the receive buffer invalidating the FE, DOR and PE flags.RW0TXEN0Transmitter EnableWriting this bit to one enables the USART transmitter. The transmitter will override normal port operation for the TxD pin when enabled. The disabling of the transmitter (writing TXEN to zero) will not become effective until ongoing and pending transmissions are completed, i.e. when the transmit shift register and transmit buffer register does not contain data to be transmitted. When disabled, the transmitter will no longer override the TxD port.RW0UCSZ02Character SizeThe UCSZ2 bits combined with the UCSZ1:0 bit in UCSR0C sets the number of data bits (character size) in a frame the receiver and transmitter use.RW0RXB80Receive Data Bit 8RXB8 is the 9th data bit of the received character when operating with serial frames with 9 data bits. Must be read before reading the low bits from UDR0.R0TXB80Transmit Data Bit 8TXB8 is the 9th data bit in the character to be transmitted when operating with serial frames with 9 data bits. Must be writ-ten before writing the low bits to UDR0.W0UCSR0CUSART Control and Status Register CNA0xC2io_flag.bmpYUMSEL01UMSEL1USART Mode SelectRW0UMSEL00UMSEL0USART Mode SelectRW0UPM01Parity Mode Bit 1This bit enable and set type of parity generation and check. If enabled, the transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value for the incoming data and compare it to the UPM0 setting. If a mismatch is detected, the PE flag in UCSR0A will be set.RW0UPM00Parity Mode Bit 0This bit enable and set type of parity generation and check. If enabled, the transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value for the incoming data and compare it to the UPM0 setting. If a mismatch is detected, the PE flag in UCSR0A will be set.RW0USBS0Stop Bit Select0: 1-bit. 1: 2-bit.RW0UCSZ01UDORD0Character SizeCharacter Size: 0 0 0 = 5-bit. 0 0 1 = 6-bit. 0 1 0 = 7 bit. 0 1 1 = 8-bit. 1 1 1 = 9 bit.RW0UCSZ00UCPHA0Character SizeCharacter Size: 0 0 0 = 5-bit. 0 0 1 = 6-bit. 0 1 0 = 7 bit. 0 1 1 = 8-bit. 1 1 1 = 9 bit.RW1UCPOL0Clock PolarityThis bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOL bit sets the relationship between data output change and data input sample, and the synchronous clock (XCK).RW0UBRR0HUSART Baud Rate Register High ByteThis is a 12-bit register which contains the USART baud rate. The UBRR0H contains the 4 most significant bits, and the UBRR0L contains the 8 least significant bits of the USART baud rate. Ongoing transmissions by the transmitter and receiver will be corrupted if the baud rate is changed. Writing UBRR0L will trigger an immediate update of the baud rate prescaler.NA0xC5io_com.bmpNUBRR11USART Baud Rate Register bit 11RW0UBRR10USART Baud Rate Register bit 10RW0UBRR9USART Baud Rate Register bit 9RW0UBRR8USART Baud Rate Register bit 8RW0UBRR0LUSART Baud Rate Register Low ByteThis is a 12-bit register which contains the USART baud rate. The UBRR0H contains the 4 most significant bits, and the UBRR0L contains the 8 least significant bits of the USART baud rate. Ongoing transmissions by the transmitter and receiver will be corrupted if the baud rate is changed. Writing UBRR0L will trigger an immediate update of the baud rate prescaler.NA0xC4io_com.bmpNUBRR7USART Baud Rate Register bit 7RW0UBRR6USART Baud Rate Register bit 6RW0UBRR5USART Baud Rate Register bit 5RW0UBRR4USART Baud Rate Register bit 4RW0UBRR3USART Baud Rate Register bit 3RW0UBRR2USART Baud Rate Register bit 2RW0UBRR1USART Baud Rate Register bit 1RW0UBRR0USART Baud Rate Register bit 0RW0[TWAMR:TWBR:TWCR:TWSR:TWDR:TWAR]io_com.bmpTWI: Simple yet powerful and flexible communications interface, only two bus lines needed. Both master and slave operation supported. Device can operate as transmitter or receiver. 7-bit address space allows up to 128 different slave addresses. Multi-master arbitration support Up to 400 kHz data transfer speed Slew-rate limited output drivers Noise suppression circuitry rejects spikes on bus lines Fully programmable slave address with general call support Address recognition causes wake-up when AVR is in sleep mode The Two-Wire Serial Interface (TWI) is ideally suited to typical microcontroller applications. The TWI protocol allows the systems designer to interconnect up to 128 different devices using only two bidirectional bus lines, one for clock (SCL) andone for data (SDA). The only external hardware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines. All devices connected to the bus have individual addresses, and mechanisms for resolving bus contention are inherent in the TWI prTWAMRTWI (Slave) Address Mask RegisterThe TWAMR can be loaded with a 7-bit Salve Address mask. Each of the bits in TWAMR can mask (disable) the corresponding address bits in the TWI Address Register (TWAR). If the mask bit is set to one then the address match logic ingnores the compare between the incomming address bit and the corresponding bit in TWAR.NA0xBDio_com.bmpYTWAM6TWAMR6RW0TWAM5TWAMR5RW0TWAM4TWAMR4RW0TWAM3TWAMR3RW0TWAM2TWAMR2RW0TWAM1TWAMR1RW0TWAM0TWAMR0RW0TWBRTWI Bit Rate registerTWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency divider which generates the SCL clock frequency in the master modes. See “Bit Rate Generator Unit” on page 165 for calculating bit rates.NA0xB8io_com.bmpNTWBR7RW0TWBR6RW0TWBR5RW0TWBR4RW0TWBR3RW0TWBR2RW0TWBR1RW0TWBR0RW0TWCRTWI Control RegisterThe TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate a master access by applying a START condition to the bus, to generate a receiver acknowledge, to generate a stop condition, and to control halting of the bus while the data to be written to the bus are written to the TWDR. It also indicates a write collision if data is attempted written to TWDR while the register is inaccessible.NA0xBCio_flag.bmpYTWINTTWI Interrupt FlagThis bit is set by hardware when the TWI has finished its current job and expects application software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the TWI interrupt vector. While the TWINT flag is set, the SCL low period is stretched. The TWINT flag must be cleared by software by writing a logic one to it. Note that this flag is not automatically cleared by hardware when executing the interrupt routine. Also note that clearing this flag starts the operation of the TWI, so all accesses to the TWI Address Register (TWAR), TWI Status Register (TWSR), and TWI Data Register (TWDR) must be complete before clearing this flagRW0TWEATWI Enable Acknowledge BitThe TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is written to one, the ACK pulse is gener-ated on the TWI bus if the following conditions are met: 1. The device’s own slave address has been received. 2. A general call has been received, while the TWGCE bit in the TWAR is set. 3. A data byte has been received in master receiver or slave receiver mode. By writing the TWEA bit to zero, the device can be virtually disconnected from the 2-wire Serial Bus temporarily. Address recognition can then be resumed by writing the TWEA bit to one againRW0TWSTATWI Start Condition BitThe application writes the TWSTA bit to one when it desires to become a master on the 2-wire Serial Bus. The TWI hard-ware checks if the bus is available, and generates a START condition on the bus if it is free. However, if the bus is not free, the TWI waits until a STOP condition is detected, and then generates a new START condition to claim the bus Master sta-tus. TWSTA is cleared by the TWI hardware when the START condition has been transmitted.RW0TWSTOTWI Stop Condition BitWriting the TWSTO bit to one in master mode will generate a STOP condition on the 2-wire Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit is cleared automatically. In slave mode, setting the TWSTO bit can be used to recover from an error condition. This will not generate a STOP condition, but the TWI returns to a well-defined unaddressed slave mode and releases the SCL and SDA lines to a high impedance state.RW0TWWCTWI Write Collition FlagThe TWWC bit is set when attempting to write to the TWI Data Register - TWDR when TWINT is low. This flag is cleared by writing the TWDR register when TWINT is high.RW0TWENTWI Enable BitThe TWEN bit enables TWI operation and activates the TWI interface. When TWEN is written to one, the TWI takes control over the I/O pins connected to the SCL and SDA pins, enabling the slew-rate limiters and spike filters. If this bit is written to zero, the TWI is switched off and all TWI transmissions are terminated, regardless of any ongoing operation.RW0TWIETWI Interrupt EnableWhen this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request will be activated for as long as the TWINT flag is high.RW0TWSRTWI Status RegisterNA0xB9io_flag.bmpYTWS7TWI StatusBits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient cRW0TWS6TWI StatusBits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient coRW0TWS5TWI StatusBits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient cRW0TWS4TWI StatusBits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient coRW0TWS3TWI StatusBits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient coRW0TWPS1TWI PrescalerBits 1..0: These bits can be read and written, and control the bit rate prescaler. See “Bit Rate Generator Unit” on page 165 for calculating bit rates.RW0TWPS0TWI PrescalerBits 1..0: These bits can be read and written, and control the bit rate prescaler. See “Bit Rate Generator Unit” on page 165 for calculating bit rates.RW0TWDRTWI Data registerIn transmit mode, TWDR contains the next byte to be transmitted. In receive mode, the TWDR contains the last byte received. It is writable while the TWI is not in the process of shifting a byte. This occurs when the TWI interrupt flag (TWINT) is set by hardware. Note that the data register cannot be initialized by the user before the first interrupt occurs. The data in TWDR remains stable as long as TWINT is set. While data is shifted out, data on the bus is simultaneously shifted in. TWDR always contains the last byte present on the bus, except after a wake up from a sleep mode by the TWI interrupt. In this case, the contents of TWDR is undefined. In the case of a lost bus arbitration, no data is lost in the transi-tion from Master to Slave. Handling of the ACK bit is controlled automatically by the TWI logic, the CPU cannot access the ACK bit directlNA0xBBio_com.bmpNTWD7TWI Data Register Bit 7RW1TWD6TWI Data Register Bit 6RW1TWD5TWI Data Register Bit 5RW1TWD4TWI Data Register Bit 4RW1TWD3TWI Data Register Bit 3RW1TWD2TWI Data Register Bit 2RW1TWD1TWI Data Register Bit 1RW1TWD0TWI Data Register Bit 0RW1TWARTWI (Slave) Address registerThe TWAR should be loaded with the 7-bit slave address (in the seven most significant bits of TWAR) to which the TWI will respond when programmed as a slave transmitter or receiver, and not needed in the master modes. In multimaster sys-tems, TWAR must be set in masters which can be addressed as slaves by other masters. The LSB of TWAR is used to enable recognition of the general call address ($00). There is an associated address compar-ator that looks for the slave address (or general call address if enabled) in the received serial address. If a match is found, an interrupt request is generaNA0xBAio_com.bmpYTWA6TWI (Slave) Address register Bit 6RW0TWA5TWI (Slave) Address register Bit 5RW0TWA4TWI (Slave) Address register Bit 4RW0TWA3TWI (Slave) Address register Bit 3RW0TWA2TWI (Slave) Address register Bit 2RW0TWA1TWI (Slave) Address register Bit 1RW0TWA0TWI (Slave) Address register Bit 0RW0TWGCETWI General Call Recognition Enable BitRW0[TIMSK1:TIFR1:TCCR1A:TCCR1B:TCCR1C:TCNT1H:TCNT1L:OCR1AH:OCR1AL:OCR1BH:OCR1BL:ICR1H:ICR1L:GTCCR]
[TCNT1H:TCNT1L];[OCR1AH:OCR1AL];[OCR1BH:OCR1BL];[ICR1H:ICR1L]
io_timer.bmpt16pwm1_12.xmlTIMSK1Timer/Counter Interrupt Mask RegisterNA0x6Fio_flag.bmpYICIE1Timer/Counter1 Input Capture Interrupt EnableWhen the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on pin 31, ICP, i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.RW0OCIE1BTimer/Counter1 Output CompareB Match Interrupt EnableWhen the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter1 occurs, i.e., when the OCF1B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.R0OCIE1ATimer/Counter1 Output CompareA Match Interrupt EnableWhen the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a CompareA match in Timer/Counter1 occurs, i.e., when the OCF1A bit is set in the Timer/Counter Interrupt Flag Register - TIFR.RW0TOIE1Timer/Counter1 Overflow Interrupt EnableWhen the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $006) is executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.RW0TIFR1Timer/Counter Interrupt Flag register0x160x36io_flag.bmpYICF1Input Capture Flag 1The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to the input capture register - ICR1. ICF1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF1 is cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable), and ICF1 are set (one), the Timer/Counter1 Capture Interrupt is executed. RW0OCF1BOutput Compare Flag 1BThe OCF1B bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1B - Output Compare Register 1B. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1B (Timer/Counter1 Compare match InterruptB Enable), and the OCF1B are set (one), the Timer/Counter1 Compare B match Interrupt is executed.RW0OCF1AOutput Compare Flag 1AThe OCF1A bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare match InterruptA Enable), and the OCF1A are set (one), the Timer/Counter1 Compare A match Interrupt is executed. RW0TOV1Timer/Counter1 Overflow FlagThe TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the cor-responding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter1 changes counting direction at $0000.RW0TCCR1ATimer/Counter1 Control Register ANA0x80io_flag.bmpYCOM1A1Compare Output Mode 1A, bit 1The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA. This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10.RW0COM1A0Comparet Ouput Mode 1A, bit 0The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA. This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10.RW0COM1B1Compare Output Mode 1B, bit 1The COM1B1 and COM1B0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.RW0COM1B0Compare Output Mode 1B, bit 0The COM1B1 and COM1B0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin.RW0WGM11Waveform Generation ModeCombined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.RW0WGM10Waveform Generation ModeCombined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.RW0TCCR1BTimer/Counter1 Control Register BNA0x81io_flag.bmpYICNC1Input Capture 1 Noise CancelerWhen the ICNC1 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the ICP - input capture pin - as specified. When the ICNC1 bit is set (one), four successive samples are measures on the ICP - input capture pin, and all samples must be high/low according to the input capture trigger specification in the ICES1 bit. The actual sampling frequency is XTAL clock frequency.RW0ICES1Input Capture 1 Edge SelectWhile the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the falling edge of the input capture pin - ICP. While the ICES1 bit is set (one), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the rising edge of the input capture pin - ICP.RW0WGM13Waveform Generation ModeCombined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.RW0WGM12Waveform Generation ModeCombined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table.RW0CS12Prescaler source of Timer/Counter 1Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.RW0CS11Prescaler source of Timer/Counter 1Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.RW0CS10Prescaler source of Timer/Counter 1Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge.RW0TCCR1CTimer/Counter1 Control Register CNA0x82io_flag.bmpYFOC1ARW0FOC1BRW0TCNT1HTimer/Counter1 High ByteThis 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR1A, OCR1B and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt rouNA0x85io_timer.bmpNTCNT1H7Timer/Counter1 High Byte bit 7RW0TCNT1H6Timer/Counter1 High Byte bit 6RW0TCNT1H5Timer/Counter1 High Byte bit 5RW0TCNT1H4Timer/Counter1 High Byte bit 4RW0TCNT1H3Timer/Counter1 High Byte bit 3RW0TCNT1H2Timer/Counter1 High Byte bit 2RW0TCNT1H1Timer/Counter1 High Byte bit 1RW0TCNT1H0Timer/Counter1 High Byte bit 0RW0TCNT1LTimer/Counter1 Low ByteThis 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR1A, OCR1B and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interruNA0x84io_timer.bmpNTCNT1L7Timer/Counter1 Low Byte bit 7RW0TCNT1L6Timer/Counter1 Low Byte bit 6RW0TCNT1L5Timer/Counter1 Low Byte bit 5RW0TCNT1L4Timer/Counter1 Low Byte bit 4RW0TCNT1L3Timer/Counter1 Low Byte bit 3RW0TCNT1L2Timer/Counter1 Low Byte bit 2RW0TCNT1L1Timer/Counter1 Low Byte bit 1RW0TCNT1L0Timer/Counter1 Low Byte bit 0RW0OCR1AHTimer/Counter1 Outbut Compare Register High ByteThe output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interruNA0x89io_timer.bmpNOCR1AH7Timer/Counter1 Outbut Compare Register High Byte bit 7RW0OCR1AH6Timer/Counter1 Outbut Compare Register High Byte bit 6RW0OCR1AH5Timer/Counter1 Outbut Compare Register High Byte bit 5RW0OCR1AH4Timer/Counter1 Outbut Compare Register High Byte bit 4RW0OCR1AH3Timer/Counter1 Outbut Compare Register High Byte bit 3RW0OCR1AH2Timer/Counter1 Outbut Compare Register High Byte bit 2RW0OCR1AH1Timer/Counter1 Outbut Compare Register High Byte bit 1RW0OCR1AH0Timer/Counter1 Outbut Compare Register High Byte bit 0RW0OCR1ALTimer/Counter1 Outbut Compare Register Low ByteThe output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interruNA0x88io_timer.bmpNOCR1AL7Timer/Counter1 Outbut Compare Register Low Byte Bit 7RW0OCR1AL6Timer/Counter1 Outbut Compare Register Low Byte Bit 6RW0OCR1AL5Timer/Counter1 Outbut Compare Register Low Byte Bit 5RW0OCR1AL4Timer/Counter1 Outbut Compare Register Low Byte Bit 4RW0OCR1AL3Timer/Counter1 Outbut Compare Register Low Byte Bit 3RW0OCR1AL2Timer/Counter1 Outbut Compare Register Low Byte Bit 2RW0OCR1AL1Timer/Counter1 Outbut Compare Register Low Byte Bit 1RW0OCR1AL0Timer/Counter1 Outbut Compare Register Low Byte Bit 0RW0OCR1BHTimer/Counter1 Output Compare Register High ByteThe output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt roNA0x8Bio_timer.bmpNOCR1BH7Timer/Counter1 Output Compare Register High Byte bit 7RW0OCR1BH6Timer/Counter1 Output Compare Register High Byte bit 6RW0OCR1BH5Timer/Counter1 Output Compare Register High Byte bit 5RW0OCR1BH4Timer/Counter1 Output Compare Register High Byte bit 4RW0OCR1BH3Timer/Counter1 Output Compare Register High Byte bit 3RW0OCR1BH2Timer/Counter1 Output Compare Register High Byte bit 2RW0OCR1BH1Timer/Counter1 Output Compare Register High Byte bit 1RW0OCR1BH0Timer/Counter1 Output Compare Register High Byte bit 0RW0OCR1BLTimer/Counter1 Output Compare Register Low ByteThe output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt routNA0x8Aio_timer.bmpNOCR1BL7Timer/Counter1 Output Compare Register Low Byte bit 7R0OCR1BL6Timer/Counter1 Output Compare Register Low Byte bit 6RW0OCR1BL5Timer/Counter1 Output Compare Register Low Byte bit 5RW0OCR1BL4Timer/Counter1 Output Compare Register Low Byte bit 4RW0OCR1BL3Timer/Counter1 Output Compare Register Low Byte bit 3RW0OCR1BL2Timer/Counter1 Output Compare Register Low Byte bit 2RW0OCR1BL1Timer/Counter1 Output Compare Register Low Byte bit 1RW0OCR1BL0Timer/Counter1 Output Compare Register Low Byte bit 0RW0ICR1HTimer/Counter1 Input Capture Register High ByteThe input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES1) of the signal at the input capture pin -ICP - is detected, the current value of the Timer/Counter1 is transferred to the Input Capture Register - ICR1. At the same time, the input capture flag - ICF1 - is set (one). Since the Input Capture Register - ICR1 - is a 16-bit register, a temporary register TEMP is used when ICR1 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR1L, the data is sent to the CPU and the data of the high byte ICR1H is placed in the TEMP register. When the CPU reads the data in the high byte ICR1H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR1L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT1, OCR1A and OCR1B. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interruptNA0x87io_timer.bmpNICR1H7Timer/Counter1 Input Capture Register High Byte bit 7RW0ICR1H6Timer/Counter1 Input Capture Register High Byte bit 6R0ICR1H5Timer/Counter1 Input Capture Register High Byte bit 5R0ICR1H4Timer/Counter1 Input Capture Register High Byte bit 4R0ICR1H3Timer/Counter1 Input Capture Register High Byte bit 3R0ICR1H2Timer/Counter1 Input Capture Register High Byte bit 2R0ICR1H1Timer/Counter1 Input Capture Register High Byte bit 1R0ICR1H0Timer/Counter1 Input Capture Register High Byte bit 0R0ICR1LTimer/Counter1 Input Capture Register Low ByteThe input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES1) of the signal at the input capture pin -ICP - is detected, the current value of the Timer/Counter1 is transferred to the Input Capture Register - ICR1. At the same time, the input capture flag - ICF1 - is set (one). Since the Input Capture Register - ICR1 - is a 16-bit register, a temporary register TEMP is used when ICR1 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR1L, the data is sent to the CPU and the data of the high byte ICR1H is placed in the TEMP register. When the CPU reads the data in the high byte ICR1H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR1L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT1, OCR1A and OCR1B. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interNA0x86io_timer.bmpNICR1L7Timer/Counter1 Input Capture Register Low Byte bit 7R0ICR1L6Timer/Counter1 Input Capture Register Low Byte bit 6R0ICR1L5Timer/Counter1 Input Capture Register Low Byte bit 5R0ICR1L4Timer/Counter1 Input Capture Register Low Byte bit 4R0ICR1L3Timer/Counter1 Input Capture Register Low Byte bit 3R0ICR1L2Timer/Counter1 Input Capture Register Low Byte bit 2R0ICR1L1Timer/Counter1 Input Capture Register Low Byte bit 1R0ICR1L0Timer/Counter1 Input Capture Register Low Byte bit 0R0GTCCRGeneral Timer/Counter Control Register0x230x43io_flag.bmpYTSMTimer/Counter Synchronization ModeWriting the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSR2 and PSR10 bits is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSR2 and PSR10 bits are cleared by hardware, and the Timer/Counters start counting simultaneousRW0PSRSYNCPrescaler Reset Timer/Counter1 and Timer/Counter0When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers.RW0[TIMSK2:TIFR2:TCCR2A:TCCR2B:TCNT2:OCR2A:OCR2B:ASSR:GTCCR]io_timer.bmpAt8pwm2_07The 8-bit Timer/Counter2 can select clock source from CK, prescaled CK, or external crystal input TOSC1. It can also be stopped as described in the section “Timer/Counter2 Control Register - TCCR2”. The status flags (overflow and compare match) are found in the Timer/Counter Interrupt Flag Register - TIFR. Control signals are found in the Timer/Counter Control Register TCCR2. The interrupt enable/disable settings are found in “The Timer/Counter Interrupt Mask Register - TIMSK”. When Timer/Counter2 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. This module features a high resolution and a high accuracy usage with the lower prescaling opportunities. Similarly, the high prescaling opportunities make this unit useful for lower speed functions or exact timing functions with infrequent actions. Timer/Counter2 can also be used as an 8-bit Pulse Width Modulator. In this mode, Timer/Counter2 and the output compare register serve as a glitch-free, stand-alone PWM with centered pulsTIMSK2Timer/Counter Interrupt Mask registerNA0x70io_flag.bmpYOCIE2BTimer/Counter2 Output Compare Match B Interrupt EnableWhen the OCIE2B bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match B interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter2 occurs, i.e., when the OCF2B bit is set in the Timer/Counter 2 Interrupt Flag Register – TIFR2.RW0OCIE2ATimer/Counter2 Output Compare Match A Interrupt EnableWhen the OCIE2A bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match A interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter2 occurs, i.e., when the OCF2A bit is set in the Timer/Counter 2 Interrupt Flag Register – TIFR2.RW0TOIE2TOIE2ATimer/Counter2 Overflow Interrupt EnableWhen the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is set in the Timer/Counter2 Interrupt Flag Register – TIFR2.RW0TIFR2Timer/Counter Interrupt Flag Register0x170x37io_flag.bmpYOCF2BOutput Compare Flag 2BThe OCF2B bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2B – Output Compare Register2. OCF2B is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF2B is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2B (Timer/Counter2 Compare match Interrupt Enable), and OCF2B are set (one), the Timer/Counter2 Compare match Interrupt is executed.RW0OCF2AOutput Compare Flag 2AThe OCF2A bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2A – Output Compare Register2. OCF2A is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF2A is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2A (Timer/Counter2 Compare match Interrupt Enable), and OCF2A are set (one), the Timer/Counter2 Compare match Interrupt is executed.RW0TOV2Timer/Counter2 Overflow FlagThe TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE2A (Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter2 changes counting direction at 0x00.RW0TCCR2ATimer/Counter2 Control Register ANA0xB0io_flag.bmpYCOM2A1Compare Output Mode bit 1The COM21 and COM20 control bits determine any output pin action following a compare match in Timer/Counter2. Output pin actions affect pin PD7(OC2). This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. (COM21:COM20) description: (0:0) = Timer/Counter disconnected from output pin OC2. (0:1) = Toggle the OC2 output line. (1:0) = Clear the OC2 output line (to zero). (1:1) = Set the OC2 output line (to one). Note: In PWM mode, these bits have a different functionRW0COM2A0Compare Output Mode bit 1The COM21 and COM20 control bits determine any output pin action following a compare match in Timer/Counter2. Output pin actions affect pin PD7(OC2). This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. (COM21:COM20) description: (0:0) = Timer/Counter disconnected from output pin OC2. (0:1) = Toggle the OC2 output line. (1:0) = Clear the OC2 output line (to zero). (1:1) = Set the OC2 output line (to one). Note: In PWM mode, these bits have a different functionRW0COM2B1Compare Output Mode bit 1The COM21 and COM20 control bits determine any output pin action following a compare match in Timer/Counter2. Output pin actions affect pin PD7(OC2). This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. (COM21:COM20) description: (0:0) = Timer/Counter disconnected from output pin OC2. (0:1) = Toggle the OC2 output line. (1:0) = Clear the OC2 output line (to zero). (1:1) = Set the OC2 output line (to one). Note: In PWM mode, these bits have a different functionRW0COM2B0Compare Output Mode bit 0The COM21 and COM20 control bits determine any output pin action following a compare match in Timer/Counter2. Output pin actions affect pin PD7(OC2). This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. (COM21:COM20) description: (0:0) = Timer/Counter disconnected from output pin OC2. (0:1) = Toggle the OC2 output line. (1:0) = Clear the OC2 output line (to zero). (1:1) = Set the OC2 output line (to one). Note: In PWM mode, these bits have a different functioRW0WGM21Waveform Genration ModeThese bits control the counting sequence of the counter,the source for hte maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter), Clear Timer on Compare match (CTC)mode,and two types of Pulse Width Modulation (PWM)modes. Please refer to the manual for more information.RW0WGM20Waveform Genration ModeThese bits control the counting sequence of the counter,the source for hte maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter), Clear Timer on Compare match (CTC)mode,and two types of Pulse Width Modulation (PWM)modes. Please refer to the manual for more information.RW0TCCR2BTimer/Counter2 Control Register BNA0xB1io_flag.bmpYFOC2AForce Output Compare AWriting a logical one to this bit, forces a change in the compare match output pin PD7 (OC2) according to the values already set in COM21 and COM20. If the COM21 and COM20 bits are written in the same cycle as FOC2, the new settings will not take effect until next compare match or forced output compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM21 and COM20 happens as if a Compare Match had occurred, but no interrupt is generated, and the Timer/Counter will not be cleared even if CTC2 is set. The corresponding I/O pin must be set as an output pin for the FOC2 bit to have effect on the pin. The FOC2 bit will always be read as zero. Setting the FOC2 bit has no effect in PWM modeRW0FOC2BForce Output Compare BWriting a logical one to this bit, forces a change in the compare match output pin PD7 (OC2) according to the values already set in COM21 and COM20. If the COM21 and COM20 bits are written in the same cycle as FOC2, the new settings will not take effect until next compare match or forced output compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM21 and COM20 happens as if a Compare Match had occurred, but no interrupt is generated, and the Timer/Counter will not be cleared even if CTC2 is set. The corresponding I/O pin must be set as an output pin for the FOC2 bit to have effect on the pin. The FOC2 bit will always be read as zero. Setting the FOC2 bit has no effect in PWM modeRW0WGM22Waveform Generation ModeThese bits control the counting sequence of the counter,the source for hte maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter), Clear Timer on Compare match (CTC)mode,and two types of Pulse Width Modulation (PWM)modes. Please refer to the manual for more information.RW0CS22Clock Select bit 2The Clock Select bits 2,1, and 0 define the prescaling source of Timer/Counter2. (CS22:CS21:CS20) Description. (0:0:0) Timer/Counter2 is stopped. (0:0:1) PCK2. (0:1:0) PCK2/8. (0:1:1) PCK2/32. (1:0:0) PCK2/64. (1:0:1) PCK2/128. (1:1:0) PCK2/256. (1:1:1) PCK2/1024. The Stop condition provides a Timer Enable/Disable function. The prescaled modes are scaled directly from the PCK2 clock.RW0CS21Clock Select bit 1The Clock Select bits 2,1, and 0 define the prescaling source of Timer/Counter2. (CS22:CS21:CS20) Description. (0:0:0) Timer/Counter2 is stopped. (0:0:1) PCK2. (0:1:0) PCK2/8. (0:1:1) PCK2/32. (1:0:0) PCK2/64. (1:0:1) PCK2/128. (1:1:0) PCK2/256. (1:1:1) PCK2/1024. The Stop condition provides a Timer Enable/Disable function. The prescaled modes are scaled directly from the PCK2 clock.RW0CS20Clock Select bit 0The Clock Select bits 2,1, and 0 define the prescaling source of Timer/Counter2. (CS22:CS21:CS20) Description. (0:0:0) Timer/Counter2 is stopped. (0:0:1) PCK2. (0:1:0) PCK2/8. (0:1:1) PCK2/32. (1:0:0) PCK2/64. (1:0:1) PCK2/128. (1:1:0) PCK2/256. (1:1:1) PCK2/1024. The Stop condition provides a Timer Enable/Disable function. The prescaled modes are scaled directly from the PCK2 clock.RW0TCNT2Timer/Counter2This 8-bit register contains the value of Timer/Counter2. Timer/Counters2 is implemented as an up or up/down (in PWM mode) counter with read and write access. If the Timer/Counter2iswritten to and a clocksourceisselected,it continues counting in the timer clock cycle following the write operation.NA0xB2io_timer.bmpNTCNT2-7Timer/Counter 2 bit 7RW0TCNT2-6Timer/Counter 2 bit 6RW0TCNT2-5Timer/Counter 2 bit 5RW0TCNT2-4Timer/Counter 2 bit 4RW0TCNT2-3Timer/Counter 2 bit 3RW0TCNT2-2Timer/Counter 2 bit 2RW0TCNT2-1Timer/Counter 2 bit 1RW0TCNT2-0Timer/Counter 2 bit 0RW0OCR2BTimer/Counter2 Output Compare Register BThe output compare register is an 8-bit read/write register. The Timer/Counter Output Compare Register contains the data to be continuously compared with Timer/Counter2. Actions on compare matches are specified in TCCR2. A compare match does only occur if Timer/Counter2 counts to the OCR2 value. A software write that sets TCNT2 and OCR2 to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Timer/Counter2 in PWM Mode When PWM mode is selected, the Timer/Counter2 either wraps (overflows) when it reaches $FF or it acts as an up/down counter. If the up/down mode is selected, the Timer/Counter2 and the Output Compare Register - OCR2 form an 8-bit, free-running, glitch-free, and phase correct PWM with outputs on the PD7(OC2) pin. If the overflow mode is selected, the Timer/Counter2 and the Output Compare Register - OCR2 form an 8-bit, free-running, and glitch-free PWM, operating with twice the speed of the up/down counting mode. PWM Modes (Up/Down and Overflow). The two different PWM modes are selected by the CTC2 bit in the Timer/Counter Control Register - TCCR2. If CTC2 is cleared and PWM mode is selected, the Timer/Counter acts as an up/down counter, counting up from $00 to $FF, where it turns and counts down again to zero before the cycle is repeated. When the counter value matches the con-tents of the Output Compare Register, the PD7(OC2) pin is set or cleared according to the settings of the COM21/COM20 bits in the Timer/Counter Control Register TCCR2. If CTC2 is set and PWM mode is selected, the Timer/Counters will wrap and start counting from $00 after reaching $FF. The PD7(OC2) pin will be set or cleared according to the settings of COM21/COM20 on a Timer/Counter overflow or when the counter value matches the contents of the Output Compare Register. Note that in PWM mode, the value to be written to the Output Compare Register is first transferred to a temporary location, and then latched into OCR2 when the Timer/Counter reaches $FF. This prevents the occurrence of odd-length PWM pulses (glitches) in the event of an unsynchronized OCR2 write. (CTC2:COM21:COM20) Effect on Compare Pin Frequency: (0:0:0) = Not connected. (0:0:1) = Not connected. (0:1:0) = Cleared on compare match, up-counting. Set on compare match, down-counting (non-inverted PWM). f TCK0/2 /510. (0:1:1) = Cleared on compare match, down-counting. Set on compare match, up-counting (inverted PWM). f TCK0/2 /510. (1:0:0) = Not connected. (1:0:1) = Not connected. (1:1:0) = Cleared on compare match, set on overflow. f TCK0/2 /256. (1:1:1) = Set on compare match, cleared on overflow. f TCK0/NA0xB4io_timer.bmpNOCR2-7Timer/Counter2 Output Compare Register Bit 7RW0OCR2-6Timer/Counter2 Output Compare Register Bit 6RW0OCR2-5Timer/Counter2 Output Compare Register Bit 5RW0OCR2-4Timer/Counter2 Output Compare Register Bit 4RW0OCR2-3Timer/Counter2 Output Compare Register Bit 3RW0OCR2-2Timer/Counter2 Output Compare Register Bit 2RW0OCR2-1Timer/Counter2 Output Compare Register Bit 1RW0OCR2-0Timer/Counter2 Output Compare Register Bit 0RW0OCR2ATimer/Counter2 Output Compare Register AThe output compare register is an 8-bit read/write register. The Timer/Counter Output Compare Register contains the data to be continuously compared with Timer/Counter2. Actions on compare matches are specified in TCCR2. A compare match does only occur if Timer/Counter2 counts to the OCR2 value. A software write that sets TCNT2 and OCR2 to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Timer/Counter2 in PWM Mode When PWM mode is selected, the Timer/Counter2 either wraps (overflows) when it reaches $FF or it acts as an up/down counter. If the up/down mode is selected, the Timer/Counter2 and the Output Compare Register - OCR2 form an 8-bit, free-running, glitch-free, and phase correct PWM with outputs on the PD7(OC2) pin. If the overflow mode is selected, the Timer/Counter2 and the Output Compare Register - OCR2 form an 8-bit, free-running, and glitch-free PWM, operating with twice the speed of the up/down counting mode. PWM Modes (Up/Down and Overflow). The two different PWM modes are selected by the CTC2 bit in the Timer/Counter Control Register - TCCR2. If CTC2 is cleared and PWM mode is selected, the Timer/Counter acts as an up/down counter, counting up from $00 to $FF, where it turns and counts down again to zero before the cycle is repeated. When the counter value matches the con-tents of the Output Compare Register, the PD7(OC2) pin is set or cleared according to the settings of the COM21/COM20 bits in the Timer/Counter Control Register TCCR2. If CTC2 is set and PWM mode is selected, the Timer/Counters will wrap and start counting from $00 after reaching $FF. The PD7(OC2) pin will be set or cleared according to the settings of COM21/COM20 on a Timer/Counter overflow or when the counter value matches the contents of the Output Compare Register. Note that in PWM mode, the value to be written to the Output Compare Register is first transferred to a temporary location, and then latched into OCR2 when the Timer/Counter reaches $FF. This prevents the occurrence of odd-length PWM pulses (glitches) in the event of an unsynchronized OCR2 write. (CTC2:COM21:COM20) Effect on Compare Pin Frequency: (0:0:0) = Not connected. (0:0:1) = Not connected. (0:1:0) = Cleared on compare match, up-counting. Set on compare match, down-counting (non-inverted PWM). f TCK0/2 /510. (0:1:1) = Cleared on compare match, down-counting. Set on compare match, up-counting (inverted PWM). f TCK0/2 /510. (1:0:0) = Not connected. (1:0:1) = Not connected. (1:1:0) = Cleared on compare match, set on overflow. f TCK0/2 /256. (1:1:1) = Set on compare match, cleared on overflow. f TCK0/NA0xB3io_timer.bmpNOCR2-7Timer/Counter2 Output Compare Register Bit 7RW0OCR2-6Timer/Counter2 Output Compare Register Bit 6RW0OCR2-5Timer/Counter2 Output Compare Register Bit 5RW0OCR2-4Timer/Counter2 Output Compare Register Bit 4RW0OCR2-3Timer/Counter2 Output Compare Register Bit 3RW0OCR2-2Timer/Counter2 Output Compare Register Bit 2RW0OCR2-1Timer/Counter2 Output Compare Register Bit 1RW0OCR2-0Timer/Counter2 Output Compare Register Bit 0RW0ASSRAsynchronous Status RegisterNA0xB6io_flag.bmpYEXCLKEnable External Clock InputWhen EXCLK is written to one, and asynchronous clock is selected, the external clock input buffer is enabled and an external clock can be input on Timer Oscillator 1 (TOSC1) pin instead of a 32 kHz crystal. Writing to EXCLK should be done before asynchronous operation is selected. Note that the crystal Oscillator will only run when this bit is zero.RW0AS2Asynchronous Timer/Counter2When AS2 is written to zero, Timer/Counter2 is clocked from the I/O clock, clkI/O. When AS2 is written to one, Timer/Counter2 is clocked from a crystal Oscillator connected to the Timer Oscillator 1 (TOSC1) pin. When the value of AS2 is changed, the contents of TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B might be corrupted.RW0TCN2UBTimer/Counter2 Update BusyWhen Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set. When TCNT2 has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCNT2 is ready to be updated with a new value.R0OCR2AUBOutput Compare Register2 Update BusyWhen Timer/Counter2 operates asynchronously and OCR2A is written, this bit becomes set. When OCR2A has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that OCR2A is ready to be updated with a new value.R0OCR2BUBOutput Compare Register 2 Update BusyWhen Timer/Counter2 operates asynchronously and OCR2B is written, this bit becomes set. When OCR2B has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that OCR2B is ready to be updated with a new value.R0TCR2AUBTimer/Counter Control Register2 Update BusyWhen Timer/Counter2 operates asynchronously and TCCR2A is written, this bit becomes set. When TCCR2A has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCCR2A is ready to be updated with a new value.R0TCR2BUBTimer/Counter Control Register2 Update BusyWhen Timer/Counter2 operates asynchronously and TCCR2B is written, this bit becomes set. When TCCR2B has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCCR2B is ready to be updated with a new value.R0GTCCRGeneral Timer Counter Control register0x230x43io_flag.bmpYTSMTimer/Counter Synchronization ModeRW0PSRASYPSR2Prescaler Reset Timer/Counter2When this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally cleared immediately by hardware. If the bit is written when Timer/Counter2 is operating in asynchronous mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by hardware if the TSM bit is set. Refer to the description of the “Bit 7 – TSM: Timer/Counter Synchronization Mode” on page 107 for a description of the Timer/Counter Synchronization mode.RW0[ADMUX:ADCSRA:ADCSRB:ADCH:ADCL:DIDR0]((IF ADMUX.ADLAR = 1) LINK [ADCH(1:0):ADCL(7:0)]); (IF ADMUX.ADLAR = 0) LINK [ADCH(7:0):ADCL(7:6)]);io_analo.bmpAD Converter Feature list: 10-bit Resolution. 0.5 LSB Integral Non-Linearity. +-2 LSB Absolute Accuracy. TBD - 260 µs Conversion Time. Up to TBD kSPS at maximum resolution. 8 Multiplexed Single Ended Input Channels. 7 Differential input channels (TQFP package only). 2 Differential input channels with optional gain of 10x and 200x (TQFP package only). Optional left adjustment for ADC result readout. 0 - VCC ADC Input Voltage Range. Selectable 2.56 V ADC reference voltage. Free Running or Single Conversion Mode. Interrupt on ADC Conversion Complete. Sleep Mode NoADMUXThe ADC multiplexer Selection RegisterNA0x7Cio_analo.bmpYREFS1Reference Selection Bit 1These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin.RW0REFS0Reference Selection Bit 0These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin.RW0ADLARLeft Adjust ResultThe ADLAR bit affects the presentation of the ADC conversion result in the ADC data register. If ADLAR is cleared, the result is right adjusted. If ADLAR is set, the result is left adjusted. Changing the ADLAR bit will affect the ADC data register immediately, regardless of any ongoing conversions. For a complete description of this bit, see “The ADC Data Register -ADCL and ADCH” on page 198. RW0MUX3Analog Channel and Gain Selection BitsThe value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).RW0MUX2Analog Channel and Gain Selection BitsThe value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).RW0MUX1Analog Channel and Gain Selection BitsThe value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).RW0MUX0Analog Channel and Gain Selection BitsThe value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).RW0ADCHADC Data Register High ByteWhen an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. The selected channel is differential if MUX4..0 are between ‘01000’ and ‘11101’, otherwise the selected channel is single ended. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8 bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUX4..0 bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adjuNA0x79io_analo.bmpNADCH7ADC Data Register High Byte Bit 7RW0ADCH6ADC Data Register High Byte Bit 6RW0ADCH5ADC Data Register High Byte Bit 5RW0ADCH4ADC Data Register High Byte Bit 4RW0ADCH3ADC Data Register High Byte Bit 3RW0ADCH2ADC Data Register High Byte Bit 2RW0ADCH1ADC Data Register High Byte Bit 1RW0ADCH0ADC Data Register High Byte Bit 0RW0ADCLADC Data Register Low ByteWhen an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. The selected channel is differential if MUX4..0 are between ‘01000’ and ‘11101’, otherwise the selected channel is single ended. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8 bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUX4..0 bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adNA0x78io_analo.bmpNADCL7ADC Data Register Low Byte Bit 7RW0ADCL6ADC Data Register Low Byte Bit 6RW0ADCL5ADC Data Register Low Byte Bit 5RW0ADCL4ADC Data Register Low Byte Bit 4RW0ADCL3ADC Data Register Low Byte Bit 3RW0ADCL2ADC Data Register Low Byte Bit 2RW0ADCL1ADC Data Register Low Byte Bit 1RW0ADCL0ADC Data Register Low Byte Bit 0RW0ADCSRAThe ADC Control and Status register ANA0x7Aio_flag.bmpYADENADC EnableWriting a logical ‘1’ to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.RW0ADSCADC Start ConversionIn Single Conversion Mode, a logical ‘1’ must be written to this bit to start each conversion. In Free Running Mode, a logical ‘1’ must be written to this bit to start the first conversion. The first time ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, an extended conversion will result. This extended conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. When a dummy conversion precedes a real conversion, ADSC will stay high until the real conversion completes. Writing a 0 to this bit has no effectRW0ADATEADC Auto Trigger EnableWhen this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a conversion on a positive edge of the selected trigger signal. The trigger source is selected by setting the ADC Trigger Select bits, ADTS in ADCSRB.RW0ADIFADC Interrupt FlagThis bit is set (one) when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set (one). ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a read-modify-write on ADCSR, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used.RW0ADIEADC Interrupt EnableWhen this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Complete Interrupt is activated.RW0ADPS2ADC Prescaler Select BitsThese bits determine the division factor between the XTAL frequency and the input clock to the ADC.RW0ADPS1ADC Prescaler Select BitsThese bits determine the division factor between the XTAL frequency and the input clock to the ADC.RW0ADPS0ADC Prescaler Select BitsThese bits determine the division factor between the XTAL frequency and the input clock to the ADC.RW0ADCSRBThe ADC Control and Status register BNA0x7Bio_flag.bmpYACMERW0ADTS2ADC Auto Trigger Source bit 2Please refer to table on page 240 in datasheet for trigger selection.RW0ADTS1ADC Auto Trigger Source bit 1Please refer to table on page 240 in datasheet for trigger selection.RW0ADTS0ADC Auto Trigger Source bit 0Please refer to table on page 240 in datasheet for trigger selection.RW0DIDR0Digital Input Disable RegisterWhen this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer.NA0x7Eio_analo.bmpYADC5DRW0ADC4DRW0ADC3DRW0ADC2DRW0ADC1DRW0ADC0DRW0[ACSR:DIDR1]io_analo.bmpAlgComp_06ACSRAnalog Comparator Control And Status Register0x300x50io_analo.bmpYACDAnalog Comparator DisableWhen this bit is written logic one, the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.RW0ACBGAnalog Comparator Bandgap SelectWhen this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. See “Internal Voltage Reference” on page 42.RW0ACOAnalog Compare OutputThe output of the analog comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1-2 clock cycles.RNAACIAnalog Comparator Interrupt FlagThis bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hard-ware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.RW0ACIEAnalog Comparator Interrupt EnableWhen the ACIE bit is written logic one and the I-bit in the Status Register is set, the analog comparator interrupt is acti-vated. When written logic zero, the interrupt is disabled.RW0ACICRW0ACIS1Analog Comparator Interrupt Mode Select bit 1These bits determine which comparator events that trigger the Analog Comparator interrupt.RW0ACIS0Analog Comparator Interrupt Mode Select bit 0These bits determine which comparator events that trigger the Analog Comparator interrupt.RW0DIDR1Digital Input Disable Register 1When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer.NA0x7Fio_analo.bmpYAIN1DAIN1 Digital Input DisableRW0AIN0DAIN0 Digital Input DisableRW0[PORTB:DDRB:PINB]io_port.bmpAVRSimIOPort.SimIOPortPORTBPort B Data Register0x050x25io_port.bmpNPORTB7Port B Data Register bit 7RW0PORTB6Port B Data Register bit 6RW0PORTB5Port B Data Register bit 5RW0PORTB4Port B Data Register bit 4RW0PORTB3Port B Data Register bit 3RW0PORTB2Port B Data Register bit 2RW0PORTB1Port B Data Register bit 1RW0PORTB0Port B Data Register bit 0RW0DDRBPort B Data Direction Register0x040x24io_flag.bmpNDDB7Port B Data Direction Register bit 7RW0DDB6Port B Data Direction Register bit 6RW0DDB5Port B Data Direction Register bit 5RW0DDB4Port B Data Direction Register bit 4RW0DDB3Port B Data Direction Register bit 3RW0DDB2Port B Data Direction Register bit 2RW0DDB1Port B Data Direction Register bit 1RW0DDB0Port B Data Direction Register bit 0RW0PINBPort B Input PinsThe Port B Input Pins address - PINB - is not a register, and this address enables access to the physical value on each Port B pin. When reading PORTB, the Port B Data Latch is read, and when reading PINB, the logical values present on the pins are read.0x030x23io_port.bmpNPINB7Port B Input Pins bit 7R0PINB6Port B Input Pins bit 6R0PINB5Port B Input Pins bit 5R0PINB4Port B Input Pins bit 4R0PINB3Port B Input Pins bit 3R0PINB2Port B Input Pins bit 2R0PINB1Port B Input Pins bit 1R0PINB0Port B Input Pins bit 0R0[PORTC:DDRC:PINC]io_port.bmpAVRSimIOPort.SimIOPortPORTCPort C Data Register0x080x28io_port.bmpNPORTC6Port C Data Register bit 6RW0PORTC5Port C Data Register bit 5RW0PORTC4Port C Data Register bit 4RW0PORTC3Port C Data Register bit 3RW0PORTC2Port C Data Register bit 2RW0PORTC1Port C Data Register bit 1RW0PORTC0Port C Data Register bit 0RW0DDRCPort C Data Direction Register0x070x27io_flag.bmpNDDC6Port C Data Direction Register bit 6RW0DDC5Port C Data Direction Register bit 5RW0DDC4Port C Data Direction Register bit 4RW0DDC3Port C Data Direction Register bit 3RW0DDC2Port C Data Direction Register bit 2RW0DDC1Port C Data Direction Register bit 1RW0DDC0Port C Data Direction Register bit 0RW0PINCPort C Input PinsThe Port C Input Pins address - PINC - is not a register, and this address enables access to the physical value on each Port C pin. When reading PORTC, the Port C Data Latch is read, and when reading PINC, the logical values present on the pins are read.0x060x26io_port.bmpNPINC6Port C Input Pins bit 6R0PINC5Port C Input Pins bit 5R0PINC4Port C Input Pins bit 4R0PINC3Port C Input Pins bit 3R0PINC2Port C Input Pins bit 2R0PINC1Port C Input Pins bit 1R0PINC0Port C Input Pins bit 0R0[PORTD:DDRD:PIND]io_port.bmpAVRSimIOPort.SimIOPortPORTDPort D Data Register0x0B0x2Bio_port.bmpNPORTD7Port D Data Register bit 7RW0PORTD6Port D Data Register bit 6RW0PORTD5Port D Data Register bit 5RW0PORTD4Port D Data Register bit 4RW0PORTD3Port D Data Register bit 3RW0PORTD2Port D Data Register bit 2RW0PORTD1Port D Data Register bit 1RW0PORTD0Port D Data Register bit 0RW0DDRDPort D Data Direction Register0x0A0x2Aio_flag.bmpNDDD7Port D Data Direction Register bit 7RW0DDD6Port D Data Direction Register bit 6RW0DDD5Port D Data Direction Register bit 5RW0DDD4Port D Data Direction Register bit 4RW0DDD3Port D Data Direction Register bit 3RW0DDD2Port D Data Direction Register bit 2RW0DDD1Port D Data Direction Register bit 1RW0DDD0Port D Data Direction Register bit 0RW0PINDPort D Input PinsThe Port D Input Pins address - PIND - is not a register, and this address enables access to the physical value on each Port D pin. When reading PORTD, the Port D Data Latch is read, and when reading PIND, the logical values present on the pins are read.0x090x29io_port.bmpNPIND7Port D Input Pins bit 7R0PIND6Port D Input Pins bit 6R0PIND5Port D Input Pins bit 5R0PIND4Port D Input Pins bit 4R0PIND3Port D Input Pins bit 3R0PIND2Port D Input Pins bit 2R0PIND1Port D Input Pins bit 1R0PIND0Port D Input Pins bit 0R0[TIMSK0:TIFR0:TCCR0A:TCCR0B:TCNT0:OCR0A:OCR0B:GTCCR]io_timer.bmpAt8pwm0_01OCR0BTimer/Counter0 Output Compare RegisterThe Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC0 pin.0x280x48io_timer.bmpNOCR0B_7RW0OCR0B_6RW0OCR0B_5RW0OCR0B_4RW0OCR0B_3RW0OCR0B_2RW0OCR0B_1RW0OCR0B_0RW0OCR0ATimer/Counter0 Output Compare RegisterThe Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC0 pin.0x270x47io_timer.bmpNOCROA_7RW0OCROA_6RW0OCROA_5RW0OCROA_4RW0OCROA_3RW0OCROA_2RW0OCROA_1RW0OCROA_0RW0TCNT0Timer/Counter0The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT0 register blocks (removes) the compare match on the following timer clock. Modifying the counter (TCNT0) while the counter is running, introduces a risk of missing a compare match between TCNT0 the OCR0 register.0x260x46io_timer.bmpNTCNT0_7RW0TCNT0_6RW0TCNT0_5RW0TCNT0_4RW0TCNT0_3RW0TCNT0_2RW0TCNT0_1RW0TCNT0_0RW0TCCR0BTimer/Counter Control Register B0x250x45io_flag.bmpYFOC0AForce Output Compare AW0FOC0BForce Output Compare BW0WGM02RW0CS02Clock SelectRW0CS01Clock SelectRW0CS00Clock SelectRW0TCCR0ATimer/Counter Control Register A0x240x44io_flag.bmpYCOM0A1Compare Output Mode, Phase Correct PWM ModeRW0COM0A0Compare Output Mode, Phase Correct PWM ModeRW0COM0B1Compare Output Mode, Fast PWmW0COM0B0Compare Output Mode, Fast PWmRW0WGM01Waveform Generation ModeRW0WGM00Waveform Generation ModeRW0TIMSK0Timer/Counter0 Interrupt Mask RegisterNA0x6Eio_flag.bmpYOCIE0BTimer/Counter0 Output Compare Match B Interrupt EnableRW0OCIE0ATimer/Counter0 Output Compare Match A Interrupt EnableRW0TOIE0Timer/Counter0 Overflow Interrupt EnableRW0TIFR0Timer/Counter0 Interrupt Flag register0x150x35io_flag.bmpYOCF0BTimer/Counter0 Output Compare Flag 0BRW0OCF0ATimer/Counter0 Output Compare Flag 0ARW0TOV0Timer/Counter0 Overflow FlagRW0GTCCRGeneral Timer/Counter Control Register0x230x43io_flag.bmpYTSMTimer/Counter Synchronization ModeWriting the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSR2 and PSR10 bits is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSR2 and PSR10 bits are cleared by hardware, and the Timer/Counters start counting simultaneouslRW0PSRSYNCPSR10Prescaler Reset Timer/Counter1 and Timer/Counter0When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers.RW0[EICRA:EIMSK:EIFR:PCICR:PCMSK2:PCMSK1:PCMSK0:PCIFR]
[PCMSK1:PCMSK0]
io_ext.bmpThe external interrupts are triggered by the INT7:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT7:0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The external inter-rupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the Exter-nal Interrupt Control Registers - EICRA (INT3:0) and EICRB (INT7:4). When the external interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT7:4 requires the presence of an I/O clock, described in “Clock Systems and their Distribution” on page 29. Low level interrupts and the edge interrupt on INT3:0 are detected asynchronously. This implies that these inter-rupts can be used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode. Note that if a level triggered interrupt is used for wake-up from Power Down Mode, the changed level must be held for some time to wake up the MCU. This makes the MCU less sensitive to noise. The changed level is sampled twice by the watchdog oscillator clock. The period of the watchdog oscillator is 1 µs (nominal) at 5.0V and 25°C. The frequency of the watchdog oscillator is voltage dependent as shown in the Electrical Characteristics section. The MCU will wake up if the input has the required level during this sampling or if it is held until the end of the start-up time. The start-up time is defined by the SUT fuses as described in “Clock Systems and their Distribution” on page 29. If the level is sampled twice by the watchdog oscillator clock but disappears before the end of the start-up time, the MCU will still wake up, but no interrupt will be generated. The required level must be held long enough for the MCU to complete the wake up to trigger the level interrupEICRAExternal Interrupt Control Register The External Interrupt Control Register A contains control bits for interrupt sense control.NA0x69io_flag.bmpYISC11External Interrupt Sense Control 1 Bit 1 The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT1 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt. RW0ISC10External Interrupt Sense Control 1 Bit 0The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT1 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt. RW0ISC01External Interrupt Sense Control 0 Bit 1 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT0 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt. RW0ISC00External Interrupt Sense Control 0 Bit 0The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT0 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt. RW0EIMSKExternal Interrupt Mask Register0x1D0x3Dio_flag.bmpYINT1External Interrupt Request 1 EnableWhen the INT1 bit is set (one)and the I-bit in the Status Register (SREG)is set (one),the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10)in the External Interrupt Control Register A (EICRA)define whether the external interrupt is activated on rising and/or falling edge of the INT1 pin or level sensed.Activity on the pin will cause an interrupt request even if INT1 is configured as an output.The corresponding interrupt of External Interrupt Request 1 is executed from the INT1 interrupt vector. RW0INT0External Interrupt Request 0 EnableWhen the INT0 bit is set (one)and the I-bit in the Status Register (SREG)is set (one),the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00)in the External Interrupt Control Register A (EICRA)define whether the external interrupt is activated on rising and/or falling edge of the INT0 pin or level sensed.Activity on the pin will cause an interrupt request even if INT0 is configured as an output.The corresponding interrupt of External Interrupt Request 0 is executed from the INT0 interrupt vector. RW0EIFRExternal Interrupt Flag Register0x1C0x3Cio_flag.bmpYINTF1External Interrupt Flag 1When an edge or logic change on the INT1 pin triggers an interrupt request,INTF1 becomes set (one).If the I-bit in SREG and the INT1 bit in EIMSK are set (one),the MCU will jump to the corresponding interrupt vector.The flag is cleared when the interrupt routine is executed.Alternatively,the flag can be cleared by writing a logical one to it.This flag is always cleared when INT0 is configured as a level interrupt. RW0INTF0External Interrupt Flag 0When an edge or logic change on the INT0 pin triggers an interrupt request,INTF0 becomes set (one).If the I-bit in SREG and the INT0 bit in EIMSK are set (one),the MCU will jump to the corresponding interrupt vector.The flag is cleared when the interrupt routine is executed.Alternatively,the flag can be cleared by writing a logical one to it.This flag is always cleared when INT0 is configured as a level interrupt. RW0PCICRNA0x68io_cpu.bmpYPCIE2R/W0PCIE1R/W0PCIE0R/W0PCMSK2Pin Change Mask Register 2Each PCINT15..8 bit selects whether pin change interrupt is enabled on the corresponding I/O pin.If PCINT15..8 is set and the PCIE1 bit in EIMSK is set,pin change interrupt is enabled on the corresponding I/O pin.If PCINT15..8 is cleared,pin change interrupt on the corresponding I/O pin is disabled. NA0x6Dio_flag.bmpYPCINT23Pin Change Enable Mask 23RW0PCINT22Pin Change Enable Mask 22RW0PCINT21Pin Change Enable Mask 21RW0PCINT20Pin Change Enable Mask 20RW0PCINT19Pin Change Enable Mask 19RW0PCINT18Pin Change Enable Mask 18RW0PCINT17Pin Change Enable Mask 17RW0PCINT16Pin Change Enable Mask 16RW0PCMSK1Pin Change Mask Register 1Each PCINT15..8 bit selects whether pin change interrupt is enabled on the corresponding I/O pin.If PCINT15..8 is set and the PCIE1 bit in EIMSK is set,pin change interrupt is enabled on the corresponding I/O pin.If PCINT15..8 is cleared,pin change interrupt on the corresponding I/O pin is disabled. NA0x6Cio_flag.bmpYPCINT14Pin Change Enable Mask 14RW0PCINT13Pin Change Enable Mask 13RW0PCINT12Pin Change Enable Mask 12RW0PCINT11Pin Change Enable Mask 11RW0PCINT10Pin Change Enable Mask 10RW0PCINT9Pin Change Enable Mask 9RW0PCINT8Pin Change Enable Mask 8RW0PCMSK0Pin Change Mask Register 0Each PCINT7..0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin.If PCINT7..0 is set and the PCIE0 bit in EIMSK is set,pin change interrupt is enabled on the corresponding I/O pin.If PCINT7..0 is cleared,pin change interrupt on the corresponding I/O pin is disabled. NA0x6Bio_flag.bmpYPCINT7Pin Change Enable Mask 7RW0PCINT6Pin Change Enable Mask 6RW0PCINT5Pin Change Enable Mask 5RW0PCINT4Pin Change Enable Mask 4RW0PCINT3Pin Change Enable Mask 3RW0PCINT2Pin Change Enable Mask 2RW0PCINT1Pin Change Enable Mask 1RW0PCINT0Pin Change Enable Mask 0RW0PCIFRPin Change Interrupt Flag Register0x1B0x3Bio_flag.bmpYPCIF2Pin Change Interrupt Flag 2When a logic change on any PCINT23..16 pin triggers an interrupt request, PCIF2 becomes set (one). If the I-bit in SREG and the PCIE2 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.RW0PCIF1Pin Change Interrupt Flag 1When a logic change on any PCINT14..8 pin triggers an interrupt request, PCIF1 becomes set (one). If the I-bit in SREG and the PCIE1 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.RW0PCIF0Pin Change Interrupt Flag 0When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0 becomes set (one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.RW0[SPDR:SPSR:SPCR]io_com.bmpSPI_01The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the device and peripheral devices or between several AVR devices. The SPI includes the following features: • Full-duplex, 3-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Seven Programmable Bit Rates • End of Transmission Interrupt Flag • Write Collision Flag Protection • Wake-up from Idle Mode • Double Speed (CK/2) Master SPI ModeSPDRSPI Data RegisterThe SPI Data Register is a read/write register used for data transfer between the register file and the SPI Shift register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read.0x2E0x4Eio_com.bmpNSPDR7SPI Data Register bit 7RWXSPDR6SPI Data Register bit 6RWXSPDR5SPI Data Register bit 5RWXSPDR4SPI Data Register bit 4RWXSPDR3SPI Data Register bit 3RWXSPDR2SPI Data Register bit 2RWXSPDR1SPI Data Register bit 1R0SPDR0SPI Data Register bit 0R0SPSRSPI Status Register0x2D0x4Dio_flag.bmpYSPIFSPI Interrupt FlagWhen a serial transfer is complete, the SPIF bit is set (one) and an interrupt is generated if SPIE in SPCR is set (one) and global interrupts are enabled. If SS is an input and is driven low when the SPI is in master mode, this will also set the SPIF flag. SPIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the SPI status register when SPIF is set (one), then accessing the SPI Data Register (SPDR).R0WCOLWrite Collision FlagThe WCOL bit is set if the SPI data register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Register when WCOL is set (one), and then accessing the SPI Data Register.R0SPI2XDouble SPI Speed BitWhen this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in master mode (see Table 71). This means that the minimum SCK period will be 2 CPU clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at f ck / 4 or lower. The SPI interface on the ATmega104 is also used for program memory and EEPROM downloading or uploading. See page 253 for serial programming and verification.RW0SPCRSPI Control Register0x2c0x4Cio_flag.bmpYSPIESPI Interrupt EnableThis bit causes the SPI interrupt to be executed if SPIF bit in the SPSR register is set and the global interrupts are enabled.RW0SPESPI EnableWhen the SPE bit is set (one), the SPI is enabled. This bit must be set to enable any SPI operations.RW0DORDData OrderWhen the DORD bit is set (one), the LSB of the data word is transmitted first. When the DORD bit is cleared (zero), the MSB of the data word is transmitted first.RW0MSTRMaster/Slave SelectThis bit selects Master SPI mode when set (one), and Slave SPI mode when cleared (zero). If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI master mode.RW0CPOLClock polarityWhen this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is low when idle. Refer to Figure 36 and Figure 37 for additional information.RW0CPHAClock PhaseRefer to Figure 36 or Figure 37 for the functionality of this bit.RW0SPR1SPI Clock Rate Select 1RW0SPR0SPI Clock Rate Select 0RW0[SREG:SPH:SPL:OSCCAL:CLKPR:SPMCSR:MCUCR:MCUSR:SMCR:GPIOR2:GPIOR1:GPIOR0:PRR]
[SPH:SPL]
io_cpu.bmpPRRPower Reduction RegisterThe Power Reduction Register, PRR, provides a method to stop the clock to individual peripherals to reduce power consumption.NA0x64io_cpu.bmpYPRTWIPower Reduction TWIR/W0PRTIM2Power Reduction Timer/Counter2R/W0PRTIM0Power Reduction Timer/Counter0R/W0PRTIM1Power Reduction Timer/Counter1R/W0PRSPIPower Reduction Serial Peripheral InterfaceR/W0PRUSART0Power Reduction USARTR/W0PRADCPower Reduction ADCR/W0OSCCALOscillator Calibration ValueWriting the calibration byte to this address will trim the internal oscillator to remove process variations from the oscillator frequency. This is done automatically during chip reset. When OSCCAL is zero, the lowest available frequency is chosen. Writing non-zero values to this register will increase the frequency of the internal oscillator. Writing $FF to the register gives the highest available frequency. The calibrated oscillator is used to time EEPROM and Flash access. If EEPROM or Flash is written, do not calibrate to more than 10% above the nominal frequency. Otherwise, the EEPROM or Flash write may fail. Note that the Oscillator is intended for calibration to 1.0 MHz, 2.0 MHz, 4.0 MHz, or 8.0MHz. Tuning to other values is not guaranteed, as indicated in Table 14NA0x66io_cpu.bmpNCAL7Oscillator Calibration Value Bit7R/W0CAL6Oscillator Calibration Value Bit6R/W0CAL5Oscillator Calibration Value Bit5R/W0CAL4Oscillator Calibration Value Bit4R/W0CAL3Oscillator Calibration Value Bit3R/W0CAL2Oscillator Calibration Value Bit2R/W0CAL1Oscillator Calibration Value Bit1R/W0CAL0Oscillator Calibration Value Bit0R/W0CLKPRClock Prescale RegisterNA0x61io_flag.bmpYCLKPCEClock Prescaler Change EnableThe CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is cleared by hardware four cycles after it is written or when CLKPS bits are written. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the CLKPCE bit.RW0CLKPS3Clock Prescaler Select Bit 3These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used.RW0CLKPS2Clock Prescaler Select Bit 2These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used.RW0CLKPS1Clock Prescaler Select Bit 1These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used.RW0CLKPS0Clock Prescaler Select Bit 0These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used.RW0SREGStatus Register0x3F0x5Fio_sreg.bmpYIGlobal Interrupt EnableThe global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable bit is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts.RW0TBit Copy StorageThe bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction.RW0HHalf Carry FlagThe half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed information.RW0SSign BitThe S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruc-tion Set Description for detailed information.RW0VTwo's Complement Overflow FlagThe two’s complement overflow flag V supports two’s complement arithmetics. See the Instruction Set Description for detailed information.RW0NNegative FlagThe negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.RW0ZZero FlagThe zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.RW0CCarry FlagThe carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software.RW0SPHStack Pointer HighThe general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the AT90S4414/8515 supports up to 64 kB external SRAM, all 16-bits are used. The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or return from interrupt R0x3E0x5Eio_sph.bmpNSP10Stack pointer bit 10RW0SP9Stack pointer bit 9RW0SP8Stack pointer bit 8RW0SPLStack Pointer LowThe general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the AT90S4414/8515 supports up to 64 kB external SRAM, all 16-bits are used. The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or return from interrupt 0x3D0x5Dio_sph.bmpNSP7Stack pointer bit 7RW0SP6Stack pointer bit 6RW0SP5Stack pointer bit 5RW0SP4Stack pointer bit 4RW0SP3Stack pointer bit 3RW0SP2Stack pointer bit 2RW0SP1Stack pointer bit 1RW0SP0Stack pointer bit 0RW0SPMCSRStore Program Memory Control Register0x370x57io_cpu.bmpYSPMIESPM Interrupt EnableWhen the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN bit in the SPMCR register is cleared.R/W0RWWSBRead-While-Write Section BusyR0RWWSRERead-While-Write section read enableR/W0BLBSETBoot Lock Bit SetIf this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles sets Boot Lock bits, according to the data in R0. The data in R1 and the address in the Z pointer are ignored. The BLBSET bit will automatically be cleared upon completion of the lock bit set, or if no SPM instruction is executed within four clock cycles.R/W0PGWRTPage WriteIf this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.R/W0PGERSPage EraseIf this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page erase. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a page erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.R/W0SELFPRGENSelf Programming EnableThe explanation is to long to include here. Please refer to the printed documentation.R/W0MCUCRMCU Control RegisterThe MCU Control Register contains control bits for general MCU functions.0x350x55io_flag.bmpYPUDRW0IVSELRW0IVCERW0MCUSRMCU Status RegisterThe MCU Status Register provides information on which reset source caused a MCU reset.0x340x54io_flag.bmpYWDRFWatchdog Reset FlagThis bit is set if a watchdog reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.R/W0BORFBrown-out Reset FlagThis bit is set if a brown-out reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.R/W0EXTRFEXTREFExternal Reset FlagThis bit is set if an external reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.R/W0PORFPower-on reset flagThis bit is set if a power-on reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the reset flags to identify a reset condition, the user should read and then reset the MCUCSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags.R/W0SMCR0x330x53io_flag.bmpYSM2RW0SM1RW0SM0RW0SERW0GPIOR2General Purpose I/O Register 20x2B0x4Bio_flag.bmpNGPIOR27RW0GPIOR26RW0GPIOR25RW0GPIOR24RW0GPIOR23GPIOR22RW0GPIOR21RW0GPIOR20RW0GPIOR1General Purpose I/O Register 10x2A0x4Aio_flag.bmpNGPIOR17RW0GPIOR16RW0GPIOR15RW0GPIOR14RW0GPIOR13GPIOR12RW0GPIOR11RW0GPIOR10RW0GPIOR0General Purpose I/O Register 00x1E0x3Eio_flag.bmpNGPIOR07RW0GPIOR06RW0GPIOR05RW0GPIOR04RW0GPIOR03GPIOR02RW0GPIOR01RW0GPIOR00RW0[WDTCSR]io_watch.bmpWDTCSRWatchdog Timer Control RegisterNA0x60io_flag.bmpYWDIFWatchdog Timeout Interrupt FlagRW0WDIEWatchdog Timeout Interrupt EnableRW0WDP3Watchdog Timer Prescaler Bit 3RW0WDCEWatchdog Change EnableRW0WDEWatch Dog EnableWhen the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdogRW0WDP2Watch Dog Timer Prescaler bit 2RW0WDP1Watch Dog Timer Prescaler bit 1RW0WDP0Watch Dog Timer Prescaler bit 0RW0[EEARL:EEARH:EEDR:EECR]io_cpu.bmpEEPROM Read/Write Access. The EEPROM access registers are accessible in the I/O space. The write access time for the EEPROM is given in Table 1. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page 19. for details on how to avoid problems in these situations.In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When theEEPROM is written, the CPU is halted for two clock cycles before the next instruction is executEEARHEEPROM Address Register High Byte0x220x42io_cpu.bmpNEEAR8EEPROM Read/Write Access Bit 0RW0EEARLEEPROM Address Register Low Byte0x210x41io_cpu.bmpNEEAR7EEPROM Read/Write Access Bit 7RW0EEAR6EEPROM Read/Write Access Bit 6RW0EEAR5EEPROM Read/Write Access Bit 5RW0EEAR4EEPROM Read/Write Access Bit 4RW0EEAR3EEPROM Read/Write Access Bit 3RW0EEAR2EEPROM Read/Write Access Bit 2RW0EEAR1EEPROM Read/Write Access Bit 1RW0EEAR0EEPROM Read/Write Access Bit 0RW0EEDREEPROM Data RegisterFor the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.0x200x40io_cpu.bmpNEEDR7EEPROM Data Register bit 7RW0EEDR6EEPROM Data Register bit 6RW0EEDR5EEPROM Data Register bit 5RW0EEDR4EEPROM Data Register bit 4RW0EEDR3EEPROM Data Register bit 3RW0EEDR2EEPROM Data Register bit 2RW0EEDR1EEPROM Data Register bit 1RW0EEDR0EEPROM Data Register bit 0RW0EECREEPROM Control Register0x1F0x3Fio_flag.bmpYEEPM1EEPROM Programming Mode Bit 1The EEPROM Programming mode bit setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in Table 2. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.RWXEEPM0EEPROM Programming Mode Bit 0The EEPROM Programming mode bit setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in Table 2. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.RWXEERIEEEPROM Ready Interrupt EnableEEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared.RW0EEMPEEEPROM Master Write EnableThe EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is written to one, writing EEWE to one within 4 clock cycles will write data to the EEPROM at the selected address. If EEMWE is zero, writing EEWE to one will have no effect. When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure.RW0EEPEEEPROM Write EnableThe EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential): 1. Wait until EEWE becomes zero. 2. Wait until SPMEN in SPMCR becomes zero. 3. Write new EEPROM address to EEAR (optional). 4. Write new EEPROM data to EEDR (optional). 5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR. 6. Within four clock cycles after setting EEMWE, write a logical one to EEWE. The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a boot loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See “Boot Loader Support - Read While Write self-programming” on page 228 for details about boot programming. Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR regis-ter will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the 4 last steps to avoid these problems. When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruc-tion is executedRWXEEREEEPROM Read EnableThe EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR register. The calibrated oscillator is used to time the EEPROM accesses. Table 1 lists the typical programming time for EEPROM access from the CPURW0[ICE50:JTAGICEmkII:SIMULATOR:STK500:STK500_2:AVRISPmkII:AVRDragon]0x050x0F0x0F0x0F0x050x050x050x050x050x050x050x050x050x0F0x0F0x0F0x150x140x140x000004FF0x000000000x000000000x000000000x000001FF0x00003FFF0x00001FFF0x00001FFF0x00001FFF0x00001FFF0x000004FF0x0000FFFF0x000001FF0x000000000x000000000x000000000x0023FFFF0x00000FFF0x000000FF0xDF0xF90x620xff0x660xc7ATmega48.bin0x020x001000000240000002 ; INTOSC = 1, INTRC=2;EXTCLK=41 ;NOTUSE = 1, EXTERNAL = 4, INTERNAL = 2 1 00x000x000x000x8080x000600000x00060000Boot Size 128 Words, 2 pages, $1F80-$1FFF, Boot reset $1F800x000600000x00040000Boot Size 256 Words, 4 pages, $1F00-$1FFF, Boot reset $1F000x000600000x00020000Boot Size 512 Words, 8 pages, $1E00-$1FFF, Boot reset $1E000x000600000x00000000Boot Size 1024 Words, 16 pages, $1C00-$1FFF, Boot reset $1C000x000100000x00010000Application reset, address $00x000100000x00000000Boot loader reset0x0C0000000x0C000000No restrictions for SPM or (E)LPM0x0C0000000x08000000No write to the Application section0x0C0000000x00000000No write to Application section, No read from the Application section0x0C0000000x04000000No read from the Application section0x300000000x30000000No restrictions for SPM or (E)LPM0x300000000x20000000No write to the Boot Loader section0x300000000x00000000No write to Boot Loader section, No read from the Boot Loader section0x300000000x10000000No read from the Boot Loader section0x000000400x00000000CKOUT fuse0x000000400x00000040CKOUT fuse0x000000310x000000001K CK, 14CK0x000000310x000000101K CK, 14CK + 4.1 ms0x000000310x000000201K CK, 14CK + 65 ms0x000000310x00000001321K CK, 14CK0x000000310x0000001132K CK, 14CK + 4.1 ms0x000000310x0000002132K CK, 14CK + 65 ms0x000000310x00000000258 CK, 14CK + 4.1 ms 0x000000310x00000010258 CK, 14CK +65 ms0x000000310x000000201K CK, 14CK0x000000310x000000301K CK, 14CK + 4.1 ms0x000000310x000000011K CK, 14CK + 65 ms0x000000310x0000001116K CK, 14CK0x000000310x0000002116K CK, 14CK + 4.1 ms0x000000310x0000003116K CK, 14CK + 65 ms0x000000300x000000006 CK, 14CK0x000000300x000000106 CK, 14CK + 4.1 ms0x000000300x000000206 CK, 14CK + 65 ms0x000000300x000000006 CK, 14 CK0x000000300x000000106 CK, 14CK + 4.1 ms0x000000300x000000206 CK, 14CK + 65 ms0x0000000e0x000000040x0000000e0x000000060x0000000f0x000000028.00x0000000f0x000000000x000010000x00000000Watchdog always ON0x000010000x00001000Watchdog disabled0x000080000x00000000RSTDSBL Fuse 0x000080000x00008000RSTDSBL0x000007000x00000700BOD disabled0x000007000x00000600BOD enabled, 1.8 V0x000007000x00000500BOD enabled, 2.7 V0x000007000x00000400BOD enabled, 4.3 V80x000000800x00000000CKDIV8 Fuse0x000000800x00000080CKDIV8 Fuse0x9406DebugWire0xF8,0x0F,0xE0,0xF8,0xFF,0x3D,0xB9,0xE00xB0,0x0D,0x00,0xE0,0xFF,0x1D,0xB8,0xE00X00,0X00,0X00,0X00,0X00,0X00,0X00,0X000X00,0X00,0X00,0X00,0X00,0X00,0X00,0X000x53,0xFB,0x01,0xDF,0xF7,0x0F,0x00,0x00,0x00,0x00,0x5F,0x3F,0x37,0x00,0x00,0x00,0x00,0x00,0x00,0x000x00,0xFB,0x01,0xD8,0xF7,0x0F,0x00,0x00,0x00,0x00,0x5F,0x2F,0x36,0x00,0x00,0x00,0x00,0x00,0x00,0x000x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x000x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x000x000X000X0012840x1F800x1F800x1F000x1E000x1C000xC60x40000x0000,320x0020,640x000x400x000x000x200x000xBD,0xF2,0xBD,0xE1,0xBB,0xCF,0xB4,0x00,0xBE,0x01,0xB6,0x01,0xBC,0x00,0xBB,0xBF,0x99,0xF9,0xBB,0xAF0xB6,0x01,0x110x3e0x3d0x310x000x000x000x1F800x000x3fAVRSimCoreV2.SimCoreV2AVRSimMemory8bit.SimMemory8bitAVRSimInterrupt.SimInterrupt0x2c018AVRSimIOPort.SimIOPortYAVRSimIOPort.SimIOPortYAVRSimIOPort.SimIOPortYAVRSimIOPinChangeInterrupt.SimIOPinChangeInterrupt0x060x480x010x3B0x010x4b0x030xffAVRSimIOPinChangeInterrupt.SimIOPinChangeInterrupt0x080x480x020x1B0x020x060x7f0x4cAVRSimIOPinChangeInterrupt.SimIOPinChangeInterrupt0x0a0x480x040x1B0x040x090xff0x4dAVRSimIOExtInterrupt.SimIOExtInterrupt0x020x1D0x010x1C0x010x090x040x490x03AVRSimIOExtInterrupt.SimIOExtInterrupt0x040x1D0x020x1C0x020x090x080x490x0cAvrSimIOtim8pwmsync2.tim8pwmsync20x0200x01C0x01EPORTDPORTD65PIND4AVRSimIOTimert16pwm1.SimIOTimert16pwm10x140x0160x0180x01A0x090x200x030x010x050x020x050x04AvrMasterTimer.MasterTimer0x0E0x100x012PORTB3PORTD31:8:32:64:128:256:1024AVRSimIOSPM.SimIOSPM0x032AVRSimIOSpi.SimIOSpi0x0220x030x200x030x100x030x080x030x040x04AVRSimIOUsart.SimIOUsart0x0240x0280x0260x090x020x090x01AvrMasterTimer.MasterTimer12810x00C2048:4096:8192:16384:32768:65536:131072:262144:524288:1048576AVRSimAC.SimIOAC0x2EAVRSimADC.SimADC0x2AAvrSimTWI.SimTWI0x300x990xff0xe10xff0x861110xFF0xFF0xFF012001002532030x53114510x41128100x400x4C0x000x000x000x41450xC10xC20x000x000x0025625644440x0E 0x1E 0x0F 0x1F 0x2E 0x3E 0x2F 0x3F 0x4E 0x5E 0x4F 0x5F 0x6E 0x7E 0x6F 0x7F 0x66 0x76 0x67 0x77 0x6A 0x7A 0x6B 0x7B 0xBE 0xFD 0x00 0x01 0x00 0x00 0x00 0x001000511510151501050x0F25625650x052562560505