[ADMIN:FUSE:INTERRUPT_VECTOR:MEMORY:POWER:PACKAGE:CORE:LOCKBIT:PROGRAMMING:IO_MODULE:ICE_SETTINGS] ATmega406 1MHZ 180 RELEASED $1E $95 $07 [LOW:HIGH] 8 WDTON Watchdog Timer Always On 1 EESAVE EEPROM memory is preserved through the chip erase 1 BOOTSZ1 Select boot size 0 BOOTSZ0 Select boot size 0 BOOTRST Select reset vector 1 SUT1 Select start-up time 1 SUT0 Select start-up time 0 CKSEL Clock Selection 1 13 0x80 0x00 Watchdog timer always on; [WDTON=0] 0x40 0x00 Preserve EEPROM memory through the Chip Erase cycle; [EESAVE=0] 0x30 0x30 Boot Flash section size=256 words Boot start address=$4F00; [BOOTSZ=11] 0x30 0x20 Boot Flash section size=512 words Boot start address=$4E00; [BOOTSZ=10] 0x30 0x10 Boot Flash section size=1024 words Boot start address=$4C00; [BOOTSZ=01] 0x30 0x00 Boot Flash section size=2048 words Boot start address=$4800; [BOOTSZ=00] ; default value 0x08 0x00 Boot Reset vector Enabled (default address=$0000); [BOOTRST=0] 0x07 0x00 CKSEL; Start-up time: 14 CK + 0 ms; [CKSEL=0 SUT=00] 0x07 0x02 CKSEL; Start-up time: 14 CK + 3.9 ms; [CKSEL=0 SUT=01] 0x07 0x04 CKSEL; Start-up time: 14 CK + 62.5 ms; [CKSEL=0 SUT=10] 0x07 0x01 CKSEL; Start-up time: 14 CK + 0 ms; [CKSEL=1 SUT=00] 0x07 0x03 CKSEL; Start-up time: 14 CK + 3.9 ms; [CKSEL=1 SUT=01] 0x07 0x05 CKSEL; Start-up time: 14 CK + 62.5 ms; [CKSEL=1 SUT=10] 2 OCDEN Enable OCD 1 JTAGEN Enable JTAG 0 2 0x02 0x00 On-Chip Debug Enabled; [OCDEN=0] 0x01 0x00 JTAG Interface Enabled; [JTAGEN=0] 23 $000 RESET External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset $002 BPINT Battery Protection Interrupt $004 INT0 External Interrupt Request 0 $006 INT1 External Interrupt Request 1 $008 INT2 External Interrupt Request 2 $00A INT3 External Interrupt Request 3 $00C PCINT0 Pin Change Interrupt 0 $00E PCINT1 Pin Change Interrupt 1 $010 WDT Watchdog Timeout Interrupt $0012 WAKE_UP Wakeup timer overflow $014 TIM1_COMP Timer/Counter 1 Compare Match $016 TIM1_OVF Timer/Counter 1 Overflow $018 TIM0_COMPA Timer/Counter0 Compare A Match $01A TIM0_COMPB Timer/Counter0 Compare B Match $001C TIM0_OVF Timer/Counter0 Overflow $001E TWI_BUS_CD Two-Wire Bus Connect/Disconnect $0020 TWI Two-Wire Serial Interface $0022 VADC Voltage ADC Conversion Complete $0024 CCADC_CONV Coulomb Counter ADC Conversion Complete $0026 CCADC_REG_CUR Coloumb Counter ADC Regular Current $0028 CCADC_ACC Coloumb Counter ADC Accumulator $02A EE READY EEPROM Ready $02C SPM READY Store Program Memory Ready AVRSimMemory8bit.SimMemory8bit 40960 512 2048 $100 0 N/A $00 $3F $60 $FF $20 $FF NA 0xF8 0x010x02 NA 0xF7 0x010x020x040x08 NA 0xF6 0x010x020x040x080x100x200x400x80 NA 0xF5 0x010x020x040x080x100x200x400x80 NA 0xF4 0x010x020x040x08 NA 0xF3 0x010x020x040x080x100x20 NA 0xF2 0x010x020x040x080x100x200x400x80 NA 0xF1 0x010x020x040x08 NA 0xF0 0x010x020x040x080x100x20 NA 0xE9 0x010x020x040x080x100x200x400x80 NA 0xE8 0x010x020x040x080x100x200x400x80 NA 0xE7 0x010x020x040x080x100x200x400x80 NA 0xE6 0x010x020x040x080x100x200x400x80 NA 0xE5 0x010x020x040x100x200x40 NA 0xE4 0x010x020x040x080x100x200x80 NA 0xE3 0x010x020x040x080x100x200x400x80 NA 0xE2 0x010x020x040x080x100x200x400x80 NA 0xE1 0x010x020x040x080x100x200x400x80 NA 0xE0 0x010x020x040x080x100x200x400x80 NA 0xD1 0x010x020x040x080x100x200x400x80 NA 0xD0 0x010x020x040x080x100x200x80 NA 0xC0 0x010x02 NA 0xBE 0x010x020x040x400x80 NA 0xBD 0x020x040x080x100x200x400x80 NA 0xBC 0x010x040x080x100x200x400x80 NA 0xBB 0x010x020x040x080x100x200x400x80 NA 0xBA 0x010x020x040x080x100x200x400x80 NA 0xB9 0x010x020x080x100x200x400x80 NA 0xB8 0x010x020x040x080x100x200x400x80 NA 0x89 0x010x020x040x080x100x200x400x80 NA 0x88 0x010x020x040x080x100x200x400x80 NA 0x85 0x010x020x040x080x100x200x400x80 NA 0x84 0x010x020x040x080x100x200x400x80 NA 0x81 0x010x020x040x08 NA 0x7E 0x010x020x040x08 NA 0x7C 0x010x020x040x08 NA 0x7A 0x010x020x040x08 NA 0x79 0x010x020x040x08 NA 0x78 0x010x020x040x080x100x200x400x80 NA 0x6F 0x010x02 NA 0x6E 0x010x020x04 NA 0x6C 0x010x020x040x080x100x200x400x80 NA 0x6B 0x010x020x040x080x100x200x400x80 NA 0x69 0x010x020x040x080x100x200x400x80 NA 0x68 0x010x02 NA 0x66 0x010x020x040x080x100x200x400x80 NA 0x64 0x010x020x040x08 NA 0x62 0x010x020x040x080x100x200x400x80 NA 0x60 0x010x020x040x080x100x200x400x80 0x3F 0x5F 0x010x020x040x080x100x200x400x80 0x3E 0x5E 0x010x020x040x080x100x200x400x80 0x3D 0x5D 0x010x020x040x080x100x200x400x80 0x37 0x57 0x010x020x040x080x100x200x400x80 0x35 0x55 0x010x020x100x80 0x34 0x54 0x010x020x040x080x10 0x33 0x53 0x010x020x040x08 0x31 0x51 0x2B 0x4B 0x010x020x040x080x100x200x400x80 0x2A 0x4A 0x010x020x040x080x100x200x400x80 0x28 0x48 0x010x020x040x080x100x200x400x80 0x27 0x47 0x010x020x040x080x100x200x400x80 0x26 0x46 0x010x020x040x080x100x200x400x80 0x25 0x45 0x010x020x040x080x400x80 0x24 0x44 0x010x020x100x200x400x80 0x23 0x43 0x010x80 0x22 0x42 0x01 0x21 0x41 0x010x020x040x080x100x200x400x80 0x20 0x40 0x010x020x040x080x100x200x400x80 0x1F 0x3F 0x010x020x040x080x100x20 0x1E 0x3E 0x010x020x040x080x100x200x400x80 0x1D 0x3D 0x010x020x040x08 0x1C 0x3C 0x010x020x040x08 0x1B 0x3B 0x010x02 0x16 0x36 0x010x02 0x15 0x35 0x010x020x04 0x0B 0x2B 0x010x02 0x0A 0x2A 0x010x02 0x09 0x29 0x010x02 0x08 0x28 0x01 0x05 0x25 0x010x020x040x080x100x200x400x80 0x04 0x24 0x010x020x040x080x100x200x400x80 0x03 0x23 0x010x020x040x080x100x200x400x80 0x02 0x22 0x010x020x040x080x100x200x400x80 0x01 0x21 0x010x020x040x080x100x200x400x80 0x00 0x20 0x010x020x040x080x100x200x400x80 $4800 $4FFF $0 $47FF 64 256 4 0 $4F00 $4F00 512 8 0 $4E00 $4E00 1024 16 0 $4C00 $4C00 2048 32 0 $4800 $4800 1MHz 85C TBD mA TBD mA TBD uA [LQFP] 48 [SGND] [PA0:ADC0:PCINT0] [PA1:ADC1:PCINT1] [PA2:ADC2:PCINT2] [PA3:ADC3:PCINT3] [VREG] [VCC] [GND] [PA4:ADC4:INT0:PCINT4] [PA5:INT1:PCINT5] [PA6:INT2:PCINT6] [PA7:INT3:PCINT7] ['RESET] [XTAL1] [XTAL2] [GND] [PB0:TDO:PCINT8] [PB1:TDI:PCINT9] [PB2:TMS:PCINT10] [PB3:TCK:PCINT11] [PB4:PCINT12] [PB5:PCINT13] [SCL] [SDA] [PB6:OC0A:PCINT14] [PB7:OC0B:PCINT15] [PD0:T0] [PD1] [GND] [PC0] [BATT] [OPC] [OC] [VFET] [OD] [PVT] [GND] [PV4] [PV3] [PV2] [PV1] [NV] [VREF] [VREFGND] [PPI] [PI] [NI] [NNI] V2E AVRSimCoreV2.SimCoreV2 [] [] [] 32 $00 $1B $1A $1D $1C $1F $1E [LB1 = 1 : LB2 = 1] No memory lock features enabled. [LB1 = 0 : LB2 = 1] Further programming of Flash and EEPROM is enabled. [LB1 = 0 : LB2 = 0] Same as previous, but verify is also disabled 6 11 0x03 0x03 Mode 1: No memory lock features enabled 0x03 0x02 Mode 2: Further programming disabled 0x03 0x00 Mode 3: Further programming and verification disabled 0x0C 0x0C Application Protection Mode 1: No lock on SPM and LPM in Application Section 0x0C 0x08 Application Protection Mode 2: SPM prohibited in Application Section 0x0C 0x00 Application Protection Mode 3: LPM and SPM prohibited in Application Section 0x0C 0x04 Application Protection Mode 4: LPM prohibited in Application Section 0x30 0x30 Boot Loader Protection Mode 1: No lock on SPM and LPM in Boot Loader Section 0x30 0x20 Boot Loader Protection Mode 2: SPM prohibited in Boot Loader Section 0x30 0x00 Boot Loader Protection Mode 3: LPM and SPM prohibited in Boot Loader Section 0x30 0x10 Boot Loader Protection Mode 4: LPM prohibited in Boot Loader Section LB1 Lock bit LB2 Lock bit BLB01 Boot Lock bit BLB02 Boot Lock bit BLB11 Boot lock bit BLB12 Boot lock bit 0x00,4.0 MHz 128 4 [AD_CONVERTER:EXTERNAL_INTERRUPT:TIMER_COUNTER_1:WAKEUP_TIMER:BATTERY_PROTECTION:FET:COULOMB_COUNTER:CELL_BALANCING:CPU:WATCHDOG:TIMER_COUNTER_0:PORTA:PORTB:PORTC:PORTD:BOOT_LOAD:TWI:BANDGAP:EEPROM] [VADMUX:VADCH:VADCL:VADCSR] [VADCH:VADCL] io_analo.bmp 12-bit resolution Sigmal-Delta ADC with +/-1 LSB Accuracy. 512 us conversion time. VADMUX The VADC multiplexer Selection Register NA 0x7C io_analo.bmp Y VADMUX3 Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). RW 0 VADMUX2 Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). RW 0 VADMUX1 Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). RW 0 VADMUX0 Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). RW 0 VADCH VADC Data Register High Byte When VADCL is read, the Voltage ADC Data Register is not updated until VADCH is read. Consequently if no more than 8-bit precision is required, it is sufficient to read VADCH. Otherwise, VADCL must be read first, then VADCH. NA 0x79 io_analo.bmp N VADC11 ADC Data Register High Byte Bit 3 R 0 VADC10 ADC Data Register High Byte Bit 2 R 0 VADC9 ADC Data Register High Byte Bit 1 R 0 VADC8 ADC Data Register High Byte Bit 0 R 0 VADCL VADC Data Register Low Byte When VADCL is read, the Voltage ADC Data Register is not updated until VADCH is read. Consequently if no more than 8-bit precision is required, it is sufficient to read VADCH. Otherwise, VADCL must be read first, then VADCH. NA 0x78 io_analo.bmp N VADC7 ADC Data Register Low Byte Bit 7 R 0 VADC6 ADC Data Register Low Byte Bit 6 R 0 VADC5 ADC Data Register Low Byte Bit 5 R 0 VADC4 ADC Data Register Low Byte Bit 4 R 0 VADC3 ADC Data Register Low Byte Bit 3 R 0 VADC2 ADC Data Register Low Byte Bit 2 R 0 VADC1 ADC Data Register Low Byte Bit 1 R 0 VADC0 ADC Data Register Low Byte Bit 0 R 0 VADCSR The VADC Control and Status register NA 0x7A io_flag.bmp Y VADEN VADC Enable Writing this bit to one enables V-ADC Conversion. By writing it to zero, the V-ADC is turned off. Turning the V-ADC off while a conversion is in progress will terminate this conversion RW 0 VADSC VADC Satrt Conversion Write this bit to one to start a new conversion of the selected channel. VADSC will read as one as long as the conversion is not finished. When the conversion is complete, it returns to zero. Writing zero to this bit has no effect. RW 0 VADCCIF VADC Conversion Complete Interrupt Flag This bit is set when a V-ADC conversion completes and the data registers are updated.V-ADC Conversion complete Interrupt is executed if the VADCCIE bit and the I-bit in S-REG are set. VADCCIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, VADCCIF is cleared by writing a logical one to the flag. Beware that if doing a Read-Modify-Write on VADCSR, a pending interrupt can be disabled. RW 0 VADCCIE VADC Conversion Complete Interrupt Enable When this bit is written to one and the I-Bit in SREG is set, the V-ADC Conversion Complete Interrupt is activated RW 0 [EICRA:EIMSK:EIFR:PCICR:PCIFR:PCMSK1:PCMSK0] [PCMSK1:PCMSK0] io_ext.bmp The external interrupts are triggered by the INT7:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT7:0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The external inter-rupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the Exter-nal Interrupt Control Registers - EICRA (INT3:0) and EICRB (INT7:4). When the external interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT7:4 requires the presence of an I/O clock, described in “Clock Systems and their Distribution” on page 29. Low level interrupts and the edge interrupt on INT3:0 are detected asynchronously. This implies that these inter-rupts can be used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode. Note that if a level triggered interrupt is used for wake-up from Power Down Mode, the changed level must be held for some time to wake up the MCU. This makes the MCU less sensitive to noise. The changed level is sampled twice by the watchdog oscillator clock. The period of the watchdog oscillator is 1 µs (nominal) at 5.0V and 25°C. The frequency of the watchdog oscillator is voltage dependent as shown in the Electrical Characteristics section. The MCU will wake up if the input has the required level during this sampling or if it is held until the end of the start-up time. The start-up time is defined by the SUT fuses as described in “Clock Systems and their Distribution” on page 29. If the level is sampled twice by the watchdog oscillator clock but disappears before the end of the start-up time, the MCU will still wake up, but no interrupt will be generated. The required level must be held long enough for the MCU to complete the wake up to trigger the level interru EICRA External Interrupt Control Register The External Interrupt Control Register A contains control bits for interrupt sense control. NA 0x69 io_flag.bmp Y ISC31 External Interrupt Sense Control 3 Bit 1 The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT1 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt. RW 0 ISC30 External Interrupt Sense Control 3 Bit 0 The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT1 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt. RW 0 ISC21 External Interrupt Sense Control 2 Bit 1 The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT1 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt. RW 0 ISC20 External Interrupt Sense Control 2 Bit 0 The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT1 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt. RW 0 ISC11 External Interrupt Sense Control 1 Bit 1 The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT1 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt. RW 0 ISC10 External Interrupt Sense Control 1 Bit 0 The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT1 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt. RW 0 ISC01 External Interrupt Sense Control 0 Bit 1 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT0 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt. RW 0 ISC00 External Interrupt Sense Control 0 Bit 0 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT0 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt. RW 0 EIMSK External Interrupt Mask Register 0x1D 0x3D io_flag.bmp Y INT3 External Interrupt Request 1 Enable When the INT3 bit is set (one)and the I-bit in the Status Register (SREG)is set (one),the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10)in the External Interrupt Control Register A (EICRA)define whether the external interrupt is activated on rising and/or falling edge of the INT1 pin or level sensed.Activity on the pin will cause an interrupt request even if INT1 is configured as an output.The corresponding interrupt of External Interrupt Request 1 is executed from the INT1 interrupt vector. RW 0 INT2 External Interrupt Request 1 Enable When the INT2 bit is set (one)and the I-bit in the Status Register (SREG)is set (one),the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10)in the External Interrupt Control Register A (EICRA)define whether the external interrupt is activated on rising and/or falling edge of the INT1 pin or level sensed.Activity on the pin will cause an interrupt request even if INT1 is configured as an output.The corresponding interrupt of External Interrupt Request 1 is executed from the INT1 interrupt vector. RW 0 INT1 External Interrupt Request 1 Enable When the INT1 bit is set (one)and the I-bit in the Status Register (SREG)is set (one),the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10)in the External Interrupt Control Register A (EICRA)define whether the external interrupt is activated on rising and/or falling edge of the INT1 pin or level sensed.Activity on the pin will cause an interrupt request even if INT1 is configured as an output.The corresponding interrupt of External Interrupt Request 1 is executed from the INT1 interrupt vector. RW 0 INT0 External Interrupt Request 0 Enable When the INT0 bit is set (one)and the I-bit in the Status Register (SREG)is set (one),the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00)in the External Interrupt Control Register A (EICRA)define whether the external interrupt is activated on rising and/or falling edge of the INT0 pin or level sensed.Activity on the pin will cause an interrupt request even if INT0 is configured as an output.The corresponding interrupt of External Interrupt Request 0 is executed from the INT0 interrupt vector. RW 0 EIFR External Interrupt Flag Register 0x1C 0x3C io_flag.bmp Y INTF3 External Interrupt Flag 3 When an edge or logic change on the INT1 pin triggers an interrupt request,INTF1 becomes set (one).If the I-bit in SREG and the INT1 bit in EIMSK are set (one),the MCU will jump to the corresponding interrupt vector.The flag is cleared when the interrupt routine is executed.Alternatively,the flag can be cleared by writing a logical one to it.This flag is always cleared when INT0 is configured as a level interrupt. RW 0 INTF2 External Interrupt Flag 2 When an edge or logic change on the INT1 pin triggers an interrupt request,INTF1 becomes set (one).If the I-bit in SREG and the INT1 bit in EIMSK are set (one),the MCU will jump to the corresponding interrupt vector.The flag is cleared when the interrupt routine is executed.Alternatively,the flag can be cleared by writing a logical one to it.This flag is always cleared when INT0 is configured as a level interrupt. RW 0 INTF1 External Interrupt Flag 1 When an edge or logic change on the INT1 pin triggers an interrupt request,INTF1 becomes set (one).If the I-bit in SREG and the INT1 bit in EIMSK are set (one),the MCU will jump to the corresponding interrupt vector.The flag is cleared when the interrupt routine is executed.Alternatively,the flag can be cleared by writing a logical one to it.This flag is always cleared when INT0 is configured as a level interrupt. RW 0 INTF0 External Interrupt Flag 0 When an edge or logic change on the INT0 pin triggers an interrupt request,INTF0 becomes set (one).If the I-bit in SREG and the INT0 bit in EIMSK are set (one),the MCU will jump to the corresponding interrupt vector.The flag is cleared when the interrupt routine is executed.Alternatively,the flag can be cleared by writing a logical one to it.This flag is always cleared when INT0 is configured as a level interrupt. RW 0 PCICR Pin Change Interrupt Control Register NA 0x68 io_flag.bmp Y PCIE1 Pin Change Interrupt Enable 1 When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 1 is enabled. Any change on any enabled PCINT15..8 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI1 Interrupt Vector. PCINT15..8 pins are enabled individually by the PCMSK1 Register. RW 0 PCIE0 Pin Change Interrupt Enable 0 When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0 Interrupt Vector. PCINT7..0 pins are enabled individually by the PCMSK0 Register. RW 0 PCIFR Pin Change Interrupt Flag Register 0x1B 0x3B io_flag.bmp Y PCIF1 Pin Change Interrupt Flag 1 When a logic change on any PCINT15..8 pin triggers an interrupt request, PCIF1 becomes set (one). If the I-bit in SREG and the PCIE1 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. RW 0 PCIF0 Pin Change Interrupt Flag 1 When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0 becomes set (one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. RW 0 PCMSK1 Pin Change Enable Mask Register 1 Each PCINT15..8-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT15..8 is set and the PCIE1 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT15..8 is cleared, pin change interrupt on the corresponding I/O pin is disabled. NA 0x6C io_flag.bmp N PCINT15 Pin Change Enable Mask 15 RW 0 PCINT14 Pin Change Enable Mask 14 RW 0 PCINT13 Pin Change Enable Mask 13 RW 0 PCINT12 Pin Change Enable Mask 12 RW 0 PCINT11 Pin Change Enable Mask 11 RW 0 PCINT10 Pin Change Enable Mask 10 RW 0 PCINT9 Pin Change Enable Mask 9 RW 0 PCINT8 Pin Change Enable Mask 8 RW 0 PCMSK0 Pin Change Enable Mask Register 0 Each PCINT7..0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is cleared, pin change interrupt on the corresponding I/O pin is disabled. NA 0x6B io_flag.bmp N PCINT7 Pin Change Enable Mask 7 RW 0 PCINT6 Pin Change Enable Mask 6 RW 0 PCINT5 Pin Change Enable Mask 5 RW 0 PCINT4 Pin Change Enable Mask 4 RW 0 PCINT3 Pin Change Enable Mask 3 RW 0 PCINT2 Pin Change Enable Mask 2 RW 0 PCINT1 Pin Change Enable Mask 1 RW 0 PCINT0 Pin Change Enable Mask 0 RW 0 [TCCR1B:TCNT1H:TCNT1L:OCR1AL:OCR1AH:TIMSK1:TIFR1:GTCCR] [TCNT1H:TCNT1L];[OCR1AH:OCR1AL] io_timer.bmp TCCR1B Timer/Counter1 Control Register B NA 0x81 io_flag.bmp Y CTC1 Clear Timer/Counter on Compare Match RW 0 CS12 Clock Select1 bit 2 RW 0 CS11 Clock Select1 bit 1 RW 0 CS10 Clock Select1 bit 0 RW 0 TCNT1H Timer Counter 1 High Byte NA 0x85 io_timer.bmp N TCNT1H7 Timer Counter 1 High Byte bit 7 RW 0 TCNT1H6 Timer Counter 1 High Byte bit 6 RW 0 TCNT1H5 Timer Counter 1 High Byte bit 5 RW 0 TCNT1H4 Timer Counter 1 High Byte bit 4 RW 0 TCNT1H3 Timer Counter 1 High Byte bit 3 RW 0 TCNT1H2 Timer Counter 1 High Byte bit 2 RW 0 TCNT1H1 Timer Counter 1 High Byte bit 1 RW 0 TCNT1H0 Timer Counter 1 High Byte bit 0 RW 0 TCNT1L Timer Counter 1 Low Byte NA 0x84 io_timer.bmp N TCNT1L7 Timer Counter 1 Low Byte bit 7 RW 0 TCNT1L6 Timer Counter 1 Low Byte bit 6 RW 0 TCNT1L5 Timer Counter 1 Low Byte bit 5 RW 0 TCNT1L4 Timer Counter 1 Low Byte bit 4 RW 0 TCNT1L3 Timer Counter 1 Low Byte bit 3 RW 0 TCNT1L2 Timer Counter 1 Low Byte bit 2 RW 0 TCNT1L1 Timer Counter 1 Low Byte bit 1 RW 0 TCNT1L0 Timer Counter 1 Low Byte bit 0 RW 0 OCR1AL Output Compare Register 1A Low byte NA 0x88 io_flag.bmp N OCR1AL7 RW 0 OCR1AL6 RW 0 OCR1AL5 RW 0 OCR1AL4 RW 0 OCR1AL3 RW 0 OCR1AL2 RW 0 OCR1AL1 RW 0 OCR1AL0 RW 0 OCR1AH Output Compare Register 1A High byte NA 0x89 io_flag.bmp N OCR1AH7 RW 0 OCR1AH6 RW 0 OCR1AH5 RW 0 OCR1AH4 RW 0 OCR1AH3 RW 0 OCR1AH2 RW 0 OCR1AH1 RW 0 OCR1AH0 RW 0 TIMSK1 Timer/Counter Interrupt Mask Register NA 0x6F io_flag.bmp Y OCIE1A Timer/Counter1 Output Compare Interrupt Enable RW 0 TOIE1 Timer/Counter1 Overflow Interrupt Enable RW 0 TIFR1 Timer/Counter Interrupt Flag register 0x16 0x36 io_flag.bmp Y OCF1A Timer/Counter1 Output Compare Flag A RW 0 TOV1 Timer/Counter1 Overflow Flag RW 0 GTCCR General Timer/Counter Control Register 0x23 0x43 io_flag.bmp Y TSM Timer/Counter Synchronization Mode RW 0 PSRSYNC Prescaler Reset RW 0 [WUTCSR] io_timer.bmp t8pwm1_01 WUTCSR Wake-up Timer Control Register NA 0x62 io_flag.bmp Y WUTIF Wake-up Timer Interrupt Flag The bit WUTIF is set (one) when an overflow occurs in the Wake-up Timer. WUTIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, WUTIE (Wake-up Timer Interrupt Enable), and WUTIF are set (one), the Wake-up Timer interrupt is executed. RW 0 WUTIE Wake-up Timer Interrupt Enable When the WUTIE bit and the I-bit in the Status Register are set (one), the Wake-up Timer interrupt is enabled. The corresponding interrupt is executed if a Wake-up Timer overflow occurs, i.e., when the WUTIF bit is set . RW 0 WUTCF Wake-up timer Calibration Flag The WUTCF bit is set after every 256 Slow RC OScillator clocks (2 ms @ 131 kHz) RW 0 WUTR Wake-up Timer Reset When WUTR is written to one, the Wake-up Timer is reset, and starts counting from zero. The WUTR bit is automatically cleared to zero after the reset has been performed. RW 0 WUTE Wake-up Timer Enable When the WUTE is set (one) the Wake-up Timer is enabled, and the WUTE is cleared (zero) the Wake-up Timer function is disabled. RW 0 WUTP2 Wake-up Timer Prescaler Bit 2 The WUTP2, WUTP1 and WUTP0 bits determine the Wake-up Timer prescaling when the Wake-up Timer is enabled. The different prescaling values and their corresponding time-out periods are shown in the datasheet. RW 0 WUTP1 Wake-up Timer Prescaler Bit 1 The WUTP2, WUTP1 and WUTP0 bits determine the Wake-up Timer prescaling when the Wake-up Timer is enabled. The different prescaling values and their corresponding time-out periods are shown in the datasheet. RW 0 WUTP0 Wake-up Timer Prescaler Bit 0 The WUTP2, WUTP1 and WUTP0 bits determine the Wake-up Timer prescaling when the Wake-up Timer is enabled. The different prescaling values and their corresponding time-out periods are shown in the datasheet. RW 0 [BPPLR:BPCR:CBPTR:BPOCD:BPSCD:BPDUV:BPIR] io_analo.bmp BPPLR Battery Protection Parameter Lock Register NA 0xF8 io_analo.bmp Y BPPLE Battery Protection Parameter Lock Enable RW 0 BPPL Battery Protection Parameter Lock RW 0 BPCR Battery Protection Control Register NA 0xF7 io_analo.bmp Y DUVD RW 0 SCD RW 0 DCD RW 0 CCD RW 0 CBPTR Current Battery Protection Timing Register NA 0xF6 io_analo.bmp Y SCPT3 RW 0 SCPT2 RW 0 SCPT1 R 0 SCPT0 RW 0 OCPT3 RW 0 OCPT2 RW 0 OCPT1 RW 0 OCPT0 RW 0 BPOCD Battery Protection OverCurrent Detection Level Register NA 0xF5 io_analo.bmp Y DCDL3 RW 0 DCDL2 RW 0 DCDL1 R 0 DCDL0 RW 0 CCDL3 RW 0 CCDL2 RW 0 CCDL1 RW 0 CCDL0 RW 0 BPSCD Battery Protection Short-Circuit Detection Level Register NA 0xF4 io_analo.bmp Y SCDL3 RW 0 SCDL2 RW 0 SCDL1 RW 0 SCDL0 RW 0 BPDUV Battery Protection Deep Under Voltage Register NA 0xF3 io_analo.bmp Y DUVT1 RW 0 DUVT0 RW 0 DUDL3 RW 0 DUDL2 RW 0 DUDL1 RW 0 DUDL0 RW 0 BPIR Battery Protection Interrupt Register NA 0xF2 io_analo.bmp Y DUVIF Deep Under-voltage Early Warning Interrupt Flag RW 0 COCIF Charge Over-current Protection Activated Interrupt Flag RW 0 DOCIF RW 0 SCIF RW 0 DUVIE Deep Under-voltage Early Warning Interrupt Enable RW 0 COCIE RW 0 DOCIE RW 0 SCIE RW 0 [FCSR] io_analo.bmp FCSR NA 0xF0 io_analo.bmp Y PWMOC Pulse Width Modulation of OC output When the PWMOC is cleared (zero), the CFE bit and the battery protection circuitry controls the OC output. When this bit is set (one), the OC output will be controlled by the PWM output from the 8-bit Timer/Counter0 and the battery protection circuitry. RW 0 PWMOPC Pulse Width Modulation Modulation of OPC output When the PWMOPC is cleared (zero), the PFD bit and the battery protection circuitry controls the OPC output. When this bit is set (one), the OC output will be controlled by the PWM output from the 8-bit Timer/Counter0 and the battery protection circuitry. RW 0 CPS Current Protection Status The CPTS bit shows the status of the Current Protection. This bit is set (one) when the Current Protection Timer is activated, and is cleared (zero) when the hold-off time has elapsed. RW 0 DFE Discharge FET Enable When the DFE bit is cleared (zero), the Discharge FET will be disabled regardless of the state of the Battery Protection circuitry. When this bit is set (one), the Discharge FET state is determined by the Battery Protection circuitry. This bit will be cleared when CURRENT_PROTECTION is set (one). RW 0 CFE Charge FET Enable When the CFE bit is cleared (zero), the Charge FET will be disabled regardless of the state of the Battery Protection circuitry. When this bit is set (one), the Charge FET state is determined by the Battery Protection circuitry. This bit will be cleared when CURRENT_PROTECTION is set (one). RW 0 PFD Precharge FET disable The PFD bit provides complete control of the Precharge FET. When the PFD bit is cleared (zero), the Precharge FET will be enabled. When the PFD bit is set (one), the Precharge FET will be disabled. This bit will be set when CURRENT_PROTECTION is set (one). RW 0 [CADCSRA:CADCSRB:CADICH:CADICL:CADAC3:CADAC2:CADAC1:CADAC0:CADRCC:CADRDC] [CADICH:CADICL];[CADAC3:CADAC2:CADAC1:CADAC0] io_analo.bmp CoulombCounter_m406 CADCSRA CC-ADC Control and Status Register A NA 0xE4 io_analo.bmp Y CADEN When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled. RW 0 CADUB CC_ADC Update Busy RW 0 CADAS1 CC_ADC Accumulate Current Select Bit 1 The CADAS bits select the conversion time for the Accumulate Current output. Please refer to table 45 in the manual. RW 0 CADAS0 CC_ADC Accumulate Current Select Bit 0 The CADAS bits select the conversion time for the Accumulate Current output. Please refer to table 45 in the manual. RW 0 CADSI1 The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. RW 0 CADSI0 The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. RW 0 CADSE When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode. RW 0 CADCSRB CC-ADC Control and Status Register B NA 0xE5 io_analo.bmp Y CADACIE CC-ADC Accumulate Current Interrupt Enable RW 0 CADRCIE Regular Current Interrupt Enable When the CADACIE bit is set (one), and the I-bit in the Status Register is set (one), the CC-ADC Accumulate Current Interrupt is enabled. RW 0 CADICIE CAD Instantenous Current Interrupt Enable The CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43. RW 0 CADACIF CC-ADC Accumulate Current Interrupt Flag The CADACIF bit is set (one) after the Accumulate Current conversion has completed. The CC-ADC Accumulate Current Interrupt is executed if the CADAIE bit and the I-bit in SREG are set (one). CADACIF is cleared by hardware when executing the corresponding Interrupt Handling Vector. Alternatively, CADACIF is cleared by writing a logic one to the flag. he CADRCIF bit is set (one) when the absolute value of the result of the last CC-ADC conversion is greater than, or equal to, the compare values set by the CC-ADC Regular Charge/Discharge Current Level Registers. A positive value is compared to the Regular Charge Current Level, and a negative value is compared to the Regular Discharge Current Level. The CC-ADC Regular Current Interrupt is executed if the CADRCIE bit and the I-bit in SREG are set (one). CADRCIF is cleared by hardware when executing the corresponding Interrupt Handling vector. Alternatively, CADRCIF is cleared by writing a logic one to the flag. RW 0 CADRCIF CC-ADC Accumulate Current Interrupt Flag The CADACIF bit is set (one) after the Accumulate Current conversion has completed. The CC-ADC Accumulate Current Interrupt is executed if the CADAIE bit and the I-bit in SREG are set (one). CADACIF is cleared by hardware when executing the corresponding Interrupt Handling Vector. Alternatively, CADACIF is cleared by writing a logic one to the flag. he CADRCIF bit is set (one) when the absolute value of the result of the last CC-ADC conversion is greater than, or equal to, the compare values set by the CC-ADC Regular Charge/Discharge Current Level Registers. A positive value is compared to the Regular Charge Current Level, and a negative value is compared to the Regular Discharge Current Level. The CC-ADC Regular Current Interrupt is executed if the CADRCIE bit and the I-bit in SREG are set (one). CADRCIF is cleared by hardware when executing the corresponding Interrupt Handling vector. Alternatively, CADRCIF is cleared by writing a logic one to the flag. RW 0 CADICIF CC-ADC Instantaneous Current Interrupt Flag The CADICIF bit is set (one) when a CC-ADC Instantaneous Current conversion is completed. The CC-ADC Instantaneous Current Interrupt is executed if the CADICIE bit and the I-bit in SREG are set (one). CADICIF is cleared by hardware when executing the corresponding Interrupt Handling vector. Alternatively, CADICIF is cleared by writing a logic one to the flag. RW 0 CADICH CC-ADC Instantaneous Current NA 0xE9 io_analo.bmp N CADICH7 When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled. RW 0 CADICH6 RW 0 CADICH5 RW 0 CADICH4 The CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43. RW 0 CADICH3 The CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43. RW 0 CADICH2 The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. RW 0 CADICH1 The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. RW 0 CADICH0 When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode. RW 0 CADICL CC-ADC Instantaneous Current NA 0xE8 io_analo.bmp N CADICL7 When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled. RW 0 CADICL6 RW 0 CADICL5 RW 0 CADICL4 The CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43. RW 0 CADICL3 The CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43. RW 0 CADICL2 The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. RW 0 CADICL1 The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. RW 0 CADICL0 When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode. RW 0 CADAC3 ADC Accumulate Current NA 0xE3 io_analo.bmp N CADAC31 R 0 CADAC30 R 0 CADAC29 R 0 CADAC28 R 0 CADAC27 R 0 CADAC26 R 0 CADAC25 R 0 CADAC24 R 0 CADAC2 ADC Accumulate Current NA 0xE2 io_analo.bmp N CADAC23 R 0 CADAC22 R 0 CADAC21 R 0 CADAC20 R 0 CADAC19 R 0 CADAC18 R 0 CADAC17 R 0 CADAC16 R 0 CADAC1 ADC Accumulate Current NA 0xE1 io_analo.bmp N CADAC15 R 0 CADAC14 R 0 CADAC13 R 0 CADAC12 R 0 CADAC11 R 0 CADAC10 R 0 CADAC09 R 0 CADAC08 R 0 CADAC0 ADC Accumulate Current NA 0xE0 io_analo.bmp N CADAC07 R 0 CADAC06 R 0 CADAC05 R 0 CADAC04 R 0 CADAC03 R 0 CADAC02 R 0 CADAC01 R 0 CADAC00 R 0 CADRCC CC-ADC Regular Charge Current The CC-ADC Regular Charge Current Register determines the threshold level for the Regular Charge Current detection. When the result of a CC-ADC Instantaneous Current conversion is positive with a value greater than, or equal to, the Regular Charge Current level, the CC-ADC Regular Current Interrupt Flag is set. The CC-ADC Regular Charge Current Register is eight bits wide, defining the eight least significant bits of the Regular Charge Current level. The most significant bits of the Regular Charge Current level are always zero. The programmable range for the Regular Charge Current level is given in Table 44. NA 0xE6 io_analo.bmp N CADRCC7 When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled. RW 0 CADRCC6 RW 0 CADRCC5 RW 0 CADRCC4 The CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43. RW 0 CADRCC3 The CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43. RW 0 CADRCC2 The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. RW 0 CADRCC1 The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. RW 0 CADRCC0 When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode. RW 0 CADRDC CC-ADC Regular Discharge Current The CC-ADC Regular Charge Current Register determines the threshold level for the Regular Charge Current detection. When the result of a CC-ADC Instantaneous Current conversion is positive with a value greater than, or equal to, the Regular Charge Current level, the CC-ADC Regular Current Interrupt Flag is set. The CC-ADC Regular Charge Current Register is eight bits wide, defining the eight least significant bits of the Regular Charge Current level. The most significant bits of the Regular Charge Current level are always zero. The programmable range for the Regular Charge Current level is given in Table 44. NA 0xE7 io_analo.bmp N CADRDC7 When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled. RW 0 CADRDC6 RW 0 CADRDC5 RW 0 CADRDC4 The CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43. RW 0 CADRDC3 The CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43. RW 0 CADRDC2 The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. RW 0 CADRDC1 The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. RW 0 CADRDC0 When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode. RW 0 [CBCR] io_analo.bmp CBCR Cell Balancing Control Register NA 0xF1 io_analo.bmp Y CBE4 Cell Balancing Enable 4 RW 0 CBE3 Cell Balancing Enable 4 RW 0 CBE2 Cell Balancing Enable 2 RW 0 CBE1 Battery Protection Parameter Lock RW 0 [SREG:SPH:SPL:MCUCR:MCUSR:FOSCCAL:SMCR:GPIOR2:GPIOR1:GPIOR0:CCSR:DIDR0:PRR0] [SPH:SPL] io_cpu.bmp SREG Status Register 0x3F 0x5F io_sreg.bmp Y I Global Interrupt Enable The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable bit is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. RW 0 T Bit Copy Storage The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction. RW 0 H Half Carry Flag The half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed information. RW 0 S Sign Bit The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruc-tion Set Description for detailed information. RW 0 V Two's Complement Overflow Flag The two’s complement overflow flag V supports two’s complement arithmetics. See the Instruction Set Description for detailed information. RW 0 N Negative Flag The negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information. RW 0 Z Zero Flag The zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information. RW 0 C Carry Flag The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software. RW 0 SPH Stack Pointer High The general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the AT90S4414/8515 supports up to 64 kB external SRAM, all 16-bits are used. The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or return from interrupt R 0x3E 0x5E io_sph.bmp N SP15 Stack pointer bit 15 RW 0 SP14 Stack pointer bit 14 RW 0 SP13 Stack pointer bit 13 RW 0 SP12 Stack pointer bit 12 RW 0 SP11 Stack pointer bit 11 RW 0 SP10 Stack pointer bit 10 RW 0 SP9 Stack pointer bit 9 RW 0 SP8 Stack pointer bit 8 RW 0 SPL Stack Pointer Low The general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the AT90S4414/8515 supports up to 64 kB external SRAM, all 16-bits are used. The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or return from interrupt 0x3D 0x5D io_sph.bmp N SP7 Stack pointer bit 7 RW 0 SP6 Stack pointer bit 6 RW 0 SP5 Stack pointer bit 5 RW 0 SP4 Stack pointer bit 4 RW 0 SP3 Stack pointer bit 3 RW 0 SP2 Stack pointer bit 2 RW 0 SP1 Stack pointer bit 1 RW 0 SP0 Stack pointer bit 0 RW 0 MCUCR MCU Control Register The MCU Control Register contains control bits for general MCU functions. 0x35 0x55 io_flag.bmp Y JTD JTAG Disable RW 0 PUD Pull-up disable When this bit is written to one,the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn registers are configured to enable the pull-ups ({DDxn,PORTxn}=0b01). RW 0 IVSEL Interrupt Vector Select When the IVSEL bit is cleared (zero),the interrupt vectors are placed at the start of the Flash memory.When this bit is set (one),the interrupt vectors are moved to the beginning of the Boot Loader section of the flash.The actual address of the start of the boot flash section is determined by the BOOTSZ fuses. RW 0 IVCE Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit.IVCE is cleared by hardware four cycles after it is written or when IVSEL is written.Setting the IVCE bit will disable interrupts. RW 0 MCUSR MCU Status Register The MCU Status Register provides information on which reset source caused an MCU reset. 0x34 0x54 io_flag.bmp Y JTRF JTAG Reset Flag This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on reset, or by writing a logic zero to the flag. • Bit 3 - WDRF: Watchdog Reset Flag R/W 0 WDRF Watchdog Reset Flag This bit is set if a watchdog reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag. R/W 0 BODRF Brown-out Reset Flag This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by R/W 0 EXTRF External Reset Flag This bit is set if an external reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag. R/W 0 PORF Power-on reset flag This bit is set if a power-on reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the reset flags to identify a reset condition, the user should read and then reset the MCUCSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags. R/W 0 FOSCCAL Fast Oscillator Calibration Value Writing the calibration byte to this address will trim the internal oscillator to remove process variations from the oscillator frequency. This is done automatically during chip reset. When OSCCAL is zero, the lowest available frequency is chosen. Writing non-zero values to this register will increase the frequency of the internal oscillator. Writing $FF to the register gives the highest available frequency. The calibrated oscillator is used to time EEPROM and Flash access. If EEPROM or Flash is written, do not calibrate to more than 10% above the nominal frequency. Otherwise, the EEPROM or Flash write may fail. Note that the Oscillator is intended for calibration to 1.0 MHz, 2.0 MHz, 4.0 MHz, or 8.0MHz. Tuning to other values is not guaranteed, as indicated in Table NA 0x66 io_cpu.bmp N FCAL7 Oscillator Calibration Value Bit7 R/W 0 FCAL6 Oscillator Calibration Value Bit6 R/W 0 FCAL5 Oscillator Calibration Value Bit5 R/W 0 FCAL4 Oscillator Calibration Value Bit4 R/W 0 FCAL3 Oscillator Calibration Value Bit3 R/W 0 FCAL2 Oscillator Calibration Value Bit2 R/W 0 FCAL1 Oscillator Calibration Value Bit1 R/W 0 FCAL0 Oscillator Calibration Value Bit0 R/W 0 SMCR Sleep Mode Control Register The Sleep Mode Control Register contains control bits for power management. 0x33 0x53 io_cpu.bmp Y SM2 Sleep Mode Select bit 2 These bits select between the five available sleep modes. RW 0 SM1 Sleep Mode Select bit 1 These bits select between the five available sleep modes. RW 0 SM0 Sleep Mode Select bit 0 These bits select between the five available sleep modes. RW 0 SE Sleep Enable The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed.To RW 0 GPIOR2 General Purpose IO Register 2 The ATmega169 contains three General Purpose I/O Registers.These registers can be used for storing any information, and they are particularly useful for storing global variables and status flags.General Purpose I/O Registers within the address range $00 -$1F are directly bit-accessible using the SBI,CBI,SBIS,and SBIC instructions. 0x2B 0x4B io_cpu.bmp N GPIOR27 General Purpose IO Register 2 bit 7 RW 0 GPIOR26 General Purpose IO Register 2 bit 6 RW 0 GPIOR25 General Purpose IO Register 2 bit 5 RW 0 GPIOR24 General Purpose IO Register 2 bit 4 RW 0 GPIOR23 General Purpose IO Register 2 bit 3 RW 0 GPIOR22 General Purpose IO Register 2 bit 2 RW 0 GPIOR21 General Purpose IO Register 2 bit 1 RW 0 GPIOR20 General Purpose IO Register 2 bit 0 RW 0 GPIOR1 General Purpose IO Register 1 The ATmega169 contains three General Purpose I/O Registers.These registers can be used for storing any information, and they are particularly useful for storing global variables and status flags.General Purpose I/O Registers within the address range $00 -$1F are directly bit-accessible using the SBI,CBI,SBIS,and SBIC instructions. 0x2A 0x4A io_cpu.bmp N GPIOR17 General Purpose IO Register 1 bit 7 RW 0 GPIOR16 General Purpose IO Register 1 bit 6 RW 0 GPIOR15 General Purpose IO Register 1 bit 5 RW 0 GPIOR14 General Purpose IO Register 1 bit 4 RW 0 GPIOR13 General Purpose IO Register 1 bit 3 RW 0 GPIOR12 General Purpose IO Register 1 bit 2 RW 0 GPIOR11 General Purpose IO Register 1 bit 1 RW 0 GPIOR10 General Purpose IO Register 1 bit 0 RW 0 GPIOR0 General Purpose IO Register 0 The ATmega169 contains three General Purpose I/O Registers.These registers can be used for storing any information, and they are particularly useful for storing global variables and status flags.General Purpose I/O Registers within the address range $00 -$1F are directly bit-accessible using the SBI,CBI,SBIS,and SBIC instructions. 0x1E 0x3E io_cpu.bmp N GPIOR07 General Purpose IO Register 0 bit 7 RW 0 GPIOR06 General Purpose IO Register 0 bit 6 RW 0 GPIOR05 General Purpose IO Register 0 bit 5 RW 0 GPIOR04 General Purpose IO Register 0 bit 4 RW 0 GPIOR03 General Purpose IO Register 0 bit 3 RW 0 GPIOR02 General Purpose IO Register 0 bit 2 RW 0 GPIOR01 General Purpose IO Register 0 bit 1 RW 0 GPIOR00 General Purpose IO Register 0 bit 0 RW 0 CCSR Clock Control and Status Register NA 0xC0 io_cpu.bmp Y XOE 32 kHz Crystal Oscillator Enable The XOE bit is used to enable the 32 kHz Crystal Oscillator before it is selected as clock source. This allows the Oscillator clock to stabilize prior to use. The 32 kHz Crystal Oscillator requires approximately two seconds to stabilize, this must be timed by the user software. This bit must remain set as long as the ACS bit is set, otherwise the 32 kHz clock to CC-ADC and Wake-up timer will be stopped. RW 0 ACS Asynchronous Clock Select The ACS bit is used to selected the source of the asynchronous clock for the Coulomb Counter ADC and Wake-up Timer. The Slow RC Oscillator is selected when this bit is cleared (zero). The 32 kHz Crystal Oscillator is selected when this bit is set (one). RW 0 DIDR0 Digital Input Disable Register NA 0x7E io_cpu.bmp N VADC3D When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled. RW 0 VADC2D When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled. RW 0 VADC1D When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled. RW 0 VADC0D When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled. RW 0 PRR0 Power Reduction Register 0 NA 0x64 io_cpu.bmp Y PRTWI Power Reduction TWI Writing a logic one to this bit shuts down the TWI by stopping the clock to the module. When waking up the TWI again, the TWI should be re initialized to ensure proper operation. RW 0 PRTIM1 Power Reduction Timer/Counter1 Writing a logic one to this bit shuts down the Timer/Counter1 module. When the, Timer/Counter1 is enabled, operation will continue like before the shutdown. RW 0 PRTIM0 Power Reduction Timer/Counter0 Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, operation will continue like before the shutdown. RW 0 PRVADC Power Reduction V-ADC Writing a logic one to this bit shuts down the V-ADC. The V-ADC must be disabled before shut down. RW 0 [WDTCSR] io_watch.bmp WDTCSR Watchdog Timer Control Register NA 0x60 io_flag.bmp Y WDIF Watchdog Timeout Interrupt Flag RW 0 WDIE Watchdog Timeout Interrupt Enable RW 0 WDP3 Watchdog Timer Prescaler Bit 3 RW 0 WDCE Watchdog Change Enable RW 0 WDE Watch Dog Enable When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog RW 0 WDP2 Watch Dog Timer Prescaler bit 2 RW 0 WDP1 Watch Dog Timer Prescaler bit 1 RW 0 WDP0 Watch Dog Timer Prescaler bit 0 RW 0 [TCCR0A:TCCR0B:TCNT0:OCR0A:OCR0B:TIMSK0:TIFR0] io_timer.bmp timer8_megaD The 8-bit Timer/Counter0 can select clock source from CK, prescaled CK, or an external pin. In addition it can be stopped as described in “Timer/Counter0 Control Register - TCCR0” on page 35. The overflow status flag is found in “The Timer/Counter Interrupt Flag Register - TIFR” on page 29. Control signals are found in the Timer/Counter0 Control Register - TCCR0. The interrupt enable/disable settings for Timer/Counter0 are found in “The Timer/Counter Interrupt Mask Regis-ter - TIMSK” on page 28. When Timer/Counter0 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. The 8-bit Timer/Counter0 features both a high resolution and a high accuracy usage with the lower prescaling opportuni-ties. Similarly, the high prescaling opportuni ties make the Timer/Counter0 useful for lower speed functions or exact timing functions with infrequent actions TCCR0A Timer/Counter0 Control Register 0x24 0x44 io_flag.bmp Y COM0A1 Force Output Compare RW 0 COM0A0 Waveform Generation Mode RW 0 COM0B1 RW 0 COM0B0 RW 0 WGM01 Clock Select0 bit 1 RW 0 WGM00 Clock Select0 bit 0 RW 0 TCCR0B Timer/Counter0 Control Register 0x25 0x45 io_flag.bmp Y FOC0A Force Output Compare RW 0 FOC0B Waveform Generation Mode RW 0 WGM02 RW 0 CS02 Clock Select0 bit 2 RW 0 CS01 Clock Select0 bit 1 RW 0 CS00 Clock Select0 bit 0 RW 0 TCNT0 Timer Counter 0 The Timer/Counter0 is realized as an up-counter with read and write access. If the Timer/Counter0 is written and a clock source is present, the Timer/Counter0 continues counting in the clock cycle following the write operation. 0x26 0x46 io_timer.bmp N TCNT07 Timer Counter 0 bit 7 RW 0 TCNT06 Timer Counter 0 bit 6 RW 0 TCNT05 Timer Counter 0 bit 5 RW 0 TCNT04 Timer Counter 0 bit 4 RW 0 TCNT03 Timer Counter 0 bit 3 RW 0 TCNT02 Timer Counter 0 bit 2 RW 0 TCNT01 Timer Counter 0 bit 1 RW 0 TCNT00 Timer Counter 0 bit 0 RW 0 OCR0A Output compare Register A 0x27 0x47 io_flag.bmp Y OCR0A7 RW 0 OCR0A6 RW 0 OCR0A5 RW 0 OCR0A4 RW 0 OCR0A3 RW 0 OCR0A2 RW 0 OCR0A1 RW 0 OCR0A0 RW 0 OCR0B Output compare Register B 0x28 0x48 io_flag.bmp Y OCR0B7 RW 0 OCR0B6 RW 0 OCR0B5 RW 0 OCR0B4 RW 0 OCR0B3 RW 0 OCR0B2 RW 0 OCR0B1 RW 0 OCR0B0 RW 0 TIMSK0 Timer/Counter Interrupt Mask Register NA 0x6E io_flag.bmp Y OCIE0B Output Compare Interrupt Enable RW 0 OCIE0A Output Compare Interrupt Enable RW 0 TOIE0 Overflow Interrupt Enable RW 0 TIFR0 Timer/Counter Interrupt Flag register 0x15 0x35 io_flag.bmp Y OCF0B Output Compare Flag RW 0 OCF0A Output Compare Flag RW 0 TOV0 Overflow Flag RW 0 [PORTA:DDRA:PINA] io_port.bmp AVRSimIOPort.SimIOPort PORTA Port A Data Register 0x02 0x22 io_port.bmp N PORTA7 Port A Data Register bit 7 RW 0 PORTA6 Port A Data Register bit 6 RW 0 PORTA5 Port A Data Register bit 5 RW 0 PORTA4 Port A Data Register bit 4 RW 0 PORTA3 Port A Data Register bit 3 RW 0 PORTA2 Port A Data Register bit 2 RW 0 PORTA1 Port A Data Register bit 1 RW 0 PORTA0 Port A Data Register bit 0 RW 0 DDRA Port A Data Direction Register 0x01 0x21 io_flag.bmp N DDA7 Data Direction Register, Port A, bit 7 RW 0 DDA6 Data Direction Register, Port A, bit 6 RW 0 DDA5 Data Direction Register, Port A, bit 5 RW 0 DDA4 Data Direction Register, Port A, bit 4 RW 0 DDA3 Data Direction Register, Port A, bit 3 RW 0 DDA2 Data Direction Register, Port A, bit 2 RW 0 DDA1 Data Direction Register, Port A, bit 1 RW 0 DDA0 Data Direction Register, Port A, bit 0 RW 0 PINA Port A Input Pins The Port A Input Pins address - PINA - is not a register, and this address enables access to the physical value on each Port A pin. When reading PORTA the Port A Data Latch is read, and when reading PINA, the logical values present on the pins are read. 0x00 0x20 io_port.bmp N PINA7 Input Pins, Port A bit 7 RW Hi-Z PINA6 Input Pins, Port A bit 6 RW Hi-Z PINA5 Input Pins, Port A bit 5 RW Hi-Z PINA4 Input Pins, Port A bit 4 RW Hi-Z PINA3 Input Pins, Port A bit 3 RW Hi-Z PINA2 Input Pins, Port A bit 2 RW Hi-Z PINA1 Input Pins, Port A bit 1 RW Hi-Z PINA0 Input Pins, Port A bit 0 RW Hi-Z [PORTB:DDRB:PINB] io_port.bmp AVRSimIOPort.SimIOPort PORTB Port B Data Register 0x05 0x25 io_port.bmp N PORTB7 Port B Data Register bit 7 RW 0 PORTB6 Port B Data Register bit 6 RW 0 PORTB5 Port B Data Register bit 5 RW 0 PORTB4 Port B Data Register bit 4 RW 0 PORTB3 Port B Data Register bit 3 RW 0 PORTB2 Port B Data Register bit 2 RW 0 PORTB1 Port B Data Register bit 1 RW 0 PORTB0 Port B Data Register bit 0 RW 0 DDRB Port B Data Direction Register 0x04 0x24 io_flag.bmp N DDB7 Port B Data Direction Register bit 7 RW 0 DDB6 Port B Data Direction Register bit 6 RW 0 DDB5 Port B Data Direction Register bit 5 RW 0 DDB4 Port B Data Direction Register bit 4 RW 0 DDB3 Port B Data Direction Register bit 3 RW 0 DDB2 Port B Data Direction Register bit 2 RW 0 DDB1 Port B Data Direction Register bit 1 RW 0 DDB0 Port B Data Direction Register bit 0 RW 0 PINB Port B Input Pins The Port B Input Pins address - PINB - is not a register, and this address enables access to the physical value on each Port B pin. When reading PORTB, the Port B Data Latch is read, and when reading PINB, the logical values present on the pins are read. 0x03 0x23 io_port.bmp N PINB7 Port B Input Pins bit 7 R 0 PINB6 Port B Input Pins bit 6 R 0 PINB5 Port B Input Pins bit 5 R 0 PINB4 Port B Input Pins bit 4 R 0 PINB3 Port B Input Pins bit 3 R 0 PINB2 Port B Input Pins bit 2 R 0 PINB1 Port B Input Pins bit 1 R 0 PINB0 Port B Input Pins bit 0 R 0 [PORTC] io_port.bmp AVRSimIOPort.SimIOPort PORTC Port C Data Register 0x08 0x28 io_port.bmp N PORTC0 Port C Data Register bit 0 RW 0 [PORTD:DDRD:PIND] io_port.bmp AVRSimIOPort.SimIOPort PORTD Data Register, Port D 0x0B 0x2B io_port.bmp N PORTD1 RW 0 PORTD0 RW 0 DDRD Data Direction Register, Port D 0x0A 0x2A io_flag.bmp N DDD1 RW 0 DDD0 RW 0 PIND Input Pins, Port D 0x09 0x29 io_port.bmp N PIND1 R 0 PIND0 R 0 [SPMCSR] io_cpu.bmp AVRSimIOSPM.SimIOSPM The Boot Loader Support provides a real Read While Write self-programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program. The Boot Loader program can use any available data interface and associated proto-col to read code and write (program) that code into the Flash memory, or read the code from the program memory. The program code within the Boot Loader section has the capability to write into the entire Flash, including the Boot Loader Memory. The Boot Loader can thus even modify itself, and it can also erase itself from the code if the feature is not needed anymore. The size of the Boot Loader Memory is configurable with fuses and the Boot Loader has two separate sets of Boot Lock Bits which can be set independently. This gives the user a unique flexibility to select different levels of protection. Boot Loader Features: Read While Write self-programming. Flexibl Boot Memory size. High security (separate Boot Lock bits for a flexible protection). Separate fuse to select reset vector Optimized page (1) size. Code efficient algorithm Efficient read-modify-write suppor SPMCSR Store Program Memory Control Register The Store Program Memory Control Register contains the control bits needed to control the Boot Loader operations. 0x37 0x57 io_flag.bmp Y SPMIE SPM Interrupt Enable When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN bit in the SPMCR register is cleared. RW 0 RWWSB Read While Write Section Busy When a self-programming (page erase or page write) operation to the RWW section is initiated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a self-programming operation is completed. Alternatively the RWWSB bit will auto-matically be cleared if a page load operation is initiated. R 0 SIGRD Signature Row Read If this bit is written to one at the same time as SPMEN, the next LPM instruction within three clock cycles will read a byte from the signature row into the destination register. see “Reading the Signature Row from Software” in the datasheet for details. An SPM instruction within four cycles after SIGRD and SPMEN are set will have no effect. This operation is reserved for future use and should not be used. RW 0 RWWSRE Read While Write section read enable When programming (page erase or page write) to the RWW section, the RWW section is blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW section, the user software must wait until the programming is completed (SPMEN will be cleared). Then, if the RWWSRE bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles re-enables the RWW section. The RWW section cannot be re-enabled while Flash is busy with a page erase or a page write (SPMEN is set). If the RWWSRE bit is written while the Flash is being loaded, the Flash load operation will abort and the data loaded will be lo RW 0 BLBSET Boot Lock Bit Set If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles sets Boot Lock bits, according to the data in R0. The data in R1 and the address in the Z pointer are ignored. The BLBSET bit will automatically be cleared upon completion of the lock bit set, or if no SPM instruction is executed within four clock cycles. An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCR register, will read either the Lock-bits or the Fuse bits (depending on Z0 in the Z pointer) into the destination register. See “Reading the Fuse and Lock Bits from Software” on page 235 for details RW 0 PGWRT Page Write If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPM instruction is exe-cuted within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed. RW 0 PGERS Page Erase If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page erase. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a page erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed. RW 0 SPMEN Store Program Memory Enable This bit enables the SPM instruction for the next four clock cycles. If written to one together with either RWWSRE, BLB-SET, PGWRT or PGERS, the following SPM instruction will have a special meaning, see description above. If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z pointer. The LSB of the Z pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During page erase and page write, the SPMEN bit remain high until the operation is completed. Writing any other combination than “10001”, "01001", "00101", "00011" or "00001" in the lower five bits will have no effec RW 0 [TWBCSR:TWAMR:TWBR:TWCR:TWSR:TWDR:TWAR] io_com.bmp TWI: Simple yet powerful and flexible communications interface, only two bus lines needed. Both master and slave operation supported. Device can operate as transmitter or receiver. 7-bit address space allows up to 128 different slave addresses. Multi-master arbitration support Up to 400 kHz data transfer speed Slew-rate limited output drivers Noise suppression circuitry rejects spikes on bus lines Fully programmable slave address with general call support Address recognition causes wake-up when AVR is in sleep mode The Two-Wire Serial Interface (TWI) is ideally suited to typical microcontroller applications. The TWI protocol allows the systems designer to interconnect up to 128 different devices using only two bidirectional bus lines, one for clock (SCL) andone for data (SDA). The only external hardware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines. All devices connected to the bus have individual addresses, and mechanisms for resolving bus contention are inherent in the TWI TWBCSR TWI Bus Control and Status Register The Bus Connect/Disconnect module is an addition to the TWI Interface. Based on a configuration bit, an interrupt can be generated either when the TWI bus is connected or disconnected. NA 0xBE io_com.bmp Y TWBCIF TWI Bus Connect/Disconnect Interrupt Flag RW 0 TWBCIE TWI Bus Connect/Disconnect Interrupt Enable RW 0 TWBDT1 TWI Bus Disconnect Time-out Period RW 0 TWBDT0 TWI Bus Disconnect Time-out Period RW 0 TWBCIP TWI Bus Connect/Disconnect Interrupt Polarity RW 0 TWAMR TWI (Slave) Address Mask Register The TWAMR can be loaded with a 7-bit Salve Address mask. Each of the bits in TWAMR can mask (disable) the corresponding address bits in the TWI Address Register (TWAR). If the mask bit is set to one then the address match logic ingnores the compare between the incomming address bit and the corresponding bit in TWAR. NA 0xBD io_com.bmp Y TWAM6 RW 0 TWAM5 RW 0 TWAM4 RW 0 TWAM3 RW 0 TWAM2 RW 0 TWAM1 RW 0 TWAM0 RW 0 TWBR TWI Bit Rate register TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency divider which generates the SCL clock frequency in the master modes. See “Bit Rate Generator Unit” on page 165 for calculating bit rates. NA 0xB8 io_com.bmp N TWBR7 RW 0 TWBR6 RW 0 TWBR5 RW 0 TWBR4 RW 0 TWBR3 RW 0 TWBR2 RW 0 TWBR1 RW 0 TWBR0 RW 0 TWCR TWI Control Register The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate a master access by applying a START condition to the bus, to generate a receiver acknowledge, to generate a stop condition, and to control halting of the bus while the data to be written to the bus are written to the TWDR. It also indicates a write collision if data is attempted written to TWDR while the register is inaccessible. NA 0xBC io_flag.bmp Y TWINT TWI Interrupt Flag This bit is set by hardware when the TWI has finished its current job and expects application software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the TWI interrupt vector. While the TWINT flag is set, the SCL low period is stretched. The TWINT flag must be cleared by software by writing a logic one to it. Note that this flag is not automatically cleared by hardware when executing the interrupt routine. Also note that clearing this flag starts the operation of the TWI, so all accesses to the TWI Address Register (TWAR), TWI Status Register (TWSR), and TWI Data Register (TWDR) must be complete before clearing this flag RW 0 TWEA TWI Enable Acknowledge Bit The TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is written to one, the ACK pulse is gener-ated on the TWI bus if the following conditions are met: 1. The device’s own slave address has been received. 2. A general call has been received, while the TWGCE bit in the TWAR is set. 3. A data byte has been received in master receiver or slave receiver mode. By writing the TWEA bit to zero, the device can be virtually disconnected from the 2-wire Serial Bus temporarily. Address recognition can then be resumed by writing the TWEA bit to one again RW 0 TWSTA TWI Start Condition Bit The application writes the TWSTA bit to one when it desires to become a master on the 2-wire Serial Bus. The TWI hard-ware checks if the bus is available, and generates a START condition on the bus if it is free. However, if the bus is not free, the TWI waits until a STOP condition is detected, and then generates a new START condition to claim the bus Master sta-tus. TWSTA is cleared by the TWI hardware when the START condition has been transmitted. RW 0 TWSTO TWI Stop Condition Bit Writing the TWSTO bit to one in master mode will generate a STOP condition on the 2-wire Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit is cleared automatically. In slave mode, setting the TWSTO bit can be used to recover from an error condition. This will not generate a STOP condition, but the TWI returns to a well-defined unaddressed slave mode and releases the SCL and SDA lines to a high impedance state. RW 0 TWWC TWI Write Collition Flag The TWWC bit is set when attempting to write to the TWI Data Register - TWDR when TWINT is low. This flag is cleared by writing the TWDR register when TWINT is high. RW 0 TWEN TWI Enable Bit The TWEN bit enables TWI operation and activates the TWI interface. When TWEN is written to one, the TWI takes control over the I/O pins connected to the SCL and SDA pins, enabling the slew-rate limiters and spike filters. If this bit is written to zero, the TWI is switched off and all TWI transmissions are terminated, regardless of any ongoing operation. RW 0 TWIE TWI Interrupt Enable When this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request will be activated for as long as the TWINT flag is high. RW 0 TWSR TWI Status Register NA 0xB9 io_flag.bmp Y TWS7 TWI Status Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient c RW 0 TWS6 TWI Status Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient co RW 0 TWS5 TWI Status Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient c RW 0 TWS4 TWI Status Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient co RW 0 TWS3 TWI Status Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient co RW 0 TWPS1 TWI Prescaler Bits 1..0: These bits can be read and written, and control the bit rate prescaler. See “Bit Rate Generator Unit” on page 165 for calculating bit rates. RW 0 TWPS0 TWI Prescaler Bits 1..0: These bits can be read and written, and control the bit rate prescaler. See “Bit Rate Generator Unit” on page 165 for calculating bit rates. RW 0 TWDR TWI Data register In transmit mode, TWDR contains the next byte to be transmitted. In receive mode, the TWDR contains the last byte received. It is writable while the TWI is not in the process of shifting a byte. This occurs when the TWI interrupt flag (TWINT) is set by hardware. Note that the data register cannot be initialized by the user before the first interrupt occurs. The data in TWDR remains stable as long as TWINT is set. While data is shifted out, data on the bus is simultaneously shifted in. TWDR always contains the last byte present on the bus, except after a wake up from a sleep mode by the TWI interrupt. In this case, the contents of TWDR is undefined. In the case of a lost bus arbitration, no data is lost in the transi-tion from Master to Slave. Handling of the ACK bit is controlled automatically by the TWI logic, the CPU cannot access the ACK bit directl NA 0xBB io_com.bmp N TWD7 TWI Data Register Bit 7 RW 1 TWD6 TWI Data Register Bit 6 RW 1 TWD5 TWI Data Register Bit 5 RW 1 TWD4 TWI Data Register Bit 4 RW 1 TWD3 TWI Data Register Bit 3 RW 1 TWD2 TWI Data Register Bit 2 RW 1 TWD1 TWI Data Register Bit 1 RW 1 TWD0 TWI Data Register Bit 0 RW 1 TWAR TWI (Slave) Address register The TWAR should be loaded with the 7-bit slave address (in the seven most significant bits of TWAR) to which the TWI will respond when programmed as a slave transmitter or receiver, and not needed in the master modes. In multimaster sys-tems, TWAR must be set in masters which can be addressed as slaves by other masters. The LSB of TWAR is used to enable recognition of the general call address ($00). There is an associated address compar-ator that looks for the slave address (or general call address if enabled) in the received serial address. If a match is found, an interrupt request is genera NA 0xBA io_com.bmp Y TWA6 TWI (Slave) Address register Bit 6 RW 0 TWA5 TWI (Slave) Address register Bit 5 RW 0 TWA4 TWI (Slave) Address register Bit 4 RW 0 TWA3 TWI (Slave) Address register Bit 3 RW 0 TWA2 TWI (Slave) Address register Bit 2 RW 0 TWA1 TWI (Slave) Address register Bit 1 RW 0 TWA0 TWI (Slave) Address register Bit 0 RW 0 TWGCE TWI General Call Recognition Enable Bit RW 0 [BGCRR:BGCCR] io_analo.bmp BGCRR Bandgap Calibration of Resistor Ladder NA 0xD1 io_analo.bmp N BGCR7 Bandgap Calibration of Resistor Ladder Bit 7 RW 0 BGCR6 Bandgap Calibration of Resistor Ladder Bit 6 RW 0 BGCR5 Bandgap Calibration of Resistor Ladder Bit 5 RW 0 BGCR4 Bandgap Calibration of Resistor Ladder Bit 4 RW 0 BGCR3 Bandgap Calibration of Resistor Ladder Bit 3 RW 0 BGCR2 Bandgap Calibration of Resistor Ladder Bit 2 RW 0 BGCR1 Bandgap Calibration of Resistor Ladder Bit 1 RW 0 BGCR0 Bandgap Calibration of Resistor Ladder Bit 0 RW 0 BGCCR Bandgap Calibration Register NA 0xD0 io_analo.bmp Y BGD Setting the BGD bit to one will disable the bandgap voltage reference. This bit must be cleared before enabling CC-ADC or V-ADC, and must remain unset while either ADC is enabled. RW 0 BGCC5 BG Calibration of PTAT Current Bit 5 RW 0 BGCC4 BG Calibration of PTAT Current Bit 4 These bits are used for trimming of the nominal value of the bandgap reference voltage. These bits are binary caoded, step size is approximately 2mV. RW 0 BGCC3 BG Calibration of PTAT Current Bit 3 These bits are used for trimming of the nominal value of the bandgap reference voltage. These bits are binary caoded, step size is approximately 2mV. RW 0 BGCC2 BG Calibration of PTAT Current Bit 2 These bits are used for trimming of the nominal value of the bandgap reference voltage. These bits are binary caoded, step size is approximately 2mV. RW 0 BGCC1 BG Calibration of PTAT Current Bit 1 These bits are used for trimming of the nominal value of the bandgap reference voltage. These bits are binary caoded, step size is approximately 2mV. RW 0 BGCC0 BG Calibration of PTAT Current Bit 0 These bits are used for trimming of the nominal value of the bandgap reference voltage. These bits are binary caoded, step size is approximately 2mV. RW 0 [EEARH:EEARL:EEDR:EECR] [EEARH:EEARL] io_cpu.bmp EEARH EEPROM Address Register High Byte io_cpu.bmp 0x22 0x42 N EEAR8 EEPROM Read/Write Access Bit 8 RW 0 EEARL EEPROM Address Register Low Byte io_cpu.bmp 0x21 0x41 N EEAR7 EEPROM Read/Write Access Bit 7 RW 0 EEAR6 EEPROM Read/Write Access Bit 6 RW 0 EEAR5 EEPROM Read/Write Access Bit 5 RW 0 EEAR4 EEPROM Read/Write Access Bit 4 RW 0 EEAR3 EEPROM Read/Write Access Bit 3 RW 0 EEAR2 EEPROM Read/Write Access Bit 2 RW 0 EEAR1 EEPROM Read/Write Access Bit 1 RW 0 EEAR0 EEPROM Read/Write Access Bit 0 RW 0 EEDR EEPROM Data Register For the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR. io_cpu.bmp 0x20 0x40 N EEDR7 EEPROM Data Register bit 7 RW 0 EEDR6 EEPROM Data Register bit 6 RW 0 EEDR5 EEPROM Data Register bit 5 RW 0 EEDR4 EEPROM Data Register bit 4 RW 0 EEDR3 EEPROM Data Register bit 3 RW 0 EEDR2 EEPROM Data Register bit 2 RW 0 EEDR1 EEPROM Data Register bit 1 RW 0 EEDR0 EEPROM Data Register bit 0 RW 0 EECR EEPROM Control Register io_flag.bmp 0x1F 0x3F Y EEPM1 EEPROM Programming Mode Bits RW NA EEPM0 EEPROM Programming Mode Bits RW NA EERIE EEPROM Ready Interrupt Enable RW 0 EEMPE EEPROM Master Programming Enable RW 0 EEMWE EEPE EEPROM Programming Enable RW X EEWE EERE EEPROM Read Enable RW 0 [JTAGICEmkII:STK500:SIMULATOR:STK500_2] 0x0950703F JTAG 0x3F,0x0F,0x60,0xF8,0xFF,0x0D,0xB8,0xE0 0x37,0x0F,0x00,0xE0,0xFF,0x0D,0xB8,0xE0 0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00 0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00 0x55,0xDB,0x00,0x57,0x32,0x03,0x00,0x00,0x00,0x00,0x00,0x7F,0x01,0x00,0x03,0x00,0xFF,0x03,0xFF,0x01 0x50,0xDB,0x00,0x50,0x32,0x03,0x00,0x00,0x00,0x00,0x00,0x6D,0x01,0x00,0x03,0x00,0xD0,0x00,0xFB,0x00 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 0x31 0X57 0X00 128 4 0x4F00 0x4F00 0x4E00 0x4C00 0x4800 0xF8 0xA000 0x0000,32 0x0020,64 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x3e 0x3d 0x00 0x00 0x00 0x00 0x01 0x01 0x00 0x3f 0x0950703F Part revision not supported by AVR Studio. 0x70 0 1 1 0xFF 0xFF 0xFF 0 0 AVRSimCoreV2.SimCoreV2 AVRSimMemory8bit.SimMemory8bit AVRSimInterrupt.SimInterrupt 13 0x2a 0 AVRSimIOPort.SimIOPort Y AVRSimIOPort.SimIOPort Y AVRSimIOPort.SimIOPort N AVRSimIOPort.SimIOPort Y AVRSimIOExtInterrupt.SimIOExtInterrupt 0x0004 0x1D 0x01 0x3A 0x01 0x00 0x10 0x69 0x03 AVRSimIOExtInterrupt.SimIOExtInterrupt 0x0006 0x1D 0x02 0x1C 0x02 0x00 0x20 0x69 0x0c AVRSimIOExtInterrupt.SimIOExtInterrupt 0x0008 0x1D 0x04 0x1C 0x04 0x00 0x40 0x69 0x30 AVRSimIOExtInterrupt.SimIOExtInterrupt 0x000A 0x1D 0x08 0x1C 0x08 0x00 0x80 0x69 0xc0 AVRSimIOPinChangeInterrupt.SimIOPinChangeInterrupt 0x0c 0x68 0x01 0x1b 0x01 0x00 0xff 0x6b AVRSimIOPinChangeInterrupt.SimIOPinChangeInterrupt 0x0e 0x68 0x02 0x1b 0x02 0x03 0xff 0x6c AvrSimIOTim8pwmsync2.tim8pwmsync2 0x001c 0x0018 0x001a PORTB 6 PORTB 7 PORTD 0 AvrSimTWI.SimTWI 0x0016 AVRSimIOSPM.SimIOSPM 0x2c 0x99 0xff 0xe1 0xff 0x0E 0x1E 0x0F 0x1F 0x2E 0x3E 0x2F 0x3F 0x4E 0x5E 0x4F 0x5F 0x6E 0x7E 0x6F 0x7F 0x66 0x76 0x67 0x77 0x6A 0x7A 0x6B 0x7B 0xBE 0xFD 0x00 0x01 0x00 0x00 0x00 0x00100060000151501050x0F25625650x072562560505