[ADMIN:FUSE:INTERRUPT_VECTOR:MEMORY:POWER:PACKAGE:CORE:LOCKBIT:PROGRAMMING:IO_MODULE:ICE_SETTINGS]ATmega4061MHZ180RELEASED$1E$95$07[LOW:HIGH]8WDTONWatchdog Timer Always On1EESAVEEEPROM memory is preserved through the chip erase1BOOTSZ1Select boot size0BOOTSZ0Select boot size0BOOTRSTSelect reset vector1SUT1Select start-up time1SUT0Select start-up time0CKSELClock Selection1130x800x00Watchdog timer always on; [WDTON=0]0x400x00Preserve EEPROM memory through the Chip Erase cycle; [EESAVE=0]0x300x30Boot Flash section size=256 words Boot start address=$4F00; [BOOTSZ=11]0x300x20Boot Flash section size=512 words Boot start address=$4E00; [BOOTSZ=10]0x300x10Boot Flash section size=1024 words Boot start address=$4C00; [BOOTSZ=01]0x300x00Boot Flash section size=2048 words Boot start address=$4800; [BOOTSZ=00] ; default value0x080x00Boot Reset vector Enabled (default address=$0000); [BOOTRST=0]0x070x00CKSEL; Start-up time: 14 CK + 0 ms; [CKSEL=0 SUT=00]0x070x02CKSEL; Start-up time: 14 CK + 3.9 ms; [CKSEL=0 SUT=01]0x070x04CKSEL; Start-up time: 14 CK + 62.5 ms; [CKSEL=0 SUT=10]0x070x01CKSEL; Start-up time: 14 CK + 0 ms; [CKSEL=1 SUT=00]0x070x03CKSEL; Start-up time: 14 CK + 3.9 ms; [CKSEL=1 SUT=01]0x070x05CKSEL; Start-up time: 14 CK + 62.5 ms; [CKSEL=1 SUT=10]2OCDENEnable OCD1JTAGENEnable JTAG020x020x00On-Chip Debug Enabled; [OCDEN=0]0x010x00JTAG Interface Enabled; [JTAGEN=0]23$000External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset$002Battery Protection Interrupt$004External Interrupt Request 0$006External Interrupt Request 1$008External Interrupt Request 2$00AExternal Interrupt Request 3$00CPin Change Interrupt 0$00EPin Change Interrupt 1$010Watchdog Timeout Interrupt$0012Wakeup timer overflow$014Timer/Counter 1 Compare Match$016Timer/Counter 1 Overflow$018Timer/Counter0 Compare A Match$01ATimer/Counter0 Compare B Match$001CTimer/Counter0 Overflow$001ETwo-Wire Bus Connect/Disconnect$0020Two-Wire Serial Interface$0022Voltage ADC Conversion Complete$0024Coulomb Counter ADC Conversion Complete$0026Coloumb Counter ADC Regular Current$0028Coloumb Counter ADC Accumulator$02AEEPROM Ready$02CStore Program Memory ReadyAVRSimMemory8bit.SimMemory8bit409605122048$1000N/A$00$3F$60$FF$20$FFNA0xF80x010x02NA0xF70x010x020x040x08NA0xF60x010x020x040x080x100x200x400x80NA0xF50x010x020x040x080x100x200x400x80NA0xF40x010x020x040x08NA0xF30x010x020x040x080x100x20NA0xF20x010x020x040x080x100x200x400x80NA0xF10x010x020x040x08NA0xF00x010x020x040x080x100x20NA0xE90x010x020x040x080x100x200x400x80NA0xE80x010x020x040x080x100x200x400x80NA0xE70x010x020x040x080x100x200x400x80NA0xE60x010x020x040x080x100x200x400x80NA0xE50x010x020x040x100x200x40NA0xE40x010x020x040x080x100x200x80NA0xE30x010x020x040x080x100x200x400x80NA0xE20x010x020x040x080x100x200x400x80NA0xE10x010x020x040x080x100x200x400x80NA0xE00x010x020x040x080x100x200x400x80NA0xD10x010x020x040x080x100x200x400x80NA0xD00x010x020x040x080x100x200x80NA0xC00x010x02NA0xBE0x010x020x040x400x80NA0xBD0x020x040x080x100x200x400x80NA0xBC0x010x040x080x100x200x400x80NA0xBB0x010x020x040x080x100x200x400x80NA0xBA0x010x020x040x080x100x200x400x80NA0xB90x010x020x080x100x200x400x80NA0xB80x010x020x040x080x100x200x400x80NA0x890x010x020x040x080x100x200x400x80NA0x880x010x020x040x080x100x200x400x80NA0x850x010x020x040x080x100x200x400x80NA0x840x010x020x040x080x100x200x400x80NA0x810x010x020x040x08NA0x7E0x010x020x040x08NA0x7C0x010x020x040x08NA0x7A0x010x020x040x08NA0x790x010x020x040x08NA0x780x010x020x040x080x100x200x400x80NA0x6F0x010x02NA0x6E0x010x020x04NA0x6C0x010x020x040x080x100x200x400x80NA0x6B0x010x020x040x080x100x200x400x80NA0x690x010x020x040x080x100x200x400x80NA0x680x010x02NA0x660x010x020x040x080x100x200x400x80NA0x640x010x020x040x08NA0x620x010x020x040x080x100x200x400x80NA0x600x010x020x040x080x100x200x400x800x3F0x5F0x010x020x040x080x100x200x400x800x3E0x5E0x010x020x040x080x100x200x400x800x3D0x5D0x010x020x040x080x100x200x400x800x370x570x010x020x040x080x100x200x400x800x350x550x010x020x100x800x340x540x010x020x040x080x100x330x530x010x020x040x080x310x510x2B0x4B0x010x020x040x080x100x200x400x800x2A0x4A0x010x020x040x080x100x200x400x800x280x480x010x020x040x080x100x200x400x800x270x470x010x020x040x080x100x200x400x800x260x460x010x020x040x080x100x200x400x800x250x450x010x020x040x080x400x800x240x440x010x020x100x200x400x800x230x430x010x800x220x420x010x210x410x010x020x040x080x100x200x400x800x200x400x010x020x040x080x100x200x400x800x1F0x3F0x010x020x040x080x100x200x1E0x3E0x010x020x040x080x100x200x400x800x1D0x3D0x010x020x040x080x1C0x3C0x010x020x040x080x1B0x3B0x010x020x160x360x010x020x150x350x010x020x040x0B0x2B0x010x020x0A0x2A0x010x020x090x290x010x020x080x280x010x050x250x010x020x040x080x100x200x400x800x040x240x010x020x040x080x100x200x400x800x030x230x010x020x040x080x100x200x400x800x020x220x010x020x040x080x100x200x400x800x010x210x010x020x040x080x100x200x400x800x000x200x010x020x040x080x100x200x400x80$4800$4FFF$0$47FF6425640$4F00$4F0051280$4E00$4E001024160$4C00$4C002048320$4800$48001MHz85CTBD mATBD mATBD uA[LQFP]48[SGND][PA0:ADC0:PCINT0][PA1:ADC1:PCINT1][PA2:ADC2:PCINT2][PA3:ADC3:PCINT3][VREG][VCC][GND][PA4:ADC4:INT0:PCINT4][PA5:INT1:PCINT5][PA6:INT2:PCINT6][PA7:INT3:PCINT7]['RESET][XTAL1][XTAL2][GND][PB0:TDO:PCINT8][PB1:TDI:PCINT9][PB2:TMS:PCINT10][PB3:TCK:PCINT11][PB4:PCINT12][PB5:PCINT13][SCL][SDA][PB6:OC0A:PCINT14][PB7:OC0B:PCINT15][PD0:T0][PD1][GND][PC0][BATT][OPC][OC][VFET][OD][PVT][GND][PV4][PV3][PV2][PV1][NV][VREF][VREFGND][PPI][PI][NI][NNI]V2EAVRSimCoreV2.SimCoreV2[][][]32$00$1B$1A$1D$1C$1F$1E[LB1 = 1 : LB2 = 1] No memory lock features enabled. [LB1 = 0 : LB2 = 1] Further programming of Flash and EEPROM is enabled. [LB1 = 0 : LB2 = 0] Same as previous, but verify is also disabled6110x030x03Mode 1: No memory lock features enabled0x030x02Mode 2: Further programming disabled0x030x00Mode 3: Further programming and verification disabled0x0C0x0CApplication Protection Mode 1: No lock on SPM and LPM in Application Section0x0C0x08Application Protection Mode 2: SPM prohibited in Application Section0x0C0x00Application Protection Mode 3: LPM and SPM prohibited in Application Section0x0C0x04Application Protection Mode 4: LPM prohibited in Application Section0x300x30Boot Loader Protection Mode 1: No lock on SPM and LPM in Boot Loader Section0x300x20Boot Loader Protection Mode 2: SPM prohibited in Boot Loader Section0x300x00Boot Loader Protection Mode 3: LPM and SPM prohibited in Boot Loader Section0x300x10Boot Loader Protection Mode 4: LPM prohibited in Boot Loader SectionLB1Lock bitLB2Lock bitBLB01Boot Lock bitBLB02Boot Lock bitBLB11Boot lock bitBLB12Boot lock bit0x00,4.0 MHz1284[AD_CONVERTER:EXTERNAL_INTERRUPT:TIMER_COUNTER_1:WAKEUP_TIMER:BATTERY_PROTECTION:FET:COULOMB_COUNTER:CELL_BALANCING:CPU:WATCHDOG:TIMER_COUNTER_0:PORTA:PORTB:PORTC:PORTD:BOOT_LOAD:TWI:BANDGAP:EEPROM][VADMUX:VADCH:VADCL:VADCSR]
[VADCH:VADCL]
io_analo.bmp12-bit resolution Sigmal-Delta ADC with +/-1 LSB Accuracy. 512 us conversion time.VADMUXThe VADC multiplexer Selection RegisterNA0x7Cio_analo.bmpYVADMUX3Analog Channel and Gain Selection BitsThe value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).RW0VADMUX2Analog Channel and Gain Selection BitsThe value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).RW0VADMUX1Analog Channel and Gain Selection BitsThe value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).RW0VADMUX0Analog Channel and Gain Selection BitsThe value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).RW0VADCHVADC Data Register High ByteWhen VADCL is read, the Voltage ADC Data Register is not updated until VADCH is read. Consequently if no more than 8-bit precision is required, it is sufficient to read VADCH. Otherwise, VADCL must be read first, then VADCH.NA0x79io_analo.bmpNVADC11ADC Data Register High Byte Bit 3R0VADC10ADC Data Register High Byte Bit 2R0VADC9ADC Data Register High Byte Bit 1R0VADC8ADC Data Register High Byte Bit 0R0VADCLVADC Data Register Low ByteWhen VADCL is read, the Voltage ADC Data Register is not updated until VADCH is read. Consequently if no more than 8-bit precision is required, it is sufficient to read VADCH. Otherwise, VADCL must be read first, then VADCH.NA0x78io_analo.bmpNVADC7ADC Data Register Low Byte Bit 7R0VADC6ADC Data Register Low Byte Bit 6R0VADC5ADC Data Register Low Byte Bit 5R0VADC4ADC Data Register Low Byte Bit 4R0VADC3ADC Data Register Low Byte Bit 3R0VADC2ADC Data Register Low Byte Bit 2R0VADC1ADC Data Register Low Byte Bit 1R0VADC0ADC Data Register Low Byte Bit 0R0VADCSRThe VADC Control and Status registerNA0x7Aio_flag.bmpYVADENVADC EnableWriting this bit to one enables V-ADC Conversion. By writing it to zero, the V-ADC is turned off. Turning the V-ADC off while a conversion is in progress will terminate this conversionRW0VADSCVADC Satrt ConversionWrite this bit to one to start a new conversion of the selected channel. VADSC will read as one as long as the conversion is not finished. When the conversion is complete, it returns to zero. Writing zero to this bit has no effect.RW0VADCCIFVADC Conversion Complete Interrupt FlagThis bit is set when a V-ADC conversion completes and the data registers are updated.V-ADC Conversion complete Interrupt is executed if the VADCCIE bit and the I-bit in S-REG are set. VADCCIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, VADCCIF is cleared by writing a logical one to the flag. Beware that if doing a Read-Modify-Write on VADCSR, a pending interrupt can be disabled.RW0VADCCIEVADC Conversion Complete Interrupt EnableWhen this bit is written to one and the I-Bit in SREG is set, the V-ADC Conversion Complete Interrupt is activatedRW0[EICRA:EIMSK:EIFR:PCICR:PCIFR:PCMSK1:PCMSK0]
[PCMSK1:PCMSK0]
io_ext.bmpThe external interrupts are triggered by the INT7:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT7:0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The external inter-rupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the Exter-nal Interrupt Control Registers - EICRA (INT3:0) and EICRB (INT7:4). When the external interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT7:4 requires the presence of an I/O clock, described in “Clock Systems and their Distribution” on page 29. Low level interrupts and the edge interrupt on INT3:0 are detected asynchronously. This implies that these inter-rupts can be used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode. Note that if a level triggered interrupt is used for wake-up from Power Down Mode, the changed level must be held for some time to wake up the MCU. This makes the MCU less sensitive to noise. The changed level is sampled twice by the watchdog oscillator clock. The period of the watchdog oscillator is 1 µs (nominal) at 5.0V and 25°C. The frequency of the watchdog oscillator is voltage dependent as shown in the Electrical Characteristics section. The MCU will wake up if the input has the required level during this sampling or if it is held until the end of the start-up time. The start-up time is defined by the SUT fuses as described in “Clock Systems and their Distribution” on page 29. If the level is sampled twice by the watchdog oscillator clock but disappears before the end of the start-up time, the MCU will still wake up, but no interrupt will be generated. The required level must be held long enough for the MCU to complete the wake up to trigger the level interruEICRAExternal Interrupt Control Register The External Interrupt Control Register A contains control bits for interrupt sense control.NA0x69io_flag.bmpYISC31External Interrupt Sense Control 3 Bit 1 The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT1 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt. RW0ISC30External Interrupt Sense Control 3 Bit 0The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT1 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt. RW0ISC21External Interrupt Sense Control 2 Bit 1The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT1 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt. RW0ISC20External Interrupt Sense Control 2 Bit 0The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT1 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt. RW0ISC11External Interrupt Sense Control 1 Bit 1 The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT1 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt. RW0ISC10External Interrupt Sense Control 1 Bit 0The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT1 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt. RW0ISC01External Interrupt Sense Control 0 Bit 1 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT0 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt. RW0ISC00External Interrupt Sense Control 0 Bit 0The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT0 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt. RW0EIMSKExternal Interrupt Mask Register0x1D0x3Dio_flag.bmpYINT3External Interrupt Request 1 EnableWhen the INT3 bit is set (one)and the I-bit in the Status Register (SREG)is set (one),the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10)in the External Interrupt Control Register A (EICRA)define whether the external interrupt is activated on rising and/or falling edge of the INT1 pin or level sensed.Activity on the pin will cause an interrupt request even if INT1 is configured as an output.The corresponding interrupt of External Interrupt Request 1 is executed from the INT1 interrupt vector. RW0INT2External Interrupt Request 1 EnableWhen the INT2 bit is set (one)and the I-bit in the Status Register (SREG)is set (one),the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10)in the External Interrupt Control Register A (EICRA)define whether the external interrupt is activated on rising and/or falling edge of the INT1 pin or level sensed.Activity on the pin will cause an interrupt request even if INT1 is configured as an output.The corresponding interrupt of External Interrupt Request 1 is executed from the INT1 interrupt vector. RW0INT1External Interrupt Request 1 EnableWhen the INT1 bit is set (one)and the I-bit in the Status Register (SREG)is set (one),the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10)in the External Interrupt Control Register A (EICRA)define whether the external interrupt is activated on rising and/or falling edge of the INT1 pin or level sensed.Activity on the pin will cause an interrupt request even if INT1 is configured as an output.The corresponding interrupt of External Interrupt Request 1 is executed from the INT1 interrupt vector. RW0INT0External Interrupt Request 0 EnableWhen the INT0 bit is set (one)and the I-bit in the Status Register (SREG)is set (one),the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00)in the External Interrupt Control Register A (EICRA)define whether the external interrupt is activated on rising and/or falling edge of the INT0 pin or level sensed.Activity on the pin will cause an interrupt request even if INT0 is configured as an output.The corresponding interrupt of External Interrupt Request 0 is executed from the INT0 interrupt vector. RW0EIFRExternal Interrupt Flag Register0x1C0x3Cio_flag.bmpYINTF3External Interrupt Flag 3When an edge or logic change on the INT1 pin triggers an interrupt request,INTF1 becomes set (one).If the I-bit in SREG and the INT1 bit in EIMSK are set (one),the MCU will jump to the corresponding interrupt vector.The flag is cleared when the interrupt routine is executed.Alternatively,the flag can be cleared by writing a logical one to it.This flag is always cleared when INT0 is configured as a level interrupt. RW0INTF2External Interrupt Flag 2When an edge or logic change on the INT1 pin triggers an interrupt request,INTF1 becomes set (one).If the I-bit in SREG and the INT1 bit in EIMSK are set (one),the MCU will jump to the corresponding interrupt vector.The flag is cleared when the interrupt routine is executed.Alternatively,the flag can be cleared by writing a logical one to it.This flag is always cleared when INT0 is configured as a level interrupt. RW0INTF1External Interrupt Flag 1When an edge or logic change on the INT1 pin triggers an interrupt request,INTF1 becomes set (one).If the I-bit in SREG and the INT1 bit in EIMSK are set (one),the MCU will jump to the corresponding interrupt vector.The flag is cleared when the interrupt routine is executed.Alternatively,the flag can be cleared by writing a logical one to it.This flag is always cleared when INT0 is configured as a level interrupt. RW0INTF0External Interrupt Flag 0When an edge or logic change on the INT0 pin triggers an interrupt request,INTF0 becomes set (one).If the I-bit in SREG and the INT0 bit in EIMSK are set (one),the MCU will jump to the corresponding interrupt vector.The flag is cleared when the interrupt routine is executed.Alternatively,the flag can be cleared by writing a logical one to it.This flag is always cleared when INT0 is configured as a level interrupt. RW0PCICRPin Change Interrupt Control RegisterNA0x68io_flag.bmpYPCIE1Pin Change Interrupt Enable 1When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 1 is enabled. Any change on any enabled PCINT15..8 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI1 Interrupt Vector. PCINT15..8 pins are enabled individually by the PCMSK1 Register.RW0PCIE0Pin Change Interrupt Enable 0When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0 Interrupt Vector. PCINT7..0 pins are enabled individually by the PCMSK0 Register.RW0PCIFRPin Change Interrupt Flag Register0x1B0x3Bio_flag.bmpYPCIF1Pin Change Interrupt Flag 1When a logic change on any PCINT15..8 pin triggers an interrupt request, PCIF1 becomes set (one). If the I-bit in SREG and the PCIE1 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.RW0PCIF0Pin Change Interrupt Flag 1When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0 becomes set (one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.RW0PCMSK1Pin Change Enable Mask Register 1Each PCINT15..8-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT15..8 is set and the PCIE1 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT15..8 is cleared, pin change interrupt on the corresponding I/O pin is disabled.NA0x6Cio_flag.bmpNPCINT15Pin Change Enable Mask 15RW0PCINT14Pin Change Enable Mask 14RW0PCINT13Pin Change Enable Mask 13RW0PCINT12Pin Change Enable Mask 12RW0PCINT11Pin Change Enable Mask 11RW0PCINT10Pin Change Enable Mask 10RW0PCINT9Pin Change Enable Mask 9RW0PCINT8Pin Change Enable Mask 8RW0PCMSK0Pin Change Enable Mask Register 0Each PCINT7..0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is cleared, pin change interrupt on the corresponding I/O pin is disabled.NA0x6Bio_flag.bmpNPCINT7Pin Change Enable Mask 7RW0PCINT6Pin Change Enable Mask 6RW0PCINT5Pin Change Enable Mask 5RW0PCINT4Pin Change Enable Mask 4RW0PCINT3Pin Change Enable Mask 3RW0PCINT2Pin Change Enable Mask 2RW0PCINT1Pin Change Enable Mask 1RW0PCINT0Pin Change Enable Mask 0RW0[TCCR1B:TCNT1H:TCNT1L:OCR1AL:OCR1AH:TIMSK1:TIFR1:GTCCR]
[TCNT1H:TCNT1L];[OCR1AH:OCR1AL]
io_timer.bmpTCCR1BTimer/Counter1 Control Register BNA0x81io_flag.bmpYCTC1Clear Timer/Counter on Compare MatchRW0CS12Clock Select1 bit 2RW0CS11Clock Select1 bit 1RW0CS10Clock Select1 bit 0RW0TCNT1HTimer Counter 1 High ByteNA0x85io_timer.bmpNTCNT1H7Timer Counter 1 High Byte bit 7RW0TCNT1H6Timer Counter 1 High Byte bit 6RW0TCNT1H5Timer Counter 1 High Byte bit 5RW0TCNT1H4Timer Counter 1 High Byte bit 4RW0TCNT1H3Timer Counter 1 High Byte bit 3RW0TCNT1H2Timer Counter 1 High Byte bit 2RW0TCNT1H1Timer Counter 1 High Byte bit 1RW0TCNT1H0Timer Counter 1 High Byte bit 0RW0TCNT1LTimer Counter 1 Low ByteNA0x84io_timer.bmpNTCNT1L7Timer Counter 1 Low Byte bit 7RW0TCNT1L6Timer Counter 1 Low Byte bit 6RW0TCNT1L5Timer Counter 1 Low Byte bit 5RW0TCNT1L4Timer Counter 1 Low Byte bit 4RW0TCNT1L3Timer Counter 1 Low Byte bit 3RW0TCNT1L2Timer Counter 1 Low Byte bit 2RW0TCNT1L1Timer Counter 1 Low Byte bit 1RW0TCNT1L0Timer Counter 1 Low Byte bit 0RW0OCR1ALOutput Compare Register 1A Low byteNA0x88io_flag.bmpNOCR1AL7RW0OCR1AL6RW0OCR1AL5RW0OCR1AL4RW0OCR1AL3RW0OCR1AL2RW0OCR1AL1RW0OCR1AL0RW0OCR1AHOutput Compare Register 1A High byteNA0x89io_flag.bmpNOCR1AH7RW0OCR1AH6RW0OCR1AH5RW0OCR1AH4RW0OCR1AH3RW0OCR1AH2RW0OCR1AH1RW0OCR1AH0RW0TIMSK1Timer/Counter Interrupt Mask RegisterNA0x6Fio_flag.bmpYOCIE1ATimer/Counter1 Output Compare Interrupt EnableRW0TOIE1Timer/Counter1 Overflow Interrupt EnableRW0TIFR1Timer/Counter Interrupt Flag register0x160x36io_flag.bmpYOCF1ATimer/Counter1 Output Compare Flag ARW0TOV1Timer/Counter1 Overflow FlagRW0GTCCRGeneral Timer/Counter Control Register0x230x43io_flag.bmpYTSMTimer/Counter Synchronization ModeRW0PSRSYNCPrescaler ResetRW0[WUTCSR]io_timer.bmpt8pwm1_01WUTCSRWake-up Timer Control RegisterNA0x62io_flag.bmpYWUTIFWake-up Timer Interrupt FlagThe bit WUTIF is set (one) when an overflow occurs in the Wake-up Timer. WUTIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, WUTIE (Wake-up Timer Interrupt Enable), and WUTIF are set (one), the Wake-up Timer interrupt is executed.RW0WUTIEWake-up Timer Interrupt EnableWhen the WUTIE bit and the I-bit in the Status Register are set (one), the Wake-up Timer interrupt is enabled. The corresponding interrupt is executed if a Wake-up Timer overflow occurs, i.e., when the WUTIF bit is set .RW0WUTCFWake-up timer Calibration FlagThe WUTCF bit is set after every 256 Slow RC OScillator clocks (2 ms @ 131 kHz)RW0WUTRWake-up Timer ResetWhen WUTR is written to one, the Wake-up Timer is reset, and starts counting from zero. The WUTR bit is automatically cleared to zero after the reset has been performed.RW0WUTEWake-up Timer EnableWhen the WUTE is set (one) the Wake-up Timer is enabled, and the WUTE is cleared (zero) the Wake-up Timer function is disabled.RW0WUTP2Wake-up Timer Prescaler Bit 2The WUTP2, WUTP1 and WUTP0 bits determine the Wake-up Timer prescaling when the Wake-up Timer is enabled. The different prescaling values and their corresponding time-out periods are shown in the datasheet.RW0WUTP1Wake-up Timer Prescaler Bit 1The WUTP2, WUTP1 and WUTP0 bits determine the Wake-up Timer prescaling when the Wake-up Timer is enabled. The different prescaling values and their corresponding time-out periods are shown in the datasheet.RW0WUTP0Wake-up Timer Prescaler Bit 0The WUTP2, WUTP1 and WUTP0 bits determine the Wake-up Timer prescaling when the Wake-up Timer is enabled. The different prescaling values and their corresponding time-out periods are shown in the datasheet.RW0[BPPLR:BPCR:CBPTR:BPOCD:BPSCD:BPDUV:BPIR]io_analo.bmpBPPLRBattery Protection Parameter Lock RegisterNA0xF8io_analo.bmpYBPPLEBattery Protection Parameter Lock EnableRW0BPPLBattery Protection Parameter LockRW0BPCRBattery Protection Control RegisterNA0xF7io_analo.bmpYDUVDRW0SCDRW0DCDRW0CCDRW0CBPTRCurrent Battery Protection Timing RegisterNA0xF6io_analo.bmpYSCPT3RW0SCPT2RW0SCPT1R0SCPT0RW0OCPT3RW0OCPT2RW0OCPT1RW0OCPT0RW0BPOCDBattery Protection OverCurrent Detection Level RegisterNA0xF5io_analo.bmpYDCDL3RW0DCDL2RW0DCDL1R0DCDL0RW0CCDL3RW0CCDL2RW0CCDL1RW0CCDL0RW0BPSCDBattery Protection Short-Circuit Detection Level RegisterNA0xF4io_analo.bmpYSCDL3RW0SCDL2RW0SCDL1RW0SCDL0RW0BPDUVBattery Protection Deep Under Voltage RegisterNA0xF3io_analo.bmpYDUVT1RW0DUVT0RW0DUDL3RW0DUDL2RW0DUDL1RW0DUDL0RW0BPIRBattery Protection Interrupt RegisterNA0xF2io_analo.bmpYDUVIFDeep Under-voltage Early Warning Interrupt FlagRW0COCIFCharge Over-current Protection Activated Interrupt FlagRW0DOCIFRW0SCIFRW0DUVIEDeep Under-voltage Early Warning Interrupt EnableRW0COCIERW0DOCIERW0SCIERW0[FCSR]io_analo.bmpFCSRNA0xF0io_analo.bmpYPWMOCPulse Width Modulation of OC outputWhen the PWMOC is cleared (zero), the CFE bit and the battery protection circuitry controls the OC output. When this bit is set (one), the OC output will be controlled by the PWM output from the 8-bit Timer/Counter0 and the battery protection circuitry. RW0PWMOPCPulse Width Modulation Modulation of OPC outputWhen the PWMOPC is cleared (zero), the PFD bit and the battery protection circuitry controls the OPC output. When this bit is set (one), the OC output will be controlled by the PWM output from the 8-bit Timer/Counter0 and the battery protection circuitry. RW0CPSCurrent Protection StatusThe CPTS bit shows the status of the Current Protection. This bit is set (one) when the Current Protection Timer is activated, and is cleared (zero) when the hold-off time has elapsed. RW0DFEDischarge FET EnableWhen the DFE bit is cleared (zero), the Discharge FET will be disabled regardless of the state of the Battery Protection circuitry. When this bit is set (one), the Discharge FET state is determined by the Battery Protection circuitry. This bit will be cleared when CURRENT_PROTECTION is set (one). RW0CFECharge FET EnableWhen the CFE bit is cleared (zero), the Charge FET will be disabled regardless of the state of the Battery Protection circuitry. When this bit is set (one), the Charge FET state is determined by the Battery Protection circuitry. This bit will be cleared when CURRENT_PROTECTION is set (one). RW0PFDPrecharge FET disableThe PFD bit provides complete control of the Precharge FET. When the PFD bit is cleared (zero), the Precharge FET will be enabled. When the PFD bit is set (one), the Precharge FET will be disabled. This bit will be set when CURRENT_PROTECTION is set (one).RW0[CADCSRA:CADCSRB:CADICH:CADICL:CADAC3:CADAC2:CADAC1:CADAC0:CADRCC:CADRDC]
[CADICH:CADICL];[CADAC3:CADAC2:CADAC1:CADAC0]
io_analo.bmpCoulombCounter_m406CADCSRACC-ADC Control and Status Register ANA0xE4io_analo.bmpYCADENWhen the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled. RW0CADUBCC_ADC Update BusyRW0CADAS1CC_ADC Accumulate Current Select Bit 1The CADAS bits select the conversion time for the Accumulate Current output. Please refer to table 45 in the manual.RW0CADAS0CC_ADC Accumulate Current Select Bit 0The CADAS bits select the conversion time for the Accumulate Current output. Please refer to table 45 in the manual.RW0CADSI1The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. RW0CADSI0The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. RW0CADSEWhen the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode.RW0CADCSRBCC-ADC Control and Status Register BNA0xE5io_analo.bmpYCADACIECC-ADC Accumulate Current Interrupt Enable RW0CADRCIERegular Current Interrupt EnableWhen the CADACIE bit is set (one), and the I-bit in the Status Register is set (one), the CC-ADC Accumulate Current Interrupt is enabled. RW0CADICIECAD Instantenous Current Interrupt EnableThe CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43. RW0CADACIFCC-ADC Accumulate Current Interrupt FlagThe CADACIF bit is set (one) after the Accumulate Current conversion has completed. The CC-ADC Accumulate Current Interrupt is executed if the CADAIE bit and the I-bit in SREG are set (one). CADACIF is cleared by hardware when executing the corresponding Interrupt Handling Vector. Alternatively, CADACIF is cleared by writing a logic one to the flag. he CADRCIF bit is set (one) when the absolute value of the result of the last CC-ADC conversion is greater than, or equal to, the compare values set by the CC-ADC Regular Charge/Discharge Current Level Registers. A positive value is compared to the Regular Charge Current Level, and a negative value is compared to the Regular Discharge Current Level. The CC-ADC Regular Current Interrupt is executed if the CADRCIE bit and the I-bit in SREG are set (one). CADRCIF is cleared by hardware when executing the corresponding Interrupt Handling vector. Alternatively, CADRCIF is cleared by writing a logic one to the flag.RW0CADRCIFCC-ADC Accumulate Current Interrupt FlagThe CADACIF bit is set (one) after the Accumulate Current conversion has completed. The CC-ADC Accumulate Current Interrupt is executed if the CADAIE bit and the I-bit in SREG are set (one). CADACIF is cleared by hardware when executing the corresponding Interrupt Handling Vector. Alternatively, CADACIF is cleared by writing a logic one to the flag. he CADRCIF bit is set (one) when the absolute value of the result of the last CC-ADC conversion is greater than, or equal to, the compare values set by the CC-ADC Regular Charge/Discharge Current Level Registers. A positive value is compared to the Regular Charge Current Level, and a negative value is compared to the Regular Discharge Current Level. The CC-ADC Regular Current Interrupt is executed if the CADRCIE bit and the I-bit in SREG are set (one). CADRCIF is cleared by hardware when executing the corresponding Interrupt Handling vector. Alternatively, CADRCIF is cleared by writing a logic one to the flag.RW0CADICIFCC-ADC Instantaneous Current Interrupt Flag The CADICIF bit is set (one) when a CC-ADC Instantaneous Current conversion is completed. The CC-ADC Instantaneous Current Interrupt is executed if the CADICIE bit and the I-bit in SREG are set (one). CADICIF is cleared by hardware when executing the corresponding Interrupt Handling vector. Alternatively, CADICIF is cleared by writing a logic one to the flag. RW0CADICHCC-ADC Instantaneous CurrentNA0xE9io_analo.bmpNCADICH7When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled. RW0CADICH6RW0CADICH5RW0CADICH4The CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43. RW0CADICH3The CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43. RW0CADICH2The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. RW0CADICH1The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. RW0CADICH0When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode.RW0CADICLCC-ADC Instantaneous CurrentNA0xE8io_analo.bmpNCADICL7When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled. RW0CADICL6RW0CADICL5RW0CADICL4The CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43. RW0CADICL3The CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43. RW0CADICL2The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. RW0CADICL1The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. RW0CADICL0When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode.RW0CADAC3ADC Accumulate CurrentNA0xE3io_analo.bmpNCADAC31R0CADAC30R0CADAC29R0CADAC28R0CADAC27R0CADAC26R0CADAC25R0CADAC24R0CADAC2ADC Accumulate CurrentNA0xE2io_analo.bmpNCADAC23R0CADAC22R0CADAC21R0CADAC20R0CADAC19R0CADAC18R0CADAC17R0CADAC16R0CADAC1ADC Accumulate CurrentNA0xE1io_analo.bmpNCADAC15R0CADAC14R0CADAC13R0CADAC12R0CADAC11R0CADAC10R0CADAC09R0CADAC08R0CADAC0ADC Accumulate CurrentNA0xE0io_analo.bmpNCADAC07R0CADAC06R0CADAC05R0CADAC04R0CADAC03R0CADAC02R0CADAC01R0CADAC00R0CADRCCCC-ADC Regular Charge CurrentThe CC-ADC Regular Charge Current Register determines the threshold level for the Regular Charge Current detection. When the result of a CC-ADC Instantaneous Current conversion is positive with a value greater than, or equal to, the Regular Charge Current level, the CC-ADC Regular Current Interrupt Flag is set. The CC-ADC Regular Charge Current Register is eight bits wide, defining the eight least significant bits of the Regular Charge Current level. The most significant bits of the Regular Charge Current level are always zero. The programmable range for the Regular Charge Current level is given in Table 44.NA0xE6io_analo.bmpNCADRCC7When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled. RW0CADRCC6RW0CADRCC5RW0CADRCC4The CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43. RW0CADRCC3The CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43. RW0CADRCC2The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. RW0CADRCC1The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. RW0CADRCC0When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode.RW0CADRDCCC-ADC Regular Discharge CurrentThe CC-ADC Regular Charge Current Register determines the threshold level for the Regular Charge Current detection. When the result of a CC-ADC Instantaneous Current conversion is positive with a value greater than, or equal to, the Regular Charge Current level, the CC-ADC Regular Current Interrupt Flag is set. The CC-ADC Regular Charge Current Register is eight bits wide, defining the eight least significant bits of the Regular Charge Current level. The most significant bits of the Regular Charge Current level are always zero. The programmable range for the Regular Charge Current level is given in Table 44.NA0xE7io_analo.bmpNCADRDC7When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled. RW0CADRDC6RW0CADRDC5RW0CADRDC4The CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43. RW0CADRDC3The CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43. RW0CADRDC2The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. RW0CADRDC1The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. RW0CADRDC0When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode.RW0[CBCR]io_analo.bmpCBCRCell Balancing Control RegisterNA0xF1io_analo.bmpYCBE4Cell Balancing Enable 4RW0CBE3Cell Balancing Enable 4RW0CBE2Cell Balancing Enable 2RW0CBE1Battery Protection Parameter LockRW0[SREG:SPH:SPL:MCUCR:MCUSR:FOSCCAL:SMCR:GPIOR2:GPIOR1:GPIOR0:CCSR:DIDR0:PRR0]
[SPH:SPL]
io_cpu.bmpSREGStatus Register0x3F0x5Fio_sreg.bmpYIGlobal Interrupt EnableThe global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable bit is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts.RW0TBit Copy StorageThe bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction.RW0HHalf Carry FlagThe half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed information.RW0SSign BitThe S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruc-tion Set Description for detailed information.RW0VTwo's Complement Overflow FlagThe two’s complement overflow flag V supports two’s complement arithmetics. See the Instruction Set Description for detailed information.RW0NNegative FlagThe negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.RW0ZZero FlagThe zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.RW0CCarry FlagThe carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software.RW0SPHStack Pointer HighThe general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the AT90S4414/8515 supports up to 64 kB external SRAM, all 16-bits are used. The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or return from interrupt R0x3E0x5Eio_sph.bmpNSP15Stack pointer bit 15RW0SP14Stack pointer bit 14RW0SP13Stack pointer bit 13RW0SP12Stack pointer bit 12RW0SP11Stack pointer bit 11RW0SP10Stack pointer bit 10RW0SP9Stack pointer bit 9RW0SP8Stack pointer bit 8RW0SPLStack Pointer LowThe general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the AT90S4414/8515 supports up to 64 kB external SRAM, all 16-bits are used. The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or return from interrupt 0x3D0x5Dio_sph.bmpNSP7Stack pointer bit 7RW0SP6Stack pointer bit 6RW0SP5Stack pointer bit 5RW0SP4Stack pointer bit 4RW0SP3Stack pointer bit 3RW0SP2Stack pointer bit 2RW0SP1Stack pointer bit 1RW0SP0Stack pointer bit 0RW0MCUCRMCU Control RegisterThe MCU Control Register contains control bits for general MCU functions.0x350x55io_flag.bmpYJTDJTAG DisableRW0PUDPull-up disableWhen this bit is written to one,the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn registers are configured to enable the pull-ups ({DDxn,PORTxn}=0b01). RW0IVSELInterrupt Vector SelectWhen the IVSEL bit is cleared (zero),the interrupt vectors are placed at the start of the Flash memory.When this bit is set (one),the interrupt vectors are moved to the beginning of the Boot Loader section of the flash.The actual address of the start of the boot flash section is determined by the BOOTSZ fuses. RW0IVCEInterrupt Vector Change EnableThe IVCE bit must be written to logic one to enable change of the IVSEL bit.IVCE is cleared by hardware four cycles after it is written or when IVSEL is written.Setting the IVCE bit will disable interrupts. RW0MCUSRMCU Status RegisterThe MCU Status Register provides information on which reset source caused an MCU reset.0x340x54io_flag.bmpYJTRFJTAG Reset FlagThis bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on reset, or by writing a logic zero to the flag. • Bit 3 - WDRF: Watchdog Reset FlagR/W0WDRFWatchdog Reset FlagThis bit is set if a watchdog reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.R/W0BODRF Brown-out Reset FlagThis bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or byR/W0EXTRFExternal Reset FlagThis bit is set if an external reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.R/W0PORFPower-on reset flagThis bit is set if a power-on reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the reset flags to identify a reset condition, the user should read and then reset the MCUCSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags.R/W0FOSCCALFast Oscillator Calibration ValueWriting the calibration byte to this address will trim the internal oscillator to remove process variations from the oscillator frequency. This is done automatically during chip reset. When OSCCAL is zero, the lowest available frequency is chosen. Writing non-zero values to this register will increase the frequency of the internal oscillator. Writing $FF to the register gives the highest available frequency. The calibrated oscillator is used to time EEPROM and Flash access. If EEPROM or Flash is written, do not calibrate to more than 10% above the nominal frequency. Otherwise, the EEPROM or Flash write may fail. Note that the Oscillator is intended for calibration to 1.0 MHz, 2.0 MHz, 4.0 MHz, or 8.0MHz. Tuning to other values is not guaranteed, as indicated in Table NA0x66io_cpu.bmpNFCAL7Oscillator Calibration Value Bit7R/W0FCAL6Oscillator Calibration Value Bit6R/W0FCAL5Oscillator Calibration Value Bit5R/W0FCAL4Oscillator Calibration Value Bit4R/W0FCAL3Oscillator Calibration Value Bit3R/W0FCAL2Oscillator Calibration Value Bit2R/W0FCAL1Oscillator Calibration Value Bit1R/W0FCAL0Oscillator Calibration Value Bit0R/W0SMCRSleep Mode Control RegisterThe Sleep Mode Control Register contains control bits for power management.0x330x53io_cpu.bmpYSM2Sleep Mode Select bit 2These bits select between the five available sleep modes.RW0SM1Sleep Mode Select bit 1These bits select between the five available sleep modes.RW0SM0Sleep Mode Select bit 0These bits select between the five available sleep modes.RW0SESleep EnableThe SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed.ToRW0GPIOR2General Purpose IO Register 2The ATmega169 contains three General Purpose I/O Registers.These registers can be used for storing any information, and they are particularly useful for storing global variables and status flags.General Purpose I/O Registers within the address range $00 -$1F are directly bit-accessible using the SBI,CBI,SBIS,and SBIC instructions. 0x2B0x4Bio_cpu.bmpNGPIOR27General Purpose IO Register 2 bit 7RW0GPIOR26General Purpose IO Register 2 bit 6RW0GPIOR25General Purpose IO Register 2 bit 5RW0GPIOR24General Purpose IO Register 2 bit 4RW0GPIOR23General Purpose IO Register 2 bit 3RW0GPIOR22General Purpose IO Register 2 bit 2RW0GPIOR21General Purpose IO Register 2 bit 1RW0GPIOR20General Purpose IO Register 2 bit 0RW0GPIOR1General Purpose IO Register 1The ATmega169 contains three General Purpose I/O Registers.These registers can be used for storing any information, and they are particularly useful for storing global variables and status flags.General Purpose I/O Registers within the address range $00 -$1F are directly bit-accessible using the SBI,CBI,SBIS,and SBIC instructions. 0x2A0x4Aio_cpu.bmpNGPIOR17General Purpose IO Register 1 bit 7RW0GPIOR16General Purpose IO Register 1 bit 6RW0GPIOR15General Purpose IO Register 1 bit 5RW0GPIOR14General Purpose IO Register 1 bit 4RW0GPIOR13General Purpose IO Register 1 bit 3RW0GPIOR12General Purpose IO Register 1 bit 2RW0GPIOR11General Purpose IO Register 1 bit 1RW0GPIOR10General Purpose IO Register 1 bit 0RW0GPIOR0General Purpose IO Register 0The ATmega169 contains three General Purpose I/O Registers.These registers can be used for storing any information, and they are particularly useful for storing global variables and status flags.General Purpose I/O Registers within the address range $00 -$1F are directly bit-accessible using the SBI,CBI,SBIS,and SBIC instructions. 0x1E0x3Eio_cpu.bmpNGPIOR07General Purpose IO Register 0 bit 7RW0GPIOR06General Purpose IO Register 0 bit 6RW0GPIOR05General Purpose IO Register 0 bit 5RW0GPIOR04General Purpose IO Register 0 bit 4RW0GPIOR03General Purpose IO Register 0 bit 3RW0GPIOR02General Purpose IO Register 0 bit 2RW0GPIOR01General Purpose IO Register 0 bit 1RW0GPIOR00General Purpose IO Register 0 bit 0RW0CCSRClock Control and Status RegisterNA0xC0io_cpu.bmpYXOE32 kHz Crystal Oscillator EnableThe XOE bit is used to enable the 32 kHz Crystal Oscillator before it is selected as clock source. This allows the Oscillator clock to stabilize prior to use. The 32 kHz Crystal Oscillator requires approximately two seconds to stabilize, this must be timed by the user software. This bit must remain set as long as the ACS bit is set, otherwise the 32 kHz clock to CC-ADC and Wake-up timer will be stopped.RW0ACSAsynchronous Clock SelectThe ACS bit is used to selected the source of the asynchronous clock for the Coulomb Counter ADC and Wake-up Timer. The Slow RC Oscillator is selected when this bit is cleared (zero). The 32 kHz Crystal Oscillator is selected when this bit is set (one).RW0DIDR0Digital Input Disable RegisterNA0x7Eio_cpu.bmpNVADC3DWhen this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled.RW0VADC2DWhen this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled.RW0VADC1DWhen this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled.RW0VADC0DWhen this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled.RW0PRR0Power Reduction Register 0NA0x64io_cpu.bmpYPRTWIPower Reduction TWIWriting a logic one to this bit shuts down the TWI by stopping the clock to the module. When waking up the TWI again, the TWI should be re initialized to ensure proper operation.RW0PRTIM1Power Reduction Timer/Counter1Writing a logic one to this bit shuts down the Timer/Counter1 module. When the, Timer/Counter1 is enabled, operation will continue like before the shutdown.RW0PRTIM0Power Reduction Timer/Counter0Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, operation will continue like before the shutdown.RW0PRVADCPower Reduction V-ADCWriting a logic one to this bit shuts down the V-ADC. The V-ADC must be disabled before shut down.RW0[WDTCSR]io_watch.bmpWDTCSRWatchdog Timer Control RegisterNA0x60io_flag.bmpYWDIFWatchdog Timeout Interrupt FlagRW0WDIEWatchdog Timeout Interrupt EnableRW0WDP3Watchdog Timer Prescaler Bit 3RW0WDCEWatchdog Change EnableRW0WDEWatch Dog EnableWhen the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdogRW0WDP2Watch Dog Timer Prescaler bit 2RW0WDP1Watch Dog Timer Prescaler bit 1RW0WDP0Watch Dog Timer Prescaler bit 0RW0[TCCR0A:TCCR0B:TCNT0:OCR0A:OCR0B:TIMSK0:TIFR0]io_timer.bmptimer8_megaDThe 8-bit Timer/Counter0 can select clock source from CK, prescaled CK, or an external pin. In addition it can be stopped as described in “Timer/Counter0 Control Register - TCCR0” on page 35. The overflow status flag is found in “The Timer/Counter Interrupt Flag Register - TIFR” on page 29. Control signals are found in the Timer/Counter0 Control Register - TCCR0. The interrupt enable/disable settings for Timer/Counter0 are found in “The Timer/Counter Interrupt Mask Regis-ter - TIMSK” on page 28. When Timer/Counter0 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. The 8-bit Timer/Counter0 features both a high resolution and a high accuracy usage with the lower prescaling opportuni-ties. Similarly, the high prescaling opportuni ties make the Timer/Counter0 useful for lower speed functions or exact timing functions with infrequent actionsTCCR0ATimer/Counter0 Control Register0x240x44io_flag.bmpYCOM0A1Force Output CompareRW0COM0A0Waveform Generation ModeRW0COM0B1RW0COM0B0RW0WGM01Clock Select0 bit 1RW0WGM00Clock Select0 bit 0RW0TCCR0BTimer/Counter0 Control Register0x250x45io_flag.bmpYFOC0AForce Output CompareRW0FOC0BWaveform Generation ModeRW0WGM02RW0CS02Clock Select0 bit 2RW0CS01Clock Select0 bit 1RW0CS00Clock Select0 bit 0RW0TCNT0Timer Counter 0The Timer/Counter0 is realized as an up-counter with read and write access. If the Timer/Counter0 is written and a clock source is present, the Timer/Counter0 continues counting in the clock cycle following the write operation.0x260x46io_timer.bmpNTCNT07Timer Counter 0 bit 7RW0TCNT06Timer Counter 0 bit 6RW0TCNT05Timer Counter 0 bit 5RW0TCNT04Timer Counter 0 bit 4RW0TCNT03Timer Counter 0 bit 3RW0TCNT02Timer Counter 0 bit 2RW0TCNT01Timer Counter 0 bit 1RW0TCNT00Timer Counter 0 bit 0RW0OCR0AOutput compare Register A0x270x47io_flag.bmpYOCR0A7RW0OCR0A6RW0OCR0A5RW0OCR0A4RW0OCR0A3RW0OCR0A2RW0OCR0A1RW0OCR0A0RW0OCR0BOutput compare Register B0x280x48io_flag.bmpYOCR0B7RW0OCR0B6RW0OCR0B5RW0OCR0B4RW0OCR0B3RW0OCR0B2RW0OCR0B1RW0OCR0B0RW0TIMSK0Timer/Counter Interrupt Mask RegisterNA0x6Eio_flag.bmpYOCIE0BOutput Compare Interrupt EnableRW0OCIE0AOutput Compare Interrupt EnableRW0TOIE0Overflow Interrupt EnableRW0TIFR0Timer/Counter Interrupt Flag register0x150x35io_flag.bmpYOCF0BOutput Compare FlagRW0OCF0AOutput Compare FlagRW0TOV0Overflow FlagRW0[PORTA:DDRA:PINA]io_port.bmpAVRSimIOPort.SimIOPortPORTAPort A Data Register0x020x22io_port.bmpNPORTA7Port A Data Register bit 7RW0PORTA6Port A Data Register bit 6RW0PORTA5Port A Data Register bit 5RW0PORTA4Port A Data Register bit 4RW0PORTA3Port A Data Register bit 3RW0PORTA2Port A Data Register bit 2RW0PORTA1Port A Data Register bit 1RW0PORTA0Port A Data Register bit 0RW0DDRAPort A Data Direction Register0x010x21io_flag.bmpNDDA7Data Direction Register, Port A, bit 7RW0DDA6Data Direction Register, Port A, bit 6RW0DDA5Data Direction Register, Port A, bit 5RW0DDA4Data Direction Register, Port A, bit 4RW0DDA3Data Direction Register, Port A, bit 3RW0DDA2Data Direction Register, Port A, bit 2RW0DDA1Data Direction Register, Port A, bit 1RW0DDA0Data Direction Register, Port A, bit 0RW0PINAPort A Input PinsThe Port A Input Pins address - PINA - is not a register, and this address enables access to the physical value on each Port A pin. When reading PORTA the Port A Data Latch is read, and when reading PINA, the logical values present on the pins are read.0x000x20io_port.bmpNPINA7Input Pins, Port A bit 7RWHi-ZPINA6Input Pins, Port A bit 6RWHi-ZPINA5Input Pins, Port A bit 5RWHi-ZPINA4Input Pins, Port A bit 4RWHi-ZPINA3Input Pins, Port A bit 3RWHi-ZPINA2Input Pins, Port A bit 2RWHi-ZPINA1Input Pins, Port A bit 1RWHi-ZPINA0Input Pins, Port A bit 0RWHi-Z[PORTB:DDRB:PINB]io_port.bmpAVRSimIOPort.SimIOPortPORTBPort B Data Register0x050x25io_port.bmpNPORTB7Port B Data Register bit 7RW0PORTB6Port B Data Register bit 6RW0PORTB5Port B Data Register bit 5RW0PORTB4Port B Data Register bit 4RW0PORTB3Port B Data Register bit 3RW0PORTB2Port B Data Register bit 2RW0PORTB1Port B Data Register bit 1RW0PORTB0Port B Data Register bit 0RW0DDRBPort B Data Direction Register0x040x24io_flag.bmpNDDB7Port B Data Direction Register bit 7RW0DDB6Port B Data Direction Register bit 6RW0DDB5Port B Data Direction Register bit 5RW0DDB4Port B Data Direction Register bit 4RW0DDB3Port B Data Direction Register bit 3RW0DDB2Port B Data Direction Register bit 2RW0DDB1Port B Data Direction Register bit 1RW0DDB0Port B Data Direction Register bit 0RW0PINBPort B Input PinsThe Port B Input Pins address - PINB - is not a register, and this address enables access to the physical value on each Port B pin. When reading PORTB, the Port B Data Latch is read, and when reading PINB, the logical values present on the pins are read.0x030x23io_port.bmpNPINB7Port B Input Pins bit 7R0PINB6Port B Input Pins bit 6R0PINB5Port B Input Pins bit 5R0PINB4Port B Input Pins bit 4R0PINB3Port B Input Pins bit 3R0PINB2Port B Input Pins bit 2R0PINB1Port B Input Pins bit 1R0PINB0Port B Input Pins bit 0R0[PORTC]io_port.bmpAVRSimIOPort.SimIOPortPORTCPort C Data Register0x080x28io_port.bmpNPORTC0Port C Data Register bit 0RW0[PORTD:DDRD:PIND]io_port.bmpAVRSimIOPort.SimIOPortPORTDData Register, Port D0x0B0x2Bio_port.bmpNPORTD1RW0PORTD0RW0DDRDData Direction Register, Port D0x0A0x2Aio_flag.bmpNDDD1RW0DDD0RW0PINDInput Pins, Port D0x090x29io_port.bmpNPIND1R0PIND0R0[SPMCSR]io_cpu.bmpAVRSimIOSPM.SimIOSPMThe Boot Loader Support provides a real Read While Write self-programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program. The Boot Loader program can use any available data interface and associated proto-col to read code and write (program) that code into the Flash memory, or read the code from the program memory. The program code within the Boot Loader section has the capability to write into the entire Flash, including the Boot Loader Memory. The Boot Loader can thus even modify itself, and it can also erase itself from the code if the feature is not needed anymore. The size of the Boot Loader Memory is configurable with fuses and the Boot Loader has two separate sets of Boot Lock Bits which can be set independently. This gives the user a unique flexibility to select different levels of protection. Boot Loader Features: Read While Write self-programming. Flexibl Boot Memory size. High security (separate Boot Lock bits for a flexible protection). Separate fuse to select reset vector Optimized page (1) size. Code efficient algorithm Efficient read-modify-write supporSPMCSRStore Program Memory Control RegisterThe Store Program Memory Control Register contains the control bits needed to control the Boot Loader operations.0x370x57io_flag.bmpYSPMIESPM Interrupt EnableWhen the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN bit in the SPMCR register is cleared.RW0RWWSBRead While Write Section BusyWhen a self-programming (page erase or page write) operation to the RWW section is initiated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a self-programming operation is completed. Alternatively the RWWSB bit will auto-matically be cleared if a page load operation is initiated.R0SIGRDSignature Row ReadIf this bit is written to one at the same time as SPMEN, the next LPM instruction within three clock cycles will read a byte from the signature row into the destination register. see “Reading the Signature Row from Software” in the datasheet for details. An SPM instruction within four cycles after SIGRD and SPMEN are set will have no effect. This operation is reserved for future use and should not be used.RW0RWWSRERead While Write section read enableWhen programming (page erase or page write) to the RWW section, the RWW section is blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW section, the user software must wait until the programming is completed (SPMEN will be cleared). Then, if the RWWSRE bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles re-enables the RWW section. The RWW section cannot be re-enabled while Flash is busy with a page erase or a page write (SPMEN is set). If the RWWSRE bit is written while the Flash is being loaded, the Flash load operation will abort and the data loaded will be loRW0BLBSETBoot Lock Bit SetIf this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles sets Boot Lock bits, according to the data in R0. The data in R1 and the address in the Z pointer are ignored. The BLBSET bit will automatically be cleared upon completion of the lock bit set, or if no SPM instruction is executed within four clock cycles. An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCR register, will read either the Lock-bits or the Fuse bits (depending on Z0 in the Z pointer) into the destination register. See “Reading the Fuse and Lock Bits from Software” on page 235 for detailsRW0PGWRTPage WriteIf this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPM instruction is exe-cuted within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.RW0PGERSPage EraseIf this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page erase. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a page erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.RW0SPMENStore Program Memory EnableThis bit enables the SPM instruction for the next four clock cycles. If written to one together with either RWWSRE, BLB-SET, PGWRT or PGERS, the following SPM instruction will have a special meaning, see description above. If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z pointer. The LSB of the Z pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During page erase and page write, the SPMEN bit remain high until the operation is completed. Writing any other combination than “10001”, "01001", "00101", "00011" or "00001" in the lower five bits will have no effecRW0[TWBCSR:TWAMR:TWBR:TWCR:TWSR:TWDR:TWAR]io_com.bmpTWI: Simple yet powerful and flexible communications interface, only two bus lines needed. Both master and slave operation supported. Device can operate as transmitter or receiver. 7-bit address space allows up to 128 different slave addresses. Multi-master arbitration support Up to 400 kHz data transfer speed Slew-rate limited output drivers Noise suppression circuitry rejects spikes on bus lines Fully programmable slave address with general call support Address recognition causes wake-up when AVR is in sleep mode The Two-Wire Serial Interface (TWI) is ideally suited to typical microcontroller applications. The TWI protocol allows the systems designer to interconnect up to 128 different devices using only two bidirectional bus lines, one for clock (SCL) andone for data (SDA). The only external hardware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines. All devices connected to the bus have individual addresses, and mechanisms for resolving bus contention are inherent in the TWI TWBCSRTWI Bus Control and Status RegisterThe Bus Connect/Disconnect module is an addition to the TWI Interface. Based on a configuration bit, an interrupt can be generated either when the TWI bus is connected or disconnected.NA0xBEio_com.bmpYTWBCIFTWI Bus Connect/Disconnect Interrupt FlagRW0TWBCIETWI Bus Connect/Disconnect Interrupt EnableRW0TWBDT1TWI Bus Disconnect Time-out PeriodRW0TWBDT0TWI Bus Disconnect Time-out PeriodRW0TWBCIPTWI Bus Connect/Disconnect Interrupt PolarityRW0TWAMRTWI (Slave) Address Mask RegisterThe TWAMR can be loaded with a 7-bit Salve Address mask. Each of the bits in TWAMR can mask (disable) the corresponding address bits in the TWI Address Register (TWAR). If the mask bit is set to one then the address match logic ingnores the compare between the incomming address bit and the corresponding bit in TWAR.NA0xBDio_com.bmpYTWAM6RW0TWAM5RW0TWAM4RW0TWAM3RW0TWAM2RW0TWAM1RW0TWAM0RW0TWBRTWI Bit Rate registerTWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency divider which generates the SCL clock frequency in the master modes. See “Bit Rate Generator Unit” on page 165 for calculating bit rates.NA0xB8io_com.bmpNTWBR7RW0TWBR6RW0TWBR5RW0TWBR4RW0TWBR3RW0TWBR2RW0TWBR1RW0TWBR0RW0TWCRTWI Control RegisterThe TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate a master access by applying a START condition to the bus, to generate a receiver acknowledge, to generate a stop condition, and to control halting of the bus while the data to be written to the bus are written to the TWDR. It also indicates a write collision if data is attempted written to TWDR while the register is inaccessible.NA0xBCio_flag.bmpYTWINTTWI Interrupt FlagThis bit is set by hardware when the TWI has finished its current job and expects application software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the TWI interrupt vector. While the TWINT flag is set, the SCL low period is stretched. The TWINT flag must be cleared by software by writing a logic one to it. Note that this flag is not automatically cleared by hardware when executing the interrupt routine. Also note that clearing this flag starts the operation of the TWI, so all accesses to the TWI Address Register (TWAR), TWI Status Register (TWSR), and TWI Data Register (TWDR) must be complete before clearing this flagRW0TWEATWI Enable Acknowledge BitThe TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is written to one, the ACK pulse is gener-ated on the TWI bus if the following conditions are met: 1. The device’s own slave address has been received. 2. A general call has been received, while the TWGCE bit in the TWAR is set. 3. A data byte has been received in master receiver or slave receiver mode. By writing the TWEA bit to zero, the device can be virtually disconnected from the 2-wire Serial Bus temporarily. Address recognition can then be resumed by writing the TWEA bit to one againRW0TWSTATWI Start Condition BitThe application writes the TWSTA bit to one when it desires to become a master on the 2-wire Serial Bus. The TWI hard-ware checks if the bus is available, and generates a START condition on the bus if it is free. However, if the bus is not free, the TWI waits until a STOP condition is detected, and then generates a new START condition to claim the bus Master sta-tus. TWSTA is cleared by the TWI hardware when the START condition has been transmitted.RW0TWSTOTWI Stop Condition BitWriting the TWSTO bit to one in master mode will generate a STOP condition on the 2-wire Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit is cleared automatically. In slave mode, setting the TWSTO bit can be used to recover from an error condition. This will not generate a STOP condition, but the TWI returns to a well-defined unaddressed slave mode and releases the SCL and SDA lines to a high impedance state.RW0TWWCTWI Write Collition FlagThe TWWC bit is set when attempting to write to the TWI Data Register - TWDR when TWINT is low. This flag is cleared by writing the TWDR register when TWINT is high.RW0TWENTWI Enable BitThe TWEN bit enables TWI operation and activates the TWI interface. When TWEN is written to one, the TWI takes control over the I/O pins connected to the SCL and SDA pins, enabling the slew-rate limiters and spike filters. If this bit is written to zero, the TWI is switched off and all TWI transmissions are terminated, regardless of any ongoing operation.RW0TWIETWI Interrupt EnableWhen this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request will be activated for as long as the TWINT flag is high.RW0TWSRTWI Status RegisterNA0xB9io_flag.bmpYTWS7TWI StatusBits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient cRW0TWS6TWI StatusBits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient coRW0TWS5TWI StatusBits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient cRW0TWS4TWI StatusBits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient coRW0TWS3TWI StatusBits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient coRW0TWPS1TWI PrescalerBits 1..0: These bits can be read and written, and control the bit rate prescaler. See “Bit Rate Generator Unit” on page 165 for calculating bit rates.RW0TWPS0TWI PrescalerBits 1..0: These bits can be read and written, and control the bit rate prescaler. See “Bit Rate Generator Unit” on page 165 for calculating bit rates.RW0TWDRTWI Data registerIn transmit mode, TWDR contains the next byte to be transmitted. In receive mode, the TWDR contains the last byte received. It is writable while the TWI is not in the process of shifting a byte. This occurs when the TWI interrupt flag (TWINT) is set by hardware. Note that the data register cannot be initialized by the user before the first interrupt occurs. The data in TWDR remains stable as long as TWINT is set. While data is shifted out, data on the bus is simultaneously shifted in. TWDR always contains the last byte present on the bus, except after a wake up from a sleep mode by the TWI interrupt. In this case, the contents of TWDR is undefined. In the case of a lost bus arbitration, no data is lost in the transi-tion from Master to Slave. Handling of the ACK bit is controlled automatically by the TWI logic, the CPU cannot access the ACK bit directlNA0xBBio_com.bmpNTWD7TWI Data Register Bit 7RW1TWD6TWI Data Register Bit 6RW1TWD5TWI Data Register Bit 5RW1TWD4TWI Data Register Bit 4RW1TWD3TWI Data Register Bit 3RW1TWD2TWI Data Register Bit 2RW1TWD1TWI Data Register Bit 1RW1TWD0TWI Data Register Bit 0RW1TWARTWI (Slave) Address registerThe TWAR should be loaded with the 7-bit slave address (in the seven most significant bits of TWAR) to which the TWI will respond when programmed as a slave transmitter or receiver, and not needed in the master modes. In multimaster sys-tems, TWAR must be set in masters which can be addressed as slaves by other masters. The LSB of TWAR is used to enable recognition of the general call address ($00). There is an associated address compar-ator that looks for the slave address (or general call address if enabled) in the received serial address. If a match is found, an interrupt request is generaNA0xBAio_com.bmpYTWA6TWI (Slave) Address register Bit 6RW0TWA5TWI (Slave) Address register Bit 5RW0TWA4TWI (Slave) Address register Bit 4RW0TWA3TWI (Slave) Address register Bit 3RW0TWA2TWI (Slave) Address register Bit 2RW0TWA1TWI (Slave) Address register Bit 1RW0TWA0TWI (Slave) Address register Bit 0RW0TWGCETWI General Call Recognition Enable BitRW0[BGCRR:BGCCR]io_analo.bmpBGCRRBandgap Calibration of Resistor LadderNA0xD1io_analo.bmpNBGCR7Bandgap Calibration of Resistor Ladder Bit 7RW0BGCR6Bandgap Calibration of Resistor Ladder Bit 6RW0BGCR5Bandgap Calibration of Resistor Ladder Bit 5RW0BGCR4Bandgap Calibration of Resistor Ladder Bit 4RW0BGCR3Bandgap Calibration of Resistor Ladder Bit 3RW0BGCR2Bandgap Calibration of Resistor Ladder Bit 2RW0BGCR1Bandgap Calibration of Resistor Ladder Bit 1RW0BGCR0Bandgap Calibration of Resistor Ladder Bit 0RW0BGCCRBandgap Calibration RegisterNA0xD0io_analo.bmpYBGDSetting the BGD bit to one will disable the bandgap voltage reference. This bit must be cleared before enabling CC-ADC or V-ADC, and must remain unset while either ADC is enabled.RW0BGCC5BG Calibration of PTAT Current Bit 5RW0BGCC4BG Calibration of PTAT Current Bit 4These bits are used for trimming of the nominal value of the bandgap reference voltage. These bits are binary caoded, step size is approximately 2mV.RW0BGCC3BG Calibration of PTAT Current Bit 3These bits are used for trimming of the nominal value of the bandgap reference voltage. These bits are binary caoded, step size is approximately 2mV.RW0BGCC2BG Calibration of PTAT Current Bit 2These bits are used for trimming of the nominal value of the bandgap reference voltage. These bits are binary caoded, step size is approximately 2mV.RW0BGCC1BG Calibration of PTAT Current Bit 1These bits are used for trimming of the nominal value of the bandgap reference voltage. These bits are binary caoded, step size is approximately 2mV.RW0BGCC0BG Calibration of PTAT Current Bit 0These bits are used for trimming of the nominal value of the bandgap reference voltage. These bits are binary caoded, step size is approximately 2mV.RW0[EEARH:EEARL:EEDR:EECR]
[EEARH:EEARL]
io_cpu.bmpEEARHEEPROM Address Register High Byteio_cpu.bmp0x220x42NEEAR8EEPROM Read/Write Access Bit 8RW0EEARLEEPROM Address Register Low Byteio_cpu.bmp0x210x41NEEAR7EEPROM Read/Write Access Bit 7RW0EEAR6EEPROM Read/Write Access Bit 6RW0EEAR5EEPROM Read/Write Access Bit 5RW0EEAR4EEPROM Read/Write Access Bit 4RW0EEAR3EEPROM Read/Write Access Bit 3RW0EEAR2EEPROM Read/Write Access Bit 2RW0EEAR1EEPROM Read/Write Access Bit 1RW0EEAR0EEPROM Read/Write Access Bit 0RW0EEDREEPROM Data RegisterFor the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.io_cpu.bmp0x200x40NEEDR7EEPROM Data Register bit 7RW0EEDR6EEPROM Data Register bit 6RW0EEDR5EEPROM Data Register bit 5RW0EEDR4EEPROM Data Register bit 4RW0EEDR3EEPROM Data Register bit 3RW0EEDR2EEPROM Data Register bit 2RW0EEDR1EEPROM Data Register bit 1RW0EEDR0EEPROM Data Register bit 0RW0EECREEPROM Control Registerio_flag.bmp0x1F0x3FYEEPM1EEPROM Programming Mode BitsRWNAEEPM0EEPROM Programming Mode BitsRWNAEERIEEEPROM Ready Interrupt EnableRW0EEMPEEEPROM Master Programming EnableRW0EEMWEEEPEEEPROM Programming EnableRWXEEWEEEREEEPROM Read EnableRW0[JTAGICEmkII:STK500:SIMULATOR:STK500_2]0x0950703FJTAG0x3F,0x0F,0x60,0xF8,0xFF,0x0D,0xB8,0xE00x37,0x0F,0x00,0xE0,0xFF,0x0D,0xB8,0xE00X00,0X00,0X00,0X00,0X00,0X00,0X00,0X000X00,0X00,0X00,0X00,0X00,0X00,0X00,0X000x55,0xDB,0x00,0x57,0x32,0x03,0x00,0x00,0x00,0x00,0x00,0x7F,0x01,0x00,0x03,0x00,0xFF,0x03,0xFF,0x010x50,0xDB,0x00,0x50,0x32,0x03,0x00,0x00,0x00,0x00,0x00,0x6D,0x01,0x00,0x03,0x00,0xD0,0x00,0xFB,0x000x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x000x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x000x310X570X0012840x4F000x4F000x4E000x4C000x48000xF80xA0000x0000,320x0020,640x000x000x000x000x000x000x000x000x3e0x3d0x000x000x000x000x010x010x000x3f0x0950703FPart revision not supported by AVR Studio.0x700110xFF0xFF0xFF00AVRSimCoreV2.SimCoreV2AVRSimMemory8bit.SimMemory8bitAVRSimInterrupt.SimInterrupt130x2a0AVRSimIOPort.SimIOPortYAVRSimIOPort.SimIOPortYAVRSimIOPort.SimIOPortNAVRSimIOPort.SimIOPortYAVRSimIOExtInterrupt.SimIOExtInterrupt0x00040x1D0x010x3A0x010x000x100x690x03AVRSimIOExtInterrupt.SimIOExtInterrupt0x00060x1D0x020x1C0x020x000x200x690x0cAVRSimIOExtInterrupt.SimIOExtInterrupt0x00080x1D0x040x1C0x040x000x400x690x30AVRSimIOExtInterrupt.SimIOExtInterrupt0x000A0x1D0x080x1C0x080x000x800x690xc0AVRSimIOPinChangeInterrupt.SimIOPinChangeInterrupt0x0c0x680x010x1b0x010x000xff0x6bAVRSimIOPinChangeInterrupt.SimIOPinChangeInterrupt0x0e0x680x020x1b0x020x030xff0x6cAvrSimIOTim8pwmsync2.tim8pwmsync20x001c0x00180x001aPORTB6PORTB7PORTD0AvrSimTWI.SimTWI0x0016AVRSimIOSPM.SimIOSPM0x2c0x990xff0xe10xff0x0E 0x1E 0x0F 0x1F 0x2E 0x3E 0x2F 0x3F 0x4E 0x5E 0x4F 0x5F 0x6E 0x7E 0x6F 0x7F 0x66 0x76 0x67 0x77 0x6A 0x7A 0x6B 0x7B 0xBE 0xFD 0x00 0x01 0x00 0x00 0x00 0x00100060000151501050x0F25625650x072562560505