[ADMIN:CORE:INTERRUPT_VECTOR:MEMORY:PACKAGE:POWER:PROGVOLT:LOCKBIT:FUSE:PROGRAMMING:IO_MODULE:ICE_SETTINGS] ATmega8 16MHZ 213 RELEASED $1E $93 $07 V2E AVRSimCoreV2.SimCoreV2 [] [] [] 32 $00 $1B $1A $1D $1C $1F $1E 19 AVRSimInterrupt.SimInterrupt $000 RESET External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset $001 INT0 External Interrupt Request 0 0x5B 0x40 0x5A 0x40 1 $002 INT1 External Interrupt Request 1 0x5B 0x80 0x5A 0x80 1 $003 TIMER2 COMP Timer/Counter2 Compare Match 0x59 0x80 0x58 0x80 1 $004 TIMER2 OVF Timer/Counter2 Overflow 0x59 0x40 0x58 0x40 1 $005 TIMER1 CAPT Timer/Counter1 Capture Event 0x59 0x20 0x58 0x20 1 0x28 0x04 0x28 0x10 1 $006 TIMER1 COMPA Timer/Counter1 Compare Match A 0x59 0x10 0x58 0x10 1 $007 TIMER1 COMPB Timer/Counter1 Compare Match B 0x59 0x08 0x58 0x08 1 $008 TIMER1 OVF Timer/Counter1 Overflow 0x59 0x04 0x58 0x04 1 $009 TIMER0 OVF Timer/Counter0 Overflow 0x59 0x01 0x58 0x01 1 $00A SPI, STC Serial Transfer Complete 0x2D 0x80 0x2E 0x80 1 $00B USART, RXC USART, Rx Complete 0x2A 0x80 0x2B 0x80 1 $00C USART, UDRE USART Data Register Empty 0x2A 0x20 0x2B 0x20 1 $00D USART, TXC USART, Tx Complete 0x2A 0x40 0x2B 0x40 1 $00E ADC ADC Conversion Complete 0x26 0x08 0x26 0x10 1 $00F EE_RDY EEPROM Ready 0x3C 0x08 0x3C 0x02 0 $010 ANA_COMP Analog Comparator 0x28 0x08 0x28 0x10 1 $011 TWI 2-wire Serial Interface 0x56 0x01 0x56 0x80 1 $012 SPM_RDY Store Program Memory Ready 0x57 0x80 0x57 0x01 0 AVRSimMemory8bit.SimMemory8bit 8192 512 1024 $60 0 NA $00 $3F NA NA $20 $5F 0x3F 0x5F 0x010x020x040x080x100x200x400x80 0x3E 0x5E 0x010x020x04 0x3D 0x5D 0x010x020x040x080x100x200x400x80 0x3B 0x5B 0x010x020x400x80 0x3A 0x5A 0x400x80 0x39 0x59 0x010x040x080x100x200x400x80 0x38 0x58 0x010x040x080x100x200x400x80 0x37 0x57 0x010x020x040x080x100x400x80 0x36 0x56 0x010x040x080x100x200x400x80 0x35 0x55 0x010x020x040x080x100x200x400x80 0x34 0x54 0x010x020x040x08 0x33 0x53 0x010x020x04 0x32 0x52 0x010x020x040x080x100x200x400x80 0x31 0x51 0x010x020x040x080x100x200x400x80 0x30 0x50 0x080x020x010x040x10 0x2F 0x4F 0x010x020x040x080x100x200x400x80 0x2E 0x4E 0x010x020x040x080x100x400x80 0x2D 0x4D 0x010x020x040x080x100x200x400x80 0x2C 0x4C 0x010x020x040x080x100x200x400x80 0x2B 0x4B 0x010x020x040x080x100x200x400x80 0x2A 0x4A 0x010x020x040x080x100x200x400x80 0x29 0x49 0x010x020x040x080x100x200x400x80 0x28 0x48 0x010x020x040x080x100x200x400x80 0x27 0x47 0x010x020x040x080x100x200x400x80 0x26 0x46 0x010x020x040x080x100x200x400x80 0x25 0x45 0x010x020x040x080x100x200x400x80 0x24 0x44 0x010x020x040x080x100x200x400x80 0x23 0x43 0x010x020x040x080x100x200x400x80 0x22 0x42 0x010x020x040x08 0x21 0x41 0x010x020x040x080x10 0x20 0x40 0x010x020x040x08 0x20 0x40 0x010x020x040x080x100x200x400x80 0x1F 0x3F 0x01 0x1E 0x3E 0x010x020x040x080x100x200x400x80 0x1D 0x3D 0x010x020x040x080x100x200x400x80 0x1C 0x3C 0x010x020x040x08 0x18 0x38 0x010x020x040x080x100x200x400x80 0x17 0x37 0x010x020x040x080x100x200x400x80 0x16 0x36 0x010x020x040x080x100x200x400x80 0x15 0x35 0x010x020x040x080x100x200x40 0x14 0x34 0x010x020x040x080x100x200x40 0x13 0x33 0x010x020x040x080x100x200x40 0x12 0x32 0x010x020x040x080x100x200x400x80 0x11 0x31 0x010x020x040x080x100x200x400x80 0x10 0x30 0x010x020x040x080x100x200x400x80 0x0F 0x2F 0x010x020x040x080x100x200x400x80 0x0E 0x2E 0x010x400x80 0x0D 0x2D 0x010x020x040x080x100x200x400x80 0x0C 0x2C 0x010x020x040x080x100x200x400x80 0x0B 0x2B 0x010x020x040x080x100x200x400x80 0x0A 0x2A 0x010x020x040x080x100x200x400x80 0x09 0x29 0x010x020x040x080x100x200x400x80 0x08 0x28 0x010x020x040x080x100x200x400x80 0x07 0x27 0x010x020x040x080x200x400x80 0x06 0x26 0x010x020x040x080x100x200x400x80 0x05 0x25 0x010x020x040x080x100x200x400x80 0x04 0x24 0x010x020x040x080x100x200x400x80 0x03 0x23 0x010x020x040x080x100x200x400x80 0x02 0x22 0x010x020x040x080x100x200x400x80 0x01 0x21 0x010x020x080x100x200x400x80 0x00 0x20 0x010x020x040x080x100x200x400x80 $C00 $FFF $0 $BFF 32 128 4 $0 $F80 $F80 256 8 $0 $F00 $F00 512 16 $0 $E00 $E00 1024 32 $0 $C00 $C00 [TQFP] 32 [PD3:IN1] INT1,External Interrupt source 1:The PD3 pin can serve as an external interrupt source. [PD4:XCK:T0] XCK, USART external clock. T0,Timer/Counter0 counter source. [GND] [VCC] [GND] [VCC] [PB6:XTAL1:TOSC1] XTAL1:Chipclock oscillator pin 1.Used for all chipclock sources except internal calibratable RC oscillator.When used as a clock pin,the pin can not be used as an I/O pin.When using internal calibratable RC oscillator as chip clock source,PB6 functions as an ordinary I/O pin. TOSC1:Timer Oscillator pin 1.Used only if internal calibratable RC oscillator is selected as chip clock source,and the asynchronous timer is enabled by the correct setting in ASSR.When the AS2 bit in ASSR is set (one)to enable asynchronous clocking of Timer/Counter1,pin PB6 is disconnected from the port,and becomes the input of the inverting oscillator amplifier.In this mode,a crystal oscillator is connected to this pin,and the pin can not be used as an I/O pin. If PB6 is used as a clock pin,DDB6,PORTB6 and PINB6 will all read [PB7:XTAL2:TOSC2] XTAL2:Chip clock oscillator pin 2.Used as clock pin for all chip clock sources except internal calibratable RC oscillator and external clock.When used as a clock pin,the pin can not be used as an I/O pin.When using internal calibratable RC oscillator or external clock as chipclock sources,PB7 functions as an ordinary I/O pin. TOSC2:Timer Oscillator pin 2.Used only if internal calibratable RC oscillator is selected as chip clock source,and the asynchronous timer is enabled by the correct setting in ASSR.When the AS2 bit in ASSR is set (one)to enable asynchro- nous clocking of Timer/Counter2,pin PB7 is disconnected from the port,and becomes the inverting output of the oscillator amplifier.In this mode,a crystal oscillator is connected to this pin,and the pin can not be used as an I/O pin. If PB7 is used as a clock pin,DDB7,PORTB7 and PINB7 will all read [PD5:T1] T1,Timer/Counter1 counter source. [PD6:AIN0] AIN0,Analog Comparator Positive Input.Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the analog comparator. [PD7:AIN1] AIN1,Analog Comparator Negative Input.Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the analog comparator. [PB0:ICP] ICP -Input Capture Pin:The PB0 pin can act as an input capture pin for Timer/Counter1. [PB1:OC1A] OC1A,Output compare match output:The PB1 pin can serve as an external output for the Timer/Counter1 compare match A.The PB1 pin has to be configured as an output (DDB1 set (one))to serve this function.The OC1A pin is also the output pin for the PWM mode timer function. [PB2:'SS:OC1B] SS:Slave Select input.When the SPI is enabled as a slave,this pin is configured as an input regardless of the setting of DDB4.As a slave,the SPI is activated when this pin is driven low.When the SPI is enabled as a master,the data direction of this pin is controlled by DDB4.When the pin is forced by the SPI to be an input,the pull-up can still be controlled by the PORTB4 bit. OC1B,Output compare match output:The PB2 pin can serve as an external output for the Timer/Counter1 compare match B.The PB2 pin has to be configured as an output (DDB2 set (one))to serve this function.The OC1B pin is also the output pin for the PWM mode timer func [PB3:MOSI:OC2] MOSI:SPI Master data output,slave data input for SPI channel.When the SPI is enabled as a slave,this pin is configured as an input regardless of the setting of DDB5.When the SPI is enabled as a master,the data direction of this pin is controlled by DDB5.When the pin is forced by the SPI to be an input,the pull-up can still be controlled by the PORTB bit. [PB4:MISO] MISO:Master data Input,Slave data Output pin for SPI channel.When the SPI is enabled as a master,this pin is configured as an input regardless of the setting of DDB6.When the SPI is enabled as a slave,the data direction of this pin is controlled by DDB6.When the pin is forced by the SPI to be an input,the pull-up can still be controlled by the PORTB6 bit. [PB5:SCK] SCK:Master clock output,slave clock input pin for SPI channel.When the SPI is enabled as a slave,this pin is configured as an input regardless of the setting of DDB7.When the SPI is enabled as a master,the data direction of this pin is controlled by DDB7.When the pin is forced by the SPI to be an input,the pull-up can still be controlled by the PORTB7 bit. [AVCC] [ADC6] [AREF] [AGND] [ADC7] [PC0:ADC0] PC0 can also be used as ADC input Channel 0.Note that ADC input channel 0 uses analog ground. [PC1:ADC1] PC1 can also be used as ADC input Channel 1.Note that ADC input channel 1 uses analog ground. [PC2:ADC2] PC2 can also be used as ADC input Channel 2.Note that ADC input channel 2 uses analog ground. [PC3:ADC3] PC3 can also be used as ADC input Channel 3.Note that ADC input channel 3 uses analog ground. [PC4:ADC4:SDA] SDA,2-wire Serial Interface Data:When the TWEN bit in TWCR is set (one)to enable the 2-wire Serial Interface,pin PC1 is disconnected from the port and becomes the Serial Data I/O pin for the 2-wire Serial Interface.In this mode,there is a spike filter on the pin to suppress spikes shorter than 0 ns on the input signal,and the pin is driven by an open drain driver with slew-rate limitation. PC4 can also be used as ADC input Channel 4.Note that ADC input channel 4 uses digital ground. [PC5:ADC5:SCL] SCL,2-wire Serial Interface Clock:When the TWEN bit in TWCR is set (one)to enable the 2-wire Serial Interface,pin PC1 is disconnected from the port and becomes the Serial Clock I/O pin for the 2-wire Serial Interface.In this mode,there is a spike filter on the pin to suppress spikes shorter than 0 ns on the input signal,and the pin is driven by an open drain driver with slew-rate limitation. PC can also be used as ADC input Channel 5.Note that ADC input channel uses digital ground. [PC6:'RESET] RESET, Reset pin: When the RSTDISBL fuse is set,this pin functions as a normal I/O pin,and the part will have to rely on Power-On Reset and Brown-Out Reset as its reset sources.When the RSTDISBL fuse is cleared,the reset circuitry is connected to the pin,and the pin can not be used as an I/O pin. If PC6 is used as a reset pin,DDC6,PORTC6 and PINC6 will all read 0. [PD0:RXD] RXD,Receive Data (Data input pin for the USART).When the USART receiver is enabled this pin is configured as an input regardless of the value of DDD0.When the USART forces this pin to be an input,the pull-up can still be controlled by the PORTD0 bit. [PD1:TXD] TXD,Transmit Data (Data output pin for the USART).When the USART transmitter is enabled,this pin is configured as an output regardless of the value of DDD1. [PD2:INT0] INT0,External Interrupt source 0:The PD2 pin can serve as an external interrupt source. UNKNOWN 25C UNKNOWN UNKNOWN UNKNOWN 4.0 5.5 4.0 5.5 [LB1 = 1 : LB2 = 1] No memory lock features enabled. [LB1 = 0 : LB2 = 1] Further programming of Flash and EEPROM is enabled. [LB1 = 0 : LB2 = 0] Same as previous, but verify is also disabled 6 11 0x03 0x03 Mode 1: No memory lock features enabled 0x03 0x02 Mode 2: Further programming disabled 0x03 0x00 Mode 3: Further programming and verification disabled 0x0C 0x0C Application Protection Mode 1: No lock on SPM and LPM in Application Section 0x0C 0x08 Application Protection Mode 2: SPM prohibited in Application Section 0x0C 0x00 Application Protection Mode 3: LPM and SPM prohibited in Application Section 0x0C 0x04 Application Protection Mode 4: LPM prohibited in Application Section 0x30 0x30 Boot Loader Protection Mode 1: No lock on SPM and LPM in Boot Loader Section 0x30 0x20 Boot Loader Protection Mode 2: SPM prohibited in Boot Loader Section 0x30 0x00 Boot Loader Protection Mode 3: LPM and SPM prohibited in Boot Loader Section 0x30 0x10 Boot Loader Protection Mode 4: LPM prohibited in Boot Loader Section LB1 Lock bit LB2 Lock bit BLB01 Boot Lock bit BLB02 Boot Lock bit BLB11 Boot lock bit BLB12 Boot lock bit [LOW:HIGH] 8 BODLEVEL Brown out detector trigger level 1 BODEN Brown out detector enable 1 SUT1 Select start-up time 0 SUT0 Select start-up time 0 CKSEL3 Select Clock Source 0 CKSEL2 Select Clock Source 0 CKSEL1 Select Clock Source 0 CKSEL0 Select Clock Source 1 61 0x80 0x00 Brown-out detection level at VCC=4.0 V; [BODLEVEL=0] 0x80 0x80 Brown-out detection level at VCC=2.7 V; [BODLEVEL=1] 0x40 0x00 Brown-out detection enabled; [BODEN=0] 0x3F 0x00 Ext. Clock; Start-up time: 6 CK + 0 ms; [CKSEL=0000 SUT=00] 0x3F 0x10 Ext. Clock; Start-up time: 6 CK + 4 ms; [CKSEL=0000 SUT=01] 0x3F 0x20 Ext. Clock; Start-up time: 6 CK + 64 ms; [CKSEL=0000 SUT=10] 0x3F 0x01 Int. RC Osc. 1 MHz; Start-up time: 6 CK + 0 ms; [CKSEL=0001 SUT=00] 0x3F 0x11 Int. RC Osc. 1 MHz; Start-up time: 6 CK + 4 ms; [CKSEL=0001 SUT=01] 0x3F 0x21 Int. RC Osc. 1 MHz; Start-up time: 6 CK + 64 ms; [CKSEL=0001 SUT=10]; default value 0x3F 0x02 Int. RC Osc. 2 MHz; Start-up time: 6 CK + 0 ms; [CKSEL=0010 SUT=00] 0x3F 0x12 Int. RC Osc. 2 MHz; Start-up time: 6 CK + 4 ms; [CKSEL=0010 SUT=01] 0x3F 0x22 Int. RC Osc. 2 MHz; Start-up time: 6 CK + 64 ms; [CKSEL=0010 SUT=10] 0x3F 0x03 Int. RC Osc. 4 MHz; Start-up time: 6 CK + 0 ms; [CKSEL=0011 SUT=00] 0x3F 0x13 Int. RC Osc. 4 MHz; Start-up time: 6 CK + 4 ms; [CKSEL=0011 SUT=01] 0x3F 0x23 Int. RC Osc. 4 MHz; Start-up time: 6 CK + 64 ms; [CKSEL=0011 SUT=10] 0x3F 0x04 Int. RC Osc. 8 MHz; Start-up time: 6 CK + 0 ms; [CKSEL=0100 SUT=00] 0x3F 0x14 Int. RC Osc. 8 MHz; Start-up time: 6 CK + 4 ms; [CKSEL=0100 SUT=01] 0x3F 0x24 Int. RC Osc. 8 MHz; Start-up time: 6 CK + 64 ms; [CKSEL=0100 SUT=10] 0x3F 0x05 Ext. RC Osc. - 0.9 MHz; Start-up time: 18 CK + 0 ms; [CKSEL=0101 SUT=00] 0x3F 0x15 Ext. RC Osc. - 0.9 MHz; Start-up time: 18 CK + 4 ms; [CKSEL=0101 SUT=01] 0x3F 0x25 Ext. RC Osc. - 0.9 MHz; Start-up time: 18 CK + 64 ms; [CKSEL=0101 SUT=10] 0x3F 0x35 Ext. RC Osc. - 0.9 MHz; Start-up time: 6 CK + 4 ms; [CKSEL=0101 SUT=11] 0x3F 0x06 Ext. RC Osc. 0.9 MHz - 3.0 MHz; Start-up time: 18 CK + 0 ms; [CKSEL=0110 SUT=00] 0x3F 0x16 Ext. RC Osc. 0.9 MHz - 3.0 MHz; Start-up time: 18 CK + 4 ms; [CKSEL=0110 SUT=01] 0x3F 0x26 Ext. RC Osc. 0.9 MHz - 3.0 MHz; Start-up time: 18 CK + 64 ms; [CKSEL=0110 SUT=10] 0x3F 0x36 Ext. RC Osc. 0.9 MHz - 3.0 MHz; Start-up time: 6 CK + 4 ms; [CKSEL=0110 SUT=11] 0x3F 0x07 Ext. RC Osc. 3.0 MHz - 8.0 MHz; Start-up time: 18 CK + 0 ms; [CKSEL=0111 SUT=00] 0x3F 0x17 Ext. RC Osc. 3.0 MHz - 8.0 MHz; Start-up time: 18 CK + 4 ms; [CKSEL=0111 SUT=01] 0x3F 0x27 Ext. RC Osc. 3.0 MHz - 8.0 MHz; Start-up time: 18 CK + 64 ms; [CKSEL=0111 SUT=10] 0x3F 0x37 Ext. RC Osc. 3.0 MHz - 8.0 MHz; Start-up time: 6 CK + 4 ms; [CKSEL=0111 SUT=11] 0x3F 0x08 Ext. RC Osc. 8.0 MHz - 12.0 MHz; Start-up time: 18 CK + 0 ms; [CKSEL=1000 SUT=00] 0x3F 0x18 Ext. RC Osc. 8.0 MHz - 12.0 MHz; Start-up time: 18 CK + 4 ms; [CKSEL=1000 SUT=01] 0x3F 0x28 Ext. RC Osc. 8.0 MHz - 12.0 MHz; Start-up time: 18 CK + 64 ms; [CKSEL=1000 SUT=10] 0x3F 0x38 Ext. RC Osc. 8.0 MHz - 12.0 MHz; Start-up time: 6 CK + 4 ms; [CKSEL=1000 SUT=11] 0x3F 0x09 Ext. Low-Freq. Crystal; Start-up time: 1K CK + 4 ms; [CKSEL=1001 SUT=00] 0x3F 0x19 Ext. Low-Freq. Crystal; Start-up time: 1K CK + 64 ms; [CKSEL=1001 SUT=01] 0x3F 0x29 Ext. Low-Freq. Crystal; Start-up time: 32K CK + 64 ms; [CKSEL=1001 SUT=10] 0x3F 0x0A Ext. Crystal/Resonator Low Freq.; Start-up time: 258 CK + 4 ms; [CKSEL=1010 SUT=00] 0x3F 0x1A Ext. Crystal/Resonator Low Freq.; Start-up time: 258 CK + 64 ms; [CKSEL=1010 SUT=01] 0x3F 0x2A Ext. Crystal/Resonator Low Freq.; Start-up time: 1K CK + 0 ms; [CKSEL=1010 SUT=10] 0x3F 0x3A Ext. Crystal/Resonator Low Freq.; Start-up time: 1K CK + 4 ms; [CKSEL=1010 SUT=11] 0x3F 0x0B Ext. Crystal/Resonator Low Freq.; Start-up time: 1K CK + 64 ms; [CKSEL=1011 SUT=00] 0x3F 0x1B Ext. Crystal/Resonator Low Freq.; Start-up time: 16K CK + 0 ms; [CKSEL=1011 SUT=01] 0x3F 0x2B Ext. Crystal/Resonator Low Freq.; Start-up time: 16K CK + 4 ms; [CKSEL=1011 SUT=10] 0x3F 0x3B Ext. Crystal/Resonator Low Freq.; Start-up time: 16K CK + 64 ms; [CKSEL=1011 SUT=11] 0x3F 0x0C Ext. Crystal/Resonator Medium Freq.; Start-up time: 258 CK + 4 ms; [CKSEL=1100 SUT=00] 0x3F 0x1C Ext. Crystal/Resonator Medium Freq.; Start-up time: 258 CK + 64 ms; [CKSEL=1100 SUT=01] 0x3F 0x2C Ext. Crystal/Resonator Medium Freq.; Start-up time: 1K CK + 0 ms; [CKSEL=1100 SUT=10] 0x3F 0x3C Ext. Crystal/Resonator Medium Freq.; Start-up time: 1K CK + 4 ms; [CKSEL=1100 SUT=11] 0x3F 0x0D Ext. Crystal/Resonator Medium Freq.; Start-up time: 1K CK + 64 ms; [CKSEL=1101 SUT=00] 0x3F 0x1D Ext. Crystal/Resonator Medium Freq.; Start-up time: 16K CK + 0 ms; [CKSEL=1101 SUT=01] 0x3F 0x2D Ext. Crystal/Resonator Medium Freq.; Start-up time: 16K CK + 4 ms; [CKSEL=1101 SUT=10] 0x3F 0x3D Ext. Crystal/Resonator Medium Freq.; Start-up time: 16K CK + 64 ms; [CKSEL=1101 SUT=11] 0x3F 0x0E Ext. Crystal/Resonator High Freq.; Start-up time: 258 CK + 4 ms; [CKSEL=1110 SUT=00] 0x3F 0x1E Ext. Crystal/Resonator High Freq.; Start-up time: 258 CK + 64 ms; [CKSEL=1110 SUT=01] 0x3F 0x2E Ext. Crystal/Resonator High Freq.; Start-up time: 1K CK + 0 ms; [CKSEL=1110 SUT=10] 0x3F 0x3E Ext. Crystal/Resonator High Freq.; Start-up time: 1K CK + 4 ms; [CKSEL=1110 SUT=11] 0x3F 0x0F Ext. Crystal/Resonator High Freq.; Start-up time: 1K CK + 64 ms; [CKSEL=1111 SUT=00] 0x3F 0x1F Ext. Crystal/Resonator High Freq.; Start-up time: 16K CK + 0 ms; [CKSEL=1111 SUT=01] 0x3F 0x2F Ext. Crystal/Resonator High Freq.; Start-up time: 16K CK + 4 ms; [CKSEL=1111 SUT=10] 0x3F 0x3F Ext. Crystal/Resonator High Freq.; Start-up time: 16K CK + 64 ms; [CKSEL=1111 SUT=11] 8 RSTDISBL Disable reset 1 WTDON Enable watchdog 0 SPIEN Enable Serial programming and Data Downloading 0 CKOPT Oscillator Options 1 EESAVE EEPROM memory is preserved through chip erase 1 BOOTSZ1 Select Boot Size 0 BOOTSZ0 Select Boot Size 0 BOOTRST Select Reset Vector 1 10 0x80 0x00 Reset Disabled (Enable PC6 as i/o pin); [RSTDISBL=0] 0x40 0x00 Watch-dog Timer always on; [WDTON=0] 0x20 0x00 Serial program downloading (SPI) enabled; [SPIEN=0] 0x08 0x00 Preserve EEPROM memory through the Chip Erase cycle; [EESAVE=0] 0x06 0x06 Boot Flash section size=128 words Boot start address=$0F80; [BOOTSZ=11] 0x06 0x04 Boot Flash section size=256 words Boot start address=$0F00; [BOOTSZ=10] 0x06 0x02 Boot Flash section size=512 words Boot start address=$0E00; [BOOTSZ=01] 0x06 0x00 Boot Flash section size=1024 words Boot start address=$0C00; [BOOTSZ=00] ; default value 0x01 0x00 Boot Reset vector Enabled (default address=$0000); [BOOTRST=0] 0x10 0x00 CKOPT fuse (operation dependent of CKSEL fuses); [CKOPT=0] 0xff,0xdf 0xff,0xdf 1,0x20,0x20,WARNING! These fuse settings will disable the ISP interface! 1,0x80,0x00,WARNING! Disabling external reset will make the ISP interface inaccessible! 1,0x20,0x20,WARNING! These fuse settings will disable the ISP interface! 1,0x80,0x00,WARNING! Disabling external reset will make the ISP interface inaccessible! 0x00,1.0 MHz 0x01,2.0 MHz 0x02,4.0 MHz 0x03,8.0 MHz 64 4 [ANALOG_COMPARATOR:SPI:EXTERNAL_INTERRUPT:TIMER_COUNTER_0:TIMER_COUNTER_1:TIMER_COUNTER_2:USART:TWI:WATCHDOG:PORTB:PORTC:PORTD:EEPROM:CPU:AD_CONVERTER] [SFIOR:ACSR] io_analo.bmp AlgComp_01 SFIOR Special Function IO Register 0x30 0x50 io_flag.bmp Y ACME Analog Comparator Multiplexer Enable When this bit is written logic one and the ADC is switched off (ADEN in ADCSR is zero), the ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed description of this bit, see “Analog Comparator Multiplexed Input” on page 186. RW 0 ACSR Analog Comparator Control And Status Register 0x08 0x28 io_analo.bmp Y ACD Analog Comparator Disable When this bit is written logic one, the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed. RW 0 ACBG Analog Comparator Bandgap Select When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. See “Internal Voltage Reference” on page 42. RW 0 ACO Analog Compare Output The output of the analog comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1-2 clock cycles. R NA ACI Analog Comparator Interrupt Flag This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hard-ware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag. RW 0 ACIE Analog Comparator Interrupt Enable When the ACIE bit is written logic one and the I-bit in the Status Register is set, the analog comparator interrupt is acti-vated. When written logic zero, the interrupt is disabled. RW 0 ACIC Analog Comparator Input Capture Enable When written logic one, this bit enables the Input Capture function in Timer/Counter1 to be triggered by the analog comparator. The comparator output is in this case directly connected to the Input Capture front-end logic, making the comparator utilize the noise canceler and edge select features of the Timer/Counter1 Input Capture interrupt. When written logic zero, no connection between the analog comparator and the Input Capture function exists. To make the comparator trigger the Timer/Counter1 Input Capture interrupt, the TICIE1 bit in the Timer Interrupt Mask Register (TIMSK) must be set RW 0 ACIS1 Analog Comparator Interrupt Mode Select bit 1 These bits determine which comparator events that trigger the Analog Comparator interrupt. RW 0 ACIS0 Analog Comparator Interrupt Mode Select bit 0 These bits determine which comparator events that trigger the Analog Comparator interrupt. RW 0 [SPDR:SPSR:SPCR] io_com.bmp SPI_01 The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the device and peripheral devices or between several AVR devices. The SPI includes the following features: • Full-duplex, 3-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Seven Programmable Bit Rates • End of Transmission Interrupt Flag • Write Collision Flag Protection • Wake-up from Idle Mode • Double Speed (CK/2) Master SPI Mode SPDR SPI Data Register The SPI Data Register is a read/write register used for data transfer between the register file and the SPI Shift register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read. 0x0F 0x2F io_com.bmp N SPDR7 SPI Data Register bit 7 RW X SPDR6 SPI Data Register bit 6 RW X SPDR5 SPI Data Register bit 5 RW X SPDR4 SPI Data Register bit 4 RW X SPDR3 SPI Data Register bit 3 RW X SPDR2 SPI Data Register bit 2 RW X SPDR1 SPI Data Register bit 1 R 0 SPDR0 SPI Data Register bit 0 R 0 SPSR SPI Status Register 0x0E 0x2E io_flag.bmp Y SPIF SPI Interrupt Flag When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is generated if SPIE in SPCR is set (one) and global interrupts are enabled. If SS is an input and is driven low when the SPI is in master mode, this will also set the SPIF flag. SPIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the SPI status register when SPIF is set (one), then accessing the SPI Data Register (SPDR). R 0 WCOL Write Collision Flag The WCOL bit is set if the SPI data register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Register when WCOL is set (one), and then accessing the SPI Data Register. R 0 SPI2X Double SPI Speed Bit When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in master mode (see Table 71). This means that the minimum SCK period will be 2 CPU clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at f ck / 4 or lower. The SPI interface on the ATmega104 is also used for program memory and EEPROM downloading or uploading. See page 253 for serial programming and verification. RW 0 SPCR SPI Control Register 0x0D 0x2D io_flag.bmp Y SPIE SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR register is set and the global interrupts are enabled. RW 0 SPE SPI Enable When the SPE bit is set (one), the SPI is enabled. This bit must be set to enable any SPI operations. RW 0 DORD Data Order When the DORD bit is set (one), the LSB of the data word is transmitted first. When the DORD bit is cleared (zero), the MSB of the data word is transmitted first. RW 0 MSTR Master/Slave Select This bit selects Master SPI mode when set (one), and Slave SPI mode when cleared (zero). If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI master mode. RW 0 CPOL Clock polarity When this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is low when idle. Refer to Figure 36 and Figure 37 for additional information. RW 0 CPHA Clock Phase Refer to Figure 36 or Figure 37 for the functionality of this bit. RW 0 SPR1 SPI Clock Rate Select 1 RW 0 SPR0 SPI Clock Rate Select 0 RW 0 [GICR:GIFR:MCUCR] io_ext.bmp GICR GIMSK General Interrupt Control Register 0x3B 0x5B io_flag.bmp Y INT1 External Interrupt Request 1 Enable When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT1 pin or level sensed. Activity on the pin will cause an interrupt request even if INT1 is configured as an output. The corresponding interrupt of External Interrupt Request 1 is executed from program memory address $002. See also “External Interrupts”. RW 0 INT0 External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from program memory address $001. See also “External Interrupts.” • Bits 5..0 - Res: Reserved bit RW 0 IVSEL Interrupt Vector Select When the IVSELbit is cleared (zero),the interrupt vectors are placed at the start of the Flash memory.When this bit is set (one),the interrupt vectors are moved to the beginning of the Boot Loader section of the flash.The actual address to the start of the boot flash section is determined by the BOOTSZ fuses.Refer to the section “Boot Loader Support Read While Write self programming ”on page 201 for details.To avoid unintentional changes of interrupt vector tables,a special write procedure must be followed to change the IVSELbit: 1.Set the Interrupt Vector Change Enable (IVCE)bit. 2.Within four cycles,write the desired value to IVSELwhile writing a zero to IVCE. Interrupts will automatically be disabled while this sequence is executed.Interrupts are disabled in the cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL.If IVSEL is not written,interrupts remain disabled for four cycles.The I-bit in the Status Register is unaffected by the automatic disabling. Note If Boot Lock bits BLB02 or BLB12 are set,changing the interrupt vector table will change from which part of the program memory interrupts are allowed.Refer to the section “Boot Loader Support Read While Write self-programmin RW 0 IVCE Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSELbit.IVCE is cleared by hardware four cycles after it is written or when IVSEL is written.Setting the IVCE bit will disable interrupts,as explained in the IVSELdescription above. RW 0 GIFR General Interrupt Flag Register 0x3A 0x5A io_flag.bmp Y INTF1 External Interrupt Flag 1 When an event on the INT1 pin triggers an interrupt request,INTF1 becomes set (one).If the I bit in SREG and the INT1 bit in GICR are set (one),the MCU will jump to the corresponding interrupt vector.The flag is cleared when the interrupt routine is executed.Alternatively,the flag can be cleared by writing a logical one to it.This flag is always cleared when INT1 is configured as a level interrupt. RW 0 INTF0 External Interrupt Flag 0 When an event on the INT0 pin triggers an interrupt request,INTF0 becomes set (one).If the I bit in SREG and the INT0 bit in GICR are set (one),the MCU will jump to the corresponding interrupt vector.The flag is cleared when the interrupt rou tine is executed.Alternatively,the flag can be cleared by writing a logical one to it.This flag is always cleared when INT0 is configured as a level interrupt. RW 0 MCUCR MCU Control Register 0x35 0x55 io_flag.bmp Y ISC11 Interrupt Sense Control 1 Bit 1 The External Interrupt 1 is activated by the external pin INT1 if the SREG I bit and the corresponding interrupt mask in the GICR are set.The level and edges on the external INT1 pin that activate the interrupt are defined below.The value on the INT1 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the low level must be held until the completion of the currently executing instruction to generate an interrupt. (ISC11:ISC10) Description: (0:0) The low level of INT1 generates an interrupt request. (0:1) Any logical change on INT1 generates an interrupt request. (1:0) The falling edge of INT1 generates an interrupt request. (1:1) The rising edge of INT1 generates an interrupt reque RW 0 ISC10 Interrupt Sense Control 1 Bit 0 The External Interrupt 1 is activated by the external pin INT1 if the SREG I bit and the corresponding interrupt mask in the GICR are set.The level and edges on the external INT1 pin that activate the interrupt are defined below.The value on the INT1 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the low level must be held until the completion of the currently executing instruction to generate an interrupt. (ISC11:ISC10) Description: (0:0) The low level of INT1 generates an interrupt request. (0:1) Any logical change on INT1 generates an interrupt request. (1:0) The falling edge of INT1 generates an interrupt request. (1:1) The rising edge of INT1 generates an interrupt reque RW 0 ISC01 Interrupt Sense Control 0 Bit 1 The External Interrupt 0 is activated by the external pin INT0 if the SREG I flag and the corresponding interrupt mask are set.The level and edges on the external INT0 pin that activate the interrupt are defined below. The value on the INT0 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the low level must be held until the completion of the currently executing instruction to generate an interrupt. (ISC01:ISC00) Description: (0:0) The low level of INT0 generates an interrupt request. (0:1) Any logical change on INT0 generates an interrupt request. (1:0) The falling edge of INT0 generates an interrupt request. (1:1) The rising edge of INT0 generates an interrupt reques RW 0 ISC00 Interrupt Sense Control 0 Bit 0 The External Interrupt 0 is activated by the external pin INT0 if the SREG I flag and the corresponding interrupt mask are set.The level and edges on the external INT0 pin that activate the interrupt are defined below. The value on the INT0 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the low level must be held until the completion of the currently executing instruction to generate an interrupt. (ISC01:ISC00) Description: (0:0) The low level of INT0 generates an interrupt request. (0:1) Any logical change on INT0 generates an interrupt request. (1:0) The falling edge of INT0 generates an interrupt request. (1:1) The rising edge of INT0 generates an interrupt reques RW 0 [TIMSK:TIFR:TCCR0:TCNT0] io_timer.bmp t81 The 8-bit Timer/Counter0 can select clock source from CK, prescaled CK, or an external pin. In addition it can be stopped as described in “Timer/Counter0 Control Register - TCCR0” on page 35. The overflow status flag is found in “The Timer/Counter Interrupt Flag Register - TIFR” on page 29. Control signals are found in the Timer/Counter0 Control Register - TCCR0. The interrupt enable/disable settings for Timer/Counter0 are found in “The Timer/Counter Interrupt Mask Regis-ter - TIMSK” on page 28. When Timer/Counter0 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. The 8-bit Timer/Counter0 features both a high resolution and a high accuracy usage with the lower prescaling opportuni-ties. Similarly, the high prescaling opportuni ties make the Timer/Counter0 useful for lower speed functions or exact timing functions with infrequent actions TIMSK Timer/Counter Interrupt Mask Register 0x39 0x59 io_flag.bmp Y TOIE0 Timer/Counter0 Overflow Interrupt Enable When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register - TIFR. RW 0 TIFR Timer/Counter Interrupt Flag register 0x38 0x58 io_flag.bmp Y TOV0 Timer/Counter0 Overflow Flag The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, and TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. RW 0 TCCR0 Timer/Counter0 Control Register 0x33 0x53 io_flag.bmp Y CS02 Clock Select0 bit 2 RW 0 CS01 Clock Select0 bit 1 RW 0 CS00 Clock Select0 bit 0 RW 0 TCNT0 Timer Counter 0 The Timer/Counter0 is realized as an up-counter with read and write access. If the Timer/Counter0 is written and a clock source is present, the Timer/Counter0 continues counting in the clock cycle following the write operation. 0x32 0x52 io_timer.bmp N TCNT07 Timer Counter 0 bit 7 RW 0 TCNT06 Timer Counter 0 bit 6 RW 0 TCNT05 Timer Counter 0 bit 5 RW 0 TCNT04 Timer Counter 0 bit 4 RW 0 TCNT03 Timer Counter 0 bit 3 RW 0 TCNT02 Timer Counter 0 bit 2 RW 0 TCNT01 Timer Counter 0 bit 1 RW 0 TCNT00 Timer Counter 0 bit 0 RW 0 [TIMSK:TIFR:TCCR1A:TCCR1B:TCNT1H:TCNT1L:OCR1AH:OCR1AL:OCR1BH:OCR1BL:ICR1H:ICR1L] [TCNT1H:TCNT1L];[OCR1AH:OCR1AL];[OCR1BH:OCR1BL];[ICR1H:ICR1L] io_timer.bmp t16pwm1_05.xml TIMSK Timer/Counter Interrupt Mask Register 0x39 0x59 io_flag.bmp Y TICIE1 Timer/Counter1 Input Capture Interrupt Enable When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on pin 31, ICP, i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR. RW 0 OCIE1A Timer/Counter1 Output CompareA Match Interrupt Enable When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a CompareA match in Timer/Counter1 occurs, i.e., when the OCF1A bit is set in the Timer/Counter Interrupt Flag Register - TIFR. RW 0 OCIE1B Timer/Counter1 Output CompareB Match Interrupt Enable When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter1 occurs, i.e., when the OCF1B bit is set in the Timer/Counter Interrupt Flag Register - TIFR. R 0 TOIE1 Timer/Counter1 Overflow Interrupt Enable When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $006) is executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR. RW 0 TIFR Timer/Counter Interrupt Flag register 0x38 0x58 io_flag.bmp Y ICF1 Input Capture Flag 1 The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to the input capture register - ICR1. ICF1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF1 is cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable), and ICF1 are set (one), the Timer/Counter1 Capture Interrupt is executed. RW 0 OCF1A Output Compare Flag 1A The OCF1A bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare match InterruptA Enable), and the OCF1A are set (one), the Timer/Counter1 Compare A match Interrupt is executed. RW 0 OCF1B Output Compare Flag 1B The OCF1B bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1B - Output Compare Register 1B. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1B (Timer/Counter1 Compare match InterruptB Enable), and the OCF1B are set (one), the Timer/Counter1 Compare B match Interrupt is executed. RW 0 TOV1 Timer/Counter1 Overflow Flag The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the cor-responding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter1 changes counting direction at $0000. RW 0 TCCR1A Timer/Counter1 Control Register A 0x2F 0x4F io_flag.bmp Y COM1A1 Compare Output Mode 1A, bit 1 The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA. This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10. RW 0 COM1A0 Comparet Ouput Mode 1A, bit 0 The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA. This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10. RW 0 COM1B1 Compare Output Mode 1B, bit 1 The COM1B1 and COM1B0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin. RW 0 COM1B0 Compare Output Mode 1B, bit 0 The COM1B1 and COM1B0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin. RW 0 FOC1A Force Output Compare 1A Writing a logical one to this bit, forces a change in the compare match output pin PD5 according to the values already set in COM1A1 and COM1A0.If the COM1A1 and COM1A0 bits are written in the same cycle as FOC1A,the new settings will not take effect until next compare match or forced compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM1A1 and COM1A0 happens as if a Compare Match had occurred, but no interrupt is generated and it will not clear the timer even if CTC1 in TCCR1B is set. The corresponding I/O pin must be set as an output pin for the FOC1A bit to have effect on the pin. The FOC1A bit will always be read as zero. The setting of the FOC1A bit has no effect in PWM mod RW 0 FOC1B Force Output Compare 1B Writing a logical one to this bit, forces a change in the compare match output pin PD4 according to the values already set in COM1B1 and COM1B0.If the COM1B1 and COM1B0 bits are written in the same cycle as FOC1B,the new settings will not take effect until next compare match or forced compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM1B1 and COM1B0 happens as if a Compare Match had occurred, but no interrupt is generated. The corresponding I/O pin must be set as an output pin for the FOC1B bit to have effect on the pin. The FOC1B bit will always be read as zero. The setting of the FOC1B bit has no effect in PWM mode RW 0 WGM11 PWM11 Waveform Generation Mode Combined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table. RW 0 WGM10 PWM10 Waveform Generation Mode Combined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table. RW 0 TCCR1B Timer/Counter1 Control Register B 0x2E 0x4E io_flag.bmp Y ICNC1 Input Capture 1 Noise Canceler When the ICNC1 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the ICP - input capture pin - as specified. When the ICNC1 bit is set (one), four successive samples are measures on the ICP - input capture pin, and all samples must be high/low according to the input capture trigger specification in the ICES1 bit. The actual sampling frequency is XTAL clock frequency. RW 0 ICES1 Input Capture 1 Edge Select While the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the falling edge of the input capture pin - ICP. While the ICES1 bit is set (one), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the rising edge of the input capture pin - ICP. RW 0 WGM13 CTC11 Waveform Generation Mode Combined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table. RW 0 WGM12 CTC10 CTC1 Waveform Generation Mode Combined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table. RW 0 CS12 Prescaler source of Timer/Counter 1 Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge. RW 0 CS11 Prescaler source of Timer/Counter 1 Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge. RW 0 CS10 Prescaler source of Timer/Counter 1 Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge. RW 0 TCNT1H Timer/Counter1 High Byte This 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR1A, OCR1B and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt rou 0x2D 0x4D io_timer.bmp N TCNT1H7 Timer/Counter1 High Byte bit 7 RW 0 TCNT1H6 Timer/Counter1 High Byte bit 6 RW 0 TCNT1H5 Timer/Counter1 High Byte bit 5 RW 0 TCNT1H4 Timer/Counter1 High Byte bit 4 RW 0 TCNT1H3 Timer/Counter1 High Byte bit 3 RW 0 TCNT1H2 Timer/Counter1 High Byte bit 2 RW 0 TCNT1H1 Timer/Counter1 High Byte bit 1 RW 0 TCNT1H0 Timer/Counter1 High Byte bit 0 RW 0 TCNT1L Timer/Counter1 Low Byte This 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR1A, OCR1B and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interru 0x2C 0x4C io_timer.bmp N TCNT1L7 Timer/Counter1 Low Byte bit 7 RW 0 TCNT1L6 Timer/Counter1 Low Byte bit 6 RW 0 TCNT1L5 Timer/Counter1 Low Byte bit 5 RW 0 TCNT1L4 Timer/Counter1 Low Byte bit 4 RW 0 TCNT1L3 Timer/Counter1 Low Byte bit 3 RW 0 TCNT1L2 Timer/Counter1 Low Byte bit 2 RW 0 TCNT1L1 Timer/Counter1 Low Byte bit 1 RW 0 TCNT1L0 Timer/Counter1 Low Byte bit 0 RW 0 OCR1AH Timer/Counter1 Outbut Compare Register High Byte The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interru 0x2B 0x4B io_timer.bmp N OCR1AH7 Timer/Counter1 Outbut Compare Register High Byte bit 7 RW 0 OCR1AH6 Timer/Counter1 Outbut Compare Register High Byte bit 6 RW 0 OCR1AH5 Timer/Counter1 Outbut Compare Register High Byte bit 5 RW 0 OCR1AH4 Timer/Counter1 Outbut Compare Register High Byte bit 4 RW 0 OCR1AH3 Timer/Counter1 Outbut Compare Register High Byte bit 3 RW 0 OCR1AH2 Timer/Counter1 Outbut Compare Register High Byte bit 2 RW 0 OCR1AH1 Timer/Counter1 Outbut Compare Register High Byte bit 1 RW 0 OCR1AH0 Timer/Counter1 Outbut Compare Register High Byte bit 0 RW 0 OCR1AL Timer/Counter1 Outbut Compare Register Low Byte The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interru 0x2A 0x4A io_timer.bmp N OCR1AL7 Timer/Counter1 Outbut Compare Register Low Byte Bit 7 RW 0 OCR1AL6 Timer/Counter1 Outbut Compare Register Low Byte Bit 6 RW 0 OCR1AL5 Timer/Counter1 Outbut Compare Register Low Byte Bit 5 RW 0 OCR1AL4 Timer/Counter1 Outbut Compare Register Low Byte Bit 4 RW 0 OCR1AL3 Timer/Counter1 Outbut Compare Register Low Byte Bit 3 RW 0 OCR1AL2 Timer/Counter1 Outbut Compare Register Low Byte Bit 2 RW 0 OCR1AL1 Timer/Counter1 Outbut Compare Register Low Byte Bit 1 RW 0 OCR1AL0 Timer/Counter1 Outbut Compare Register Low Byte Bit 0 RW 0 OCR1BH Timer/Counter1 Output Compare Register High Byte The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt ro 0x29 0x49 io_timer.bmp N OCR1BH7 Timer/Counter1 Output Compare Register High Byte bit 7 RW 0 OCR1BH6 Timer/Counter1 Output Compare Register High Byte bit 6 RW 0 OCR1BH5 Timer/Counter1 Output Compare Register High Byte bit 5 RW 0 OCR1BH4 Timer/Counter1 Output Compare Register High Byte bit 4 RW 0 OCR1BH3 Timer/Counter1 Output Compare Register High Byte bit 3 RW 0 OCR1BH2 Timer/Counter1 Output Compare Register High Byte bit 2 RW 0 OCR1BH1 Timer/Counter1 Output Compare Register High Byte bit 1 RW 0 OCR1BH0 Timer/Counter1 Output Compare Register High Byte bit 0 RW 0 OCR1BL Timer/Counter1 Output Compare Register Low Byte The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt rout 0x28 0x48 io_timer.bmp N OCR1BL7 Timer/Counter1 Output Compare Register Low Byte bit 7 R 0 OCR1BL6 Timer/Counter1 Output Compare Register Low Byte bit 6 RW 0 OCR1BL5 Timer/Counter1 Output Compare Register Low Byte bit 5 RW 0 OCR1BL4 Timer/Counter1 Output Compare Register Low Byte bit 4 RW 0 OCR1BL3 Timer/Counter1 Output Compare Register Low Byte bit 3 RW 0 OCR1BL2 Timer/Counter1 Output Compare Register Low Byte bit 2 RW 0 OCR1BL1 Timer/Counter1 Output Compare Register Low Byte bit 1 RW 0 OCR1BL0 Timer/Counter1 Output Compare Register Low Byte bit 0 RW 0 ICR1H Timer/Counter1 Input Capture Register High Byte The input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES1) of the signal at the input capture pin -ICP - is detected, the current value of the Timer/Counter1 is transferred to the Input Capture Register - ICR1. At the same time, the input capture flag - ICF1 - is set (one). Since the Input Capture Register - ICR1 - is a 16-bit register, a temporary register TEMP is used when ICR1 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR1L, the data is sent to the CPU and the data of the high byte ICR1H is placed in the TEMP register. When the CPU reads the data in the high byte ICR1H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR1L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT1, OCR1A and OCR1B. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt 0x27 0x47 io_timer.bmp N ICR1H7 Timer/Counter1 Input Capture Register High Byte bit 7 RW 0 ICR1H6 Timer/Counter1 Input Capture Register High Byte bit 6 R 0 ICR1H5 Timer/Counter1 Input Capture Register High Byte bit 5 R 0 ICR1H4 Timer/Counter1 Input Capture Register High Byte bit 4 R 0 ICR1H3 Timer/Counter1 Input Capture Register High Byte bit 3 R 0 ICR1H2 Timer/Counter1 Input Capture Register High Byte bit 2 R 0 ICR1H1 Timer/Counter1 Input Capture Register High Byte bit 1 R 0 ICR1H0 Timer/Counter1 Input Capture Register High Byte bit 0 R 0 ICR1L Timer/Counter1 Input Capture Register Low Byte The input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES1) of the signal at the input capture pin -ICP - is detected, the current value of the Timer/Counter1 is transferred to the Input Capture Register - ICR1. At the same time, the input capture flag - ICF1 - is set (one). Since the Input Capture Register - ICR1 - is a 16-bit register, a temporary register TEMP is used when ICR1 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR1L, the data is sent to the CPU and the data of the high byte ICR1H is placed in the TEMP register. When the CPU reads the data in the high byte ICR1H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR1L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT1, OCR1A and OCR1B. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within inter 0x26 0x46 io_timer.bmp N ICR1L7 Timer/Counter1 Input Capture Register Low Byte bit 7 R 0 ICR1L6 Timer/Counter1 Input Capture Register Low Byte bit 6 R 0 ICR1L5 Timer/Counter1 Input Capture Register Low Byte bit 5 R 0 ICR1L4 Timer/Counter1 Input Capture Register Low Byte bit 4 R 0 ICR1L3 Timer/Counter1 Input Capture Register Low Byte bit 3 R 0 ICR1L2 Timer/Counter1 Input Capture Register Low Byte bit 2 R 0 ICR1L1 Timer/Counter1 Input Capture Register Low Byte bit 1 R 0 ICR1L0 Timer/Counter1 Input Capture Register Low Byte bit 0 R 0 [TIMSK:TIFR:TCCR2:TCNT2:OCR2:ASSR:SFIOR] io_timer.bmp At8pwm2_02 The 8-bit Timer/Counter2 can select clock source from CK, prescaled CK, or external crystal input TOSC1. It can also be stopped as described in the section “Timer/Counter2 Control Register - TCCR2”. The status flags (overflow and compare match) are found in the Timer/Counter Interrupt Flag Register - TIFR. Control signals are found in the Timer/Counter Control Register TCCR2. The interrupt enable/disable settings are found in “The Timer/Counter Interrupt Mask Register - TIMSK”. When Timer/Counter2 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. This module features a high resolution and a high accuracy usage with the lower prescaling opportunities. Similarly, the high prescaling opportunities make this unit useful for lower speed functions or exact timing functions with infrequent actions. Timer/Counter2 can also be used as an 8-bit Pulse Width Modulator. In this mode, Timer/Counter2 and the output compare register serve as a glitch-free, stand-alone PWM with centered puls TIMSK Timer/Counter Interrupt Mask register 0x39 0x59 io_flag.bmp Y OCIE2 Timer/Counter2 Output Compare Match Interrupt Enable When the OCIE2 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match interrupt is enabled. The corresponding interrupt (at vector $006) is executed if a compare match in Timer/Counter2 occurs, i.e. when the OCF2 bit is set in the Timer/Counter Interrupt Flag Register - TIFR. RW 0 TOIE2 Timer/Counter2 Overflow Interrupt Enable When the TOIE2 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow interrupt is RW 0 TIFR Timer/Counter Interrupt Flag Register 0x38 0x58 io_flag.bmp Y OCF2 Output Compare Flag 2 The OCF2 bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2 - Output Compare Register2. OCF2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF2 is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE2 (Timer/Counter2 Compare match Interrupt Enable), and the OCF2 are set (one), the Timer/Counter2 Compare match Interrupt is executed. RW 0 TOV2 Timer/Counter2 Overflow Flag The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, and TOIE2 (Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In up/down PWM mode, this bit is set when Timer/Counter2 changes counting direction at $00. RW 0 TCCR2 Timer/Counter2 Control Register 0x25 0x45 io_flag.bmp Y FOC2 Force Output Compare Writing a logical one to this bit, forces a change in the compare match output pin PD7 (OC2) according to the values already set in COM21 and COM20. If the COM21 and COM20 bits are written in the same cycle as FOC2, the new settings will not take effect until next compare match or forced output compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM21 and COM20 happens as if a Compare Match had occurred, but no interrupt is generated, and the Timer/Counter will not be cleared even if CTC2 is set. The corresponding I/O pin must be set as an output pin for the FOC2 bit to have effect on the pin. The FOC2 bit will always be read as zero. Setting the FOC2 bit has no effect in PWM mode RW 0 WGM20 PWM2 Waveform Genration Mode These bits control the counting sequence of the counter,the source for hte maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter), Clear Timer on Compare match (CTC)mode,and two types of Pulse Width Modulation (PWM)modes. Please refer to the manual for more information. RW 0 COM21 Compare Output Mode bit 1 The COM21 and COM20 control bits determine any output pin action following a compare match in Timer/Counter2. Output pin actions affect pin PD7(OC2). This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. (COM21:COM20) description: (0:0) = Timer/Counter disconnected from output pin OC2. (0:1) = Toggle the OC2 output line. (1:0) = Clear the OC2 output line (to zero). (1:1) = Set the OC2 output line (to one). Note: In PWM mode, these bits have a different function RW 0 COM20 Compare Output Mode bit 0 The COM21 and COM20 control bits determine any output pin action following a compare match in Timer/Counter2. Output pin actions affect pin PD7(OC2). This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. (COM21:COM20) description: (0:0) = Timer/Counter disconnected from output pin OC2. (0:1) = Toggle the OC2 output line. (1:0) = Clear the OC2 output line (to zero). (1:1) = Set the OC2 output line (to one). Note: In PWM mode, these bits have a different function RW 0 WGM21 CTC2 Waveform Generation Mode These bits control the counting sequence of the counter,the source for hte maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter), Clear Timer on Compare match (CTC)mode,and two types of Pulse Width Modulation (PWM)modes. Please refer to the manual for more information. RW 0 CS22 Clock Select bit 2 The Clock Select bits 2,1, and 0 define the prescaling source of Timer/Counter2. (CS22:CS21:CS20) Description. (0:0:0) Timer/Counter2 is stopped. (0:0:1) PCK2. (0:1:0) PCK2/8. (0:1:1) PCK2/32. (1:0:0) PCK2/64. (1:0:1) PCK2/128. (1:1:0) PCK2/256. (1:1:1) PCK2/1024. The Stop condition provides a Timer Enable/Disable function. The prescaled modes are scaled directly from the PCK2 clock. RW 0 CS21 Clock Select bit 1 The Clock Select bits 2,1, and 0 define the prescaling source of Timer/Counter2. (CS22:CS21:CS20) Description. (0:0:0) Timer/Counter2 is stopped. (0:0:1) PCK2. (0:1:0) PCK2/8. (0:1:1) PCK2/32. (1:0:0) PCK2/64. (1:0:1) PCK2/128. (1:1:0) PCK2/256. (1:1:1) PCK2/1024. The Stop condition provides a Timer Enable/Disable function. The prescaled modes are scaled directly from the PCK2 clock. RW 0 CS20 Clock Select bit 0 The Clock Select bits 2,1, and 0 define the prescaling source of Timer/Counter2. (CS22:CS21:CS20) Description. (0:0:0) Timer/Counter2 is stopped. (0:0:1) PCK2. (0:1:0) PCK2/8. (0:1:1) PCK2/32. (1:0:0) PCK2/64. (1:0:1) PCK2/128. (1:1:0) PCK2/256. (1:1:1) PCK2/1024. The Stop condition provides a Timer Enable/Disable function. The prescaled modes are scaled directly from the PCK2 clock. RW 0 TCNT2 Timer/Counter2 This 8-bit register contains the value of Timer/Counter2. Timer/Counters2 is implemented as an up or up/down (in PWM mode) counter with read and write access. If the Timer/Counter2iswritten to and a clocksourceisselected,it continues counting in the timer clock cycle following the write operation. 0x24 0x44 io_timer.bmp N TCNT2-7 Timer/Counter 2 bit 7 RW 0 TCNT2-6 Timer/Counter 2 bit 6 RW 0 TCNT2-5 Timer/Counter 2 bit 5 RW 0 TCNT2-4 Timer/Counter 2 bit 4 RW 0 TCNT2-3 Timer/Counter 2 bit 3 RW 0 TCNT2-2 Timer/Counter 2 bit 2 RW 0 TCNT2-1 Timer/Counter 2 bit 1 RW 0 TCNT2-0 Timer/Counter 2 bit 0 RW 0 OCR2 Timer/Counter2 Output Compare Register The output compare register is an 8-bit read/write register. The Timer/Counter Output Compare Register contains the data to be continuously compared with Timer/Counter2. Actions on compare matches are specified in TCCR2. A compare match does only occur if Timer/Counter2 counts to the OCR2 value. A software write that sets TCNT2 and OCR2 to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Timer/Counter2 in PWM Mode When PWM mode is selected, the Timer/Counter2 either wraps (overflows) when it reaches $FF or it acts as an up/down counter. If the up/down mode is selected, the Timer/Counter2 and the Output Compare Register - OCR2 form an 8-bit, free-running, glitch-free, and phase correct PWM with outputs on the PD7(OC2) pin. If the overflow mode is selected, the Timer/Counter2 and the Output Compare Register - OCR2 form an 8-bit, free-running, and glitch-free PWM, operating with twice the speed of the up/down counting mode. PWM Modes (Up/Down and Overflow). The two different PWM modes are selected by the CTC2 bit in the Timer/Counter Control Register - TCCR2. If CTC2 is cleared and PWM mode is selected, the Timer/Counter acts as an up/down counter, counting up from $00 to $FF, where it turns and counts down again to zero before the cycle is repeated. When the counter value matches the con-tents of the Output Compare Register, the PD7(OC2) pin is set or cleared according to the settings of the COM21/COM20 bits in the Timer/Counter Control Register TCCR2. If CTC2 is set and PWM mode is selected, the Timer/Counters will wrap and start counting from $00 after reaching $FF. The PD7(OC2) pin will be set or cleared according to the settings of COM21/COM20 on a Timer/Counter overflow or when the counter value matches the contents of the Output Compare Register. Note that in PWM mode, the value to be written to the Output Compare Register is first transferred to a temporary location, and then latched into OCR2 when the Timer/Counter reaches $FF. This prevents the occurrence of odd-length PWM pulses (glitches) in the event of an unsynchronized OCR2 write. (CTC2:COM21:COM20) Effect on Compare Pin Frequency: (0:0:0) = Not connected. (0:0:1) = Not connected. (0:1:0) = Cleared on compare match, up-counting. Set on compare match, down-counting (non-inverted PWM). f TCK0/2 /510. (0:1:1) = Cleared on compare match, down-counting. Set on compare match, up-counting (inverted PWM). f TCK0/2 /510. (1:0:0) = Not connected. (1:0:1) = Not connected. (1:1:0) = Cleared on compare match, set on overflow. f TCK0/2 /256. (1:1:1) = Set on compare match, cleared on overflow. f TCK0/2 / 0x23 0x43 io_timer.bmp N OCR2-7 Timer/Counter2 Output Compare Register Bit 7 RW 0 OCR2-6 Timer/Counter2 Output Compare Register Bit 6 RW 0 OCR2-5 Timer/Counter2 Output Compare Register Bit 5 RW 0 OCR2-4 Timer/Counter2 Output Compare Register Bit 4 RW 0 OCR2-3 Timer/Counter2 Output Compare Register Bit 3 RW 0 OCR2-2 Timer/Counter2 Output Compare Register Bit 2 RW 0 OCR2-1 Timer/Counter2 Output Compare Register Bit 1 RW 0 OCR2-0 Timer/Counter2 Output Compare Register Bit 0 RW 0 ASSR Asynchronous Status Register 0x22 0x42 io_flag.bmp Y AS2 Asynchronous Timer/counter2 When AS2 is cleared (zero), Timer/Counter2 is clocked from the internal system clock, CK. When AS2 is set (one), Timer/Counter2 is clocked from the PC6(TOSC1) pin. Pins PC6 and PC7 are connected to a crystal oscillator and cannot be used as general I/O pins. When the value of this bit is changed, the contents of TCNT2, OCR2, and TCCR2 might be corrupted. RW 0 TCN2UB Timer/Counter2 Update Busy When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set (one). When TCNT2 has been updated from the temporary storage register, this bit is cleared (zero) by hardware. A logical zero in this bit indicates that TCNT2 is ready to be updated with a new value. R 0 OCR2UB Output Compare Register2 Update Busy When Timer/Counter2 operates asynchronously and OCR2 is written, this bit becomes set (one). When OCR2 has been updated from the temporary storage register, this bit is cleared (zero) by hardware. A logical zero in this bit indicates that OCR2 is ready to be updated with a new value. R 0 TCR2UB Timer/counter Control Register2 Update Busy When Timer/Counter2 operates asynchronously and TCCR2 is written, this bit becomes set (one). When TCCR2 has been updated from the temporary storage register, this bit is cleared (zero) by hardware. A logical zero in this bit indicates that TCCR2 is ready to be updated with a new value. If a write is performed to any of the three Timer/Counter2 registers while its update busy flag is set (one), the updated value might get corrupted and cause an unintentional interrupt to occur. The mechanisms for reading TCNT2, OCR2, and TCCR2 are different. When reading TCNT2, the actual timer value is read. When reading OCR2 or TCCR2, the value in the temporary storage register is rea R 0 SFIOR Special Function IO Register 0x30 0x50 io_cpu.bmp Y PSR2 Prescaler Reset Timer/Counter2 When this bit is set (one)the Timer/Counter2 prescaler will be reset.The bit will be cleared by hardware after the operation is performed.Writing a zero to this bit will have no effect.This bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock.If this bit is written when Timer/Counter2 is operating in asynchronous mode,the bit will remain one until the prescaler has been reset. R 0 [UDR:UCSRA:UCSRB:UCSRC:UBRRH:UBRRL] [UBRRH:UBRRL] io_com.bmp The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. The main features are: • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • High Resolution Baud Rate Generator • Supports Serial Frames with 5, 6, 7, 8 or 9 Data Bits and 1 or 2 Stop Bits • Odd or Even Parity Generation and Parity Check Supported by Hardware • Data OverRun Detection • Framing Error Detection • Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter • Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete • Multi-processor Communication Mode • Double Speed Asynchronous Communicat UDR USART I/O Data Register The UDR0 register is actually two physically separate registers sharing the same I/O address. When writing to the register, the USART Transmit Data register is written. When reading from UDR0, the USART Receive Data register is read. 0x0C 0x2C io_com.bmp N UDR7 USART I/O Data Register bit 7 RW 0 UDR6 USART I/O Data Register bit 6 RW 0 UDR5 USART I/O Data Register bit 5 RW 0 UDR4 USART I/O Data Register bit 4 RW 0 UDR3 USART I/O Data Register bit 3 RW 0 UDR2 USART I/O Data Register bit 2 RW 0 UDR1 USART I/O Data Register bit 1 RW 0 UDR0 USART I/O Data Register bit 0 RW 0 UCSRA USR USART Control and Status Register A 0x0B 0x2B io_flag.bmp Y RXC USART Receive Complete This bit is set (one) when a received character is transferred from the Receiver Shift register to UDR0. The bit is set regard-less of any detected framing errors. When the RXCIE bit in UCR is set, the USART Receive Complete interrupt will be executed when RXC is set(one). RXC is cleared by reading UDR0. When interrupt-driven data reception is used, the USART Receive Complete Interrupt routine must read UDRin order to clear RXC, otherwise a new interrupt will occur once the interrupt routine terminates. R 0 TXC USART Transmitt Complete This bit is set (one) when the entire character (including the stop bit) in the Transmit Shift register has been shifted out and no new data has been written to UDR0. This flag is especially useful in half-duplex communications interfaces, where a transmitting application must enter receive mode and free the communications bus immediately after completing the transmission. When the TXCIE bit in UCR is set, setting of TXC causes the USART Transmit Complete interrupt to be executed. TXC is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the TXC bit is cleared (zero) by writing a logical one to the bi RW 0 UDRE USART Data Register Empty This bit is set (one) when a character written to UDRis transferred to the Transmit shift register. Setting of this bit indicates that the transmitter is ready to receive a new character for transmission. When the UDR0IE bit in UCR is set, the USART Transmit Complete interrupt to be executed as long as UDR0E is set. UDR0E is cleared by writing UDR0. When interrupt-driven data transmittal is used, the USART Data Register Empty Interrupt routine must write UDRin order to clear UDR0E, otherwise a new interrupt will occur once the interrupt routine terminates. UDR0E is set (one) during reset to indicate that the transmitter is rea R 1 FE Framing Error This bit is set if a Framing Error condition is detected, i.e. when the stop bit of an incoming character is zero. The FE bit is cleared when the stop bit of received data is one. R 0 DOR Data overRun This bit is set if an Overrun condition is detected, i.e. when a character already present in the UDRregister is not read before the next character has been shifted into the Receiver Shift register. The OR bit is buffered, which means that it will be set once the valid data still in UDR0E is read. The OR bit is cleared (zero) when data is received and transferred to UDR0. R 0 UPE PE Parity Error This bit is set if the next character in the receive buffer had a Parity Error when received and the parity checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer (UDR0) is read. Always set this bit to zero when writing to UCSR0A. R 0 U2X Double the USART transmission speed This bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation. Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous communication. RW 0 MPCM Multi-processor Communication Mode This bit enables the Multi-processor Communication Mode. When the MPCM bit is written to one, all the incoming frames received by the USART receiver that do not contain address information will be ignored. The transmitter is unaffected by the MPCM setting. For more detailed information see “Multi-processor Communication Mode” on page 152. RW 0 UCSRB UCR USART Control and Status Register B 0x0A 0x2A io_flag.bmp Y RXCIE RX Complete Interrupt Enable Writing this bit to one enables interrupt on the RXC flag. A USART Receive Complete interrupt will be generated only if the RXCIE bit is written to one, the global interrupt flag in SREG is written to one and the RXC bit in UCSR0A is set. RW 0 TXCIE TX Complete Interrupt Enable Writing this bit to one enables interrupt on the TXC flag. A USART Transmit Complete interrupt will be generated only if the TXCIE bit is written to one, the global interrupt flag in SREG is written to one and the TXC bit in UCSR0A is set. RW 0 UDRIE USART Data register Empty Interrupt Enable Writing this bit to one enables interrupt on the UDR0E flag. A Data Register Empty interrupt will be generated only if the UDR0IE bit is written to one, the global interrupt flag in SREG is written to one and the UDR0E bit in UCSR0A is set. RW 1 RXEN Receiver Enable Writing this bit to one enables the USART receiver. The receiver will override normal port operation for the RxD pin when enabled. Disabling the receiver will flush the receive buffer invalidating the FE, DOR and PE flags. RW 0 TXEN Transmitter Enable Writing this bit to one enables the USART transmitter. The transmitter will override normal port operation for the TxD pin when enabled. The disabling of the transmitter (writing TXEN to zero) will not become effective until ongoing and pending transmissions are completed, i.e. when the transmit shift register and transmit buffer register does not contain data to be transmitted. When disabled, the transmitter will no longer override the TxD port. RW 0 UCSZ2 CHR9 Character Size The UCSZ2 bits combined with the UCSZ1:0 bit in UCSR0C sets the number of data bits (character size) in a frame the receiver and transmitter use. RW 0 RXB8 Receive Data Bit 8 RXB8 is the 9th data bit of the received character when operating with serial frames with 9 data bits. Must be read before reading the low bits from UDR0. R 0 TXB8 Transmit Data Bit 8 TXB8 is the 9th data bit in the character to be transmitted when operating with serial frames with 9 data bits. Must be writ-ten before writing the low bits to UDR0. W 0 UCSRC USART Control and Status Register C 0x20 0x40 io_flag.bmp Y URSEL Register Select This bit selects between accessing the UCSRC or the UBRRH register.It is read as one when reading UCSRC.The URSELmust be one when writing the UCSRC. RW 0 UMSEL USART Mode Select 0: Asynchronous Operation. 1: Synchronous Operation RW 0 UPM1 Parity Mode Bit 1 This bit enable and set type of parity generation and check. If enabled, the transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value for the incoming data and compare it to the UPM0 setting. If a mismatch is detected, the PE flag in UCSR0A will be set. RW 0 UPM0 Parity Mode Bit 0 This bit enable and set type of parity generation and check. If enabled, the transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value for the incoming data and compare it to the UPM0 setting. If a mismatch is detected, the PE flag in UCSR0A will be set. RW 0 USBS Stop Bit Select 0: 1-bit. 1: 2-bit. RW 0 UCSZ1 Character Size Character Size: 0 0 0 = 5-bit. 0 0 1 = 6-bit. 0 1 0 = 7 bit. 0 1 1 = 8-bit. 1 1 1 = 9 bit. RW 0 UCSZ0 Character Size Character Size: 0 0 0 = 5-bit. 0 0 1 = 6-bit. 0 1 0 = 7 bit. 0 1 1 = 8-bit. 1 1 1 = 9 bit. RW 1 UCPOL Clock Polarity This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOL bit sets the relationship between data output change and data input sample, and the synchronous clock (XCK). RW 0 UBRRH UBRRHI USART Baud Rate Register Hight Byte This is a 12-bit register which contains the USART baud rate. The UBRR0H contains the 4 most significant bits, and the UBRR0L contains the 8 least significant bits of the USART baud rate. Ongoing transmissions by the transmitter and receiver will be corrupted if the baud rate is changed. Writing UBRR0L will trigger an immediate update of the baud rate prescaler. 0x20 0x40 io_com.bmp N UBRR11 USART Baud Rate Register bit 11 RW 0 UBRR10 USART Baud Rate Register bit 10 RW 0 UBRR9 USART Baud Rate Register bit 9 RW 0 UBRR8 USART Baud Rate Register bit 8 RW 0 UBRRL USART Baud Rate Register Low Byte This is a 12-bit register which contains the USART baud rate. The UBRR0H contains the 4 most significant bits, and the UBRR0L contains the 8 least significant bits of the USART baud rate. Ongoing transmissions by the transmitter and receiver will be corrupted if the baud rate is changed. Writing UBRR0L will trigger an immediate update of the baud rate prescaler. 0x09 0x29 io_com.bmp N UBRR7 USART Baud Rate Register bit 7 RW 0 UBRR6 USART Baud Rate Register bit 6 RW 0 UBRR5 USART Baud Rate Register bit 5 RW 0 UBRR4 USART Baud Rate Register bit 4 RW 0 UBRR3 USART Baud Rate Register bit 3 RW 0 UBRR2 USART Baud Rate Register bit 2 RW 0 UBRR1 USART Baud Rate Register bit 1 RW 0 UBRR0 USART Baud Rate Register bit 0 RW 0 [TWBR:TWCR:TWSR:TWDR:TWAR] io_com.bmp TWI: Simple yet powerful and flexible communications interface, only two bus lines needed. Both master and slave operation supported. Device can operate as transmitter or receiver. 7-bit address space allows up to 128 different slave addresses. Multi-master arbitration support Up to 400 kHz data transfer speed Slew-rate limited output drivers Noise suppression circuitry rejects spikes on bus lines Fully programmable slave address with general call support Address recognition causes wake-up when AVR is in sleep mode The Two-Wire Serial Interface (TWI) is ideally suited to typical microcontroller applications. The TWI protocol allows the systems designer to interconnect up to 128 different devices using only two bidirectional bus lines, one for clock (SCL) andone for data (SDA). The only external hardware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines. All devices connected to the bus have individual addresses, and mechanisms for resolving bus contention are inherent in the TWI pr TWBR I2BR TWI Bit Rate register TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency divider which generates the SCL clock frequency in the master modes. See “Bit Rate Generator Unit” on page 165 for calculating bit rates. 0x00 0x20 io_com.bmp N TWBR7 RW 0 TWBR6 RW 0 TWBR5 RW 0 TWBR4 RW 0 TWBR3 RW 0 TWBR2 RW 0 TWBR1 RW 0 TWBR0 RW 0 TWCR I2CR TWI Control Register The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate a master access by applying a START condition to the bus, to generate a receiver acknowledge, to generate a stop condition, and to control halting of the bus while the data to be written to the bus are written to the TWDR. It also indicates a write collision if data is attempted written to TWDR while the register is inaccessible. 0x36 0x56 io_flag.bmp Y TWINT I2INT TWI Interrupt Flag This bit is set by hardware when the TWI has finished its current job and expects application software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the TWI interrupt vector. While the TWINT flag is set, the SCL low period is stretched. The TWINT flag must be cleared by software by writing a logic one to it. Note that this flag is not automatically cleared by hardware when executing the interrupt routine. Also note that clearing this flag starts the operation of the TWI, so all accesses to the TWI Address Register (TWAR), TWI Status Register (TWSR), and TWI Data Register (TWDR) must be complete before clearing this flag RW 0 TWEA I2EA TWI Enable Acknowledge Bit The TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is written to one, the ACK pulse is gener-ated on the TWI bus if the following conditions are met: 1. The device’s own slave address has been received. 2. A general call has been received, while the TWGCE bit in the TWAR is set. 3. A data byte has been received in master receiver or slave receiver mode. By writing the TWEA bit to zero, the device can be virtually disconnected from the 2-wire Serial Bus temporarily. Address recognition can then be resumed by writing the TWEA bit to one again RW 0 TWSTA I2STA TWI Start Condition Bit The application writes the TWSTA bit to one when it desires to become a master on the 2-wire Serial Bus. The TWI hard-ware checks if the bus is available, and generates a START condition on the bus if it is free. However, if the bus is not free, the TWI waits until a STOP condition is detected, and then generates a new START condition to claim the bus Master sta-tus. TWSTA is cleared by the TWI hardware when the START condition has been transmitted. RW 0 TWSTO I2STO TWI Stop Condition Bit Writing the TWSTO bit to one in master mode will generate a STOP condition on the 2-wire Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit is cleared automatically. In slave mode, setting the TWSTO bit can be used to recover from an error condition. This will not generate a STOP condition, but the TWI returns to a well-defined unaddressed slave mode and releases the SCL and SDA lines to a high impedance state. RW 0 TWWC I2WC TWI Write Collition Flag The TWWC bit is set when attempting to write to the TWI Data Register - TWDR when TWINT is low. This flag is cleared by writing the TWDR register when TWINT is high. RW 0 TWEN I2EN ENI2C TWI Enable Bit The TWEN bit enables TWI operation and activates the TWI interface. When TWEN is written to one, the TWI takes control over the I/O pins connected to the SCL and SDA pins, enabling the slew-rate limiters and spike filters. If this bit is written to zero, the TWI is switched off and all TWI transmissions are terminated, regardless of any ongoing operation. RW 0 TWIE I2IE TWI Interrupt Enable When this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request will be activated for as long as the TWINT flag is high. RW 0 TWSR I2SR TWI Status Register 0x01 0x21 io_flag.bmp Y TWS7 I2S7 TWI Status Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient c RW 0 TWS6 I2S6 TWI Status Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient co RW 0 TWS5 I2S5 TWI Status Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient c RW 0 TWS4 I2S4 TWI Status Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient co RW 0 TWS3 I2S3 TWI Status Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient co RW 0 TWPS1 TWS1 TWI Prescaler Bits 1..0: These bits can be read and written, and control the bit rate prescaler. See “Bit Rate Generator Unit” on page 165 for calculating bit rates. RW 0 TWPS0 TWS0 I2GCE TWI Prescaler Bits 1..0: These bits can be read and written, and control the bit rate prescaler. See “Bit Rate Generator Unit” on page 165 for calculating bit rates. RW 0 TWDR I2DR TWI Data register In transmit mode, TWDR contains the next byte to be transmitted. In receive mode, the TWDR contains the last byte received. It is writable while the TWI is not in the process of shifting a byte. This occurs when the TWI interrupt flag (TWINT) is set by hardware. Note that the data register cannot be initialized by the user before the first interrupt occurs. The data in TWDR remains stable as long as TWINT is set. While data is shifted out, data on the bus is simultaneously shifted in. TWDR always contains the last byte present on the bus, except after a wake up from a sleep mode by the TWI interrupt. In this case, the contents of TWDR is undefined. In the case of a lost bus arbitration, no data is lost in the transi-tion from Master to Slave. Handling of the ACK bit is controlled automatically by the TWI logic, the CPU cannot access the ACK bit directl 0x03 0x23 io_com.bmp N TWD7 TWI Data Register Bit 7 RW 1 TWD6 TWI Data Register Bit 6 RW 1 TWD5 TWI Data Register Bit 5 RW 1 TWD4 TWI Data Register Bit 4 RW 1 TWD3 TWI Data Register Bit 3 RW 1 TWD2 TWI Data Register Bit 2 RW 1 TWD1 TWI Data Register Bit 1 RW 1 TWD0 TWI Data Register Bit 0 RW 1 TWAR I2AR TWI (Slave) Address register The TWAR should be loaded with the 7-bit slave address (in the seven most significant bits of TWAR) to which the TWI will respond when programmed as a slave transmitter or receiver, and not needed in the master modes. In multimaster sys-tems, TWAR must be set in masters which can be addressed as slaves by other masters. The LSB of TWAR is used to enable recognition of the general call address ($00). There is an associated address compar-ator that looks for the slave address (or general call address if enabled) in the received serial address. If a match is found, an interrupt request is genera 0x02 0x22 io_com.bmp Y TWA6 TWI (Slave) Address register Bit 6 RW 0 TWA5 TWI (Slave) Address register Bit 5 RW 0 TWA4 TWI (Slave) Address register Bit 4 RW 0 TWA3 TWI (Slave) Address register Bit 3 RW 0 TWA2 TWI (Slave) Address register Bit 2 RW 0 TWA1 TWI (Slave) Address register Bit 1 RW 0 TWA0 TWI (Slave) Address register Bit 0 RW 0 TWGCE TWI General Call Recognition Enable Bit RW 0 [WDTCR] io_watch.bmp WDTCR WDTCSR Watchdog Timer Control Register 0x21 0x41 io_flag.bmp Y WDCE WDTOE Watchdog Change Enable This bit must be set when the WDE bit is written to logic zero.Otherwise,the watchdog will not be disabled.Once written to one,hardware will clear this bit after four clock cycles.Refer to the description of the WDE bit for a watchdog disable procedure.This bit must also be set when changing the prescaler bits. RW 0 WDE Watch Dog Enable When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog RW 0 WDP2 Watch Dog Timer Prescaler bit 2 The WDP2,WDP1,and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. RW 0 WDP1 Watch Dog Timer Prescaler bit 1 The WDP2,WDP1,and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. RW 0 WDP0 Watch Dog Timer Prescaler bit 0 The WDP2,WDP1,and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. RW 0 [PORTB:DDRB:PINB] io_port.bmp AVRSimIOPort.SimIOPort PORTB Port B Data Register 0x18 0x38 io_port.bmp N PORTB7 Port B Data Register bit 7 RW 0 PORTB6 Port B Data Register bit 6 RW 0 PORTB5 Port B Data Register bit 5 RW 0 PORTB4 Port B Data Register bit 4 RW 0 PORTB3 Port B Data Register bit 3 RW 0 PORTB2 Port B Data Register bit 2 RW 0 PORTB1 Port B Data Register bit 1 RW 0 PORTB0 Port B Data Register bit 0 RW 0 DDRB Port B Data Direction Register 0x17 0x37 io_flag.bmp N DDB7 Port B Data Direction Register bit 7 RW 0 DDB6 Port B Data Direction Register bit 6 RW 0 DDB5 Port B Data Direction Register bit 5 RW 0 DDB4 Port B Data Direction Register bit 4 RW 0 DDB3 Port B Data Direction Register bit 3 RW 0 DDB2 Port B Data Direction Register bit 2 RW 0 DDB1 Port B Data Direction Register bit 1 RW 0 DDB0 Port B Data Direction Register bit 0 RW 0 PINB Port B Input Pins The Port B Input Pins address - PINB - is not a register, and this address enables access to the physical value on each Port B pin. When reading PORTB, the Port B Data Latch is read, and when reading PINB, the logical values present on the pins are read. 0x16 0x36 io_port.bmp N PINB7 Port B Input Pins bit 7 R 0 PINB6 Port B Input Pins bit 6 R 0 PINB5 Port B Input Pins bit 5 R 0 PINB4 Port B Input Pins bit 4 R 0 PINB3 Port B Input Pins bit 3 R 0 PINB2 Port B Input Pins bit 2 R 0 PINB1 Port B Input Pins bit 1 R 0 PINB0 Port B Input Pins bit 0 R 0 [PORTC:DDRC:PINC] io_port.bmp AVRSimIOPort.SimIOPort PORTC Port C Data Register 0x15 0x35 io_port.bmp N PORTC6 Port C Data Register bit 6 RW 0 PORTC5 Port C Data Register bit 5 RW 0 PORTC4 Port C Data Register bit 4 RW 0 PORTC3 Port C Data Register bit 3 RW 0 PORTC2 Port C Data Register bit 2 RW 0 PORTC1 Port C Data Register bit 1 RW 0 PORTC0 Port C Data Register bit 0 RW 0 DDRC Port C Data Direction Register 0x14 0x34 io_flag.bmp N DDC6 Port C Data Direction Register bit 6 RW 0 DDC5 Port C Data Direction Register bit 5 RW 0 DDC4 Port C Data Direction Register bit 4 RW 0 DDC3 Port C Data Direction Register bit 3 RW 0 DDC2 Port C Data Direction Register bit 2 RW 0 DDC1 Port C Data Direction Register bit 1 RW 0 DDC0 Port C Data Direction Register bit 0 RW 0 PINC Port C Input Pins The Port C Input Pins address - PINC - is not a register, and this address enables access to the physical value on each Port C pin. When reading PORTC, the Port C Data Latch is read, and when reading PINC, the logical values present on the pins are read. 0x13 0x33 io_port.bmp N PINC6 Port C Input Pins bit 6 R 0 PINC5 Port C Input Pins bit 5 R 0 PINC4 Port C Input Pins bit 4 R 0 PINC3 Port C Input Pins bit 3 R 0 PINC2 Port C Input Pins bit 2 R 0 PINC1 Port C Input Pins bit 1 R 0 PINC0 Port C Input Pins bit 0 R 0 [PORTD:DDRD:PIND] io_port.bmp AVRSimIOPort.SimIOPort PORTD Port D Data Register 0x12 0x32 io_port.bmp N PORTD7 Port D Data Register bit 7 RW 0 PORTD6 Port D Data Register bit 6 RW 0 PORTD5 Port D Data Register bit 5 RW 0 PORTD4 Port D Data Register bit 4 RW 0 PORTD3 Port D Data Register bit 3 RW 0 PORTD2 Port D Data Register bit 2 RW 0 PORTD1 Port D Data Register bit 1 RW 0 PORTD0 Port D Data Register bit 0 RW 0 DDRD Port D Data Direction Register 0x11 0x31 io_flag.bmp N DDD7 Port D Data Direction Register bit 7 RW 0 DDD6 Port D Data Direction Register bit 6 RW 0 DDD5 Port D Data Direction Register bit 5 RW 0 DDD4 Port D Data Direction Register bit 4 RW 0 DDD3 Port D Data Direction Register bit 3 RW 0 DDD2 Port D Data Direction Register bit 2 RW 0 DDD1 Port D Data Direction Register bit 1 RW 0 DDD0 Port D Data Direction Register bit 0 RW 0 PIND Port D Input Pins The Port D Input Pins address - PIND - is not a register, and this address enables access to the physical value on each Port D pin. When reading PORTD, the Port D Data Latch is read, and when reading PIND, the logical values present on the pins are read. 0x10 0x30 io_port.bmp N PIND7 Port D Input Pins bit 7 R 0 PIND6 Port D Input Pins bit 6 R 0 PIND5 Port D Input Pins bit 5 R 0 PIND4 Port D Input Pins bit 4 R 0 PIND3 Port D Input Pins bit 3 R 0 PIND2 Port D Input Pins bit 2 R 0 PIND1 Port D Input Pins bit 1 R 0 PIND0 Port D Input Pins bit 0 R 0 [EEARH:EEARL:EEDR:EECR] [EEARH:EEARL] io_cpu.bmp EEPROM Read/Write Access. The EEPROM access registers are accessible in the I/O space. The write access time for the EEPROM is given in Table 1. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page 19. for details on how to avoid problems in these situations.In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When theEEPROM is written, the CPU is halted for two clock cycles before the next instruction is execute EEARH EEPROM Address Register High Byte Bits 11..0 - EEAR11..0: EEPROM Address The EEPROM Address Registers - EEARH and EEARL specify the EEPROM address in the 4K bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 4096. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed. 0x1F 0x3F io_cpu.bmp N EEAR8 EEPROM Read/Write Access Bit 8 RW 0 EEARL EEPROM Address Register Low Byte Bits 11..0 - EEAR11..0: EEPROM Address The EEPROM Address Registers - EEARH and EEARL specify the EEPROM address in the 4K bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 4096. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed. 0x1E 0x3E io_cpu.bmp N EEAR7 EEPROM Read/Write Access Bit 7 RW 0 EEAR6 EEPROM Read/Write Access Bit 6 RW 0 EEAR5 EEPROM Read/Write Access Bit 5 RW 0 EEAR4 EEPROM Read/Write Access Bit 4 RW 0 EEAR3 EEPROM Read/Write Access Bit 3 RW 0 EEAR2 EEPROM Read/Write Access Bit 2 RW 0 EEAR1 EEPROM Read/Write Access Bit 1 RW 0 EEAR0 EEPROM Read/Write Access Bit 0 RW 0 EEDR EEPROM Data Register For the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR. 0x1D 0x3D io_cpu.bmp N EEDR7 EEPROM Data Register bit 7 RW 0 EEDR6 EEPROM Data Register bit 6 RW 0 EEDR5 EEPROM Data Register bit 5 RW 0 EEDR4 EEPROM Data Register bit 4 RW 0 EEDR3 EEPROM Data Register bit 3 RW 0 EEDR2 EEPROM Data Register bit 2 RW 0 EEDR1 EEPROM Data Register bit 1 RW 0 EEDR0 EEPROM Data Register bit 0 RW 0 EECR EEPROM Control Register 0x1C 0x3C io_flag.bmp Y EERIE EEPROM Ready Interrupt Enable EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared. RW 0 EEMWE EEWEE EEPROM Master Write Enable The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is written to one, writing EEWE to one within 4 clock cycles will write data to the EEPROM at the selected address. If EEMWE is zero, writing EEWE to one will have no effect. When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure. RW 0 EEWE EEPROM Write Enable The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential): 1. Wait until EEWE becomes zero. 2. Wait until SPMEN in SPMCR becomes zero. 3. Write new EEPROM address to EEAR (optional). 4. Write new EEPROM data to EEDR (optional). 5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR. 6. Within four clock cycles after setting EEMWE, write a logical one to EEWE. The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a boot loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See “Boot Loader Support - Read While Write self-programming” on page 228 for details about boot programming. Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR regis-ter will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the 4 last steps to avoid these problems. When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruc-tion is executed RW X EERE EEPROM Read Enable The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR register. The calibrated oscillator is used to time the EEPROM accesses. Table 1 lists the typical programming time for EEPROM access from the CPU RW 0 [SREG:SPH:SPL:MCUCR:MCUCSR:OSCCAL:SPMCR:SFIOR] [SPH:SPL] io_cpu.bmp SREG Status Register 0x3F 0x5F io_sreg.bmp Y I Global Interrupt Enable The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable bit is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. RW 0 T Bit Copy Storage The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction. RW 0 H Half Carry Flag The half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed information. RW 0 S Sign Bit The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruc-tion Set Description for detailed information. RW 0 V Two's Complement Overflow Flag The two’s complement overflow flag V supports two’s complement arithmetics. See the Instruction Set Description for detailed information. RW 0 N Negative Flag The negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information. RW 0 Z Zero Flag The zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information. RW 0 C Carry Flag The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software. RW 0 SPH Stack Pointer High The general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the AT90S4414/8515 supports up to 64 kB external SRAM, all 16-bits are used. The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or return from interrupt R 0x3E 0x5E io_sph.bmp N SP10 Stack pointer bit 10 RW 0 SP9 Stack pointer bit 9 RW 0 SP8 Stack pointer bit 8 RW 0 SPL Stack Pointer Low The general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the AT90S4414/8515 supports up to 64 kB external SRAM, all 16-bits are used. The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or return from interrupt 0x3D 0x5D io_sph.bmp N SP7 Stack pointer bit 7 RW 0 SP6 Stack pointer bit 6 RW 0 SP5 Stack pointer bit 5 RW 0 SP4 Stack pointer bit 4 RW 0 SP3 Stack pointer bit 3 RW 0 SP2 Stack pointer bit 2 RW 0 SP1 Stack pointer bit 1 RW 0 SP0 Stack pointer bit 0 RW 0 MCUCR MCU Control Register The MCU Control Register contains control bits for general MCU functions. 0x35 0x55 io_flag.bmp Y SE Sleep Enable RW 0 SM2 Sleep Mode Select The description is to long for the tooltip help, please refer to the manual RW 0 SM1 Sleep Mode Select The description is to long for the tooltip help, please refer to the manual RW 0 SM0 Sleep Mode Select The description is to long for the tooltip help, please refer to the manual RW 0 ISC11 Interrupt Sense Control 1 Bit 1 ISC10 Interrupt Sense Control 1 Bit 0 RW 0 ISC01 Interrupt Sense Control 0 Bit 1 RW 0 ISC00 Interrupt Sense Control 0 Bit 0 RW 0 MCUCSR MCUSR MCU Control And Status Register The MCU Control And Status Register provides information on which reset source caused a MCU reset. 0x34 0x54 io_flag.bmp Y WDRF Watchdog Reset Flag This bit is set if a watchdog reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag. R/W 0 BORF Brown-out Reset Flag This bit is set if a brown-out reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag. R/W 0 EXTRF External Reset Flag This bit is set if an external reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag. R/W 0 PORF Power-on reset flag This bit is set if a power-on reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the reset flags to identify a reset condition, the user should read and then reset the MCUCSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags. R/W 0 OSCCAL Oscillator Calibration Value Writing the calibration byte to this address will trim the internal oscillator to remove process variations from the oscillator frequency. This is done automatically during chip reset. When OSCCAL is zero, the lowest available frequency is chosen. Writing non-zero values to this register will increase the frequency of the internal oscillator. Writing $FF to the register gives the highest available frequency. The calibrated oscillator is used to time EEPROM and Flash access. If EEPROM or Flash is written, do not calibrate to more than 10% above the nominal frequency. Otherwise, the EEPROM or Flash write may fail. Note that the Oscillator is intended for calibration to 1.0 MHz, 2.0 MHz, 4.0 MHz, or 8.0MHz. Tuning to other values is not guaranteed, as indicated in Table 14 0x31 0x51 io_cpu.bmp N CAL7 Oscillator Calibration Value Bit7 R/W 0 CAL6 Oscillator Calibration Value Bit6 R/W 0 CAL5 Oscillator Calibration Value Bit5 R/W 0 CAL4 Oscillator Calibration Value Bit4 R/W 0 CAL3 Oscillator Calibration Value Bit3 R/W 0 CAL2 Oscillator Calibration Value Bit2 R/W 0 CAL1 Oscillator Calibration Value Bit1 R/W 0 CAL0 Oscillator Calibration Value Bit0 R/W 0 SPMCR Store Program Memory Control Register 0x37 0x57 io_cpu.bmp Y SPMIE SPM Interrupt Enable When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN bit in the SPMCR register is cleared. R/W 0 RWWSB Read-While-Write Section Busy When a Self-Programming (page erase or page write) operation to the RWW section is initiated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a Self-Programming operation is completed. Alternatively the RWWSB bit will automatically be cleared if a page load operation is initiated. R 0 RWWSRE Read-While-Write Section Read Enable When programming (page erase or page write) to the RWW section, the RWW section is blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW section, the user software must wait until the programming is completed (SPMEN will be cleared). Then, if the RWWSRE bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles re-enables the RWW section. The RWW section cannot be re-enabled while the Flash is busy with a page erase or a page write (SPMEN is set). If the RWWSRE bit is written while the Flash is being loaded, the Flash load operation will abort and the data loaded will be lost R/W 0 BLBSET Boot Lock Bit Set If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles sets Boot Lock bits, according to the data in R0. The data in R1 and the address in the Z pointer are ignored. The BLBSET bit will automatically be cleared upon completion of the lock bit set, or if no SPM instruction is executed within four clock cycles. R/W 0 PGWRT Page Write If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed. R/W 0 PGERS Page Erase If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page erase. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a page erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed. R/W 0 SPMEN Store Program Memory Enable The explanation is to long to include here. Please refer to the printed documentation. R/W 0 SFIOR Special Function IO Register 0x30 0x50 io_cpu.bmp Y ADHSM ADC High Speed Mode Writing this bit to one enables the ADC High Speed Mode. This mode enables higher R/W 0 PUD Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See “Configuring the Pin” on page 48 for more details about this feature. R/W 0 PSR10 Prescaler Reset Timer/Counter1 and Timer/Counter0 When this bit is written to one, the Timer/Counter1 and Timer/Counter0 prescaler will be reset. The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. This bit will always be read as zero. R/W 0 [ADMUX:ADCSRA:ADCH:ADCL] [ADCH:ADCL] ((IF ADMUX.ADLAR = 1) LINK [ADCH(1:0):ADCL(7:0)]); (IF ADMUX.ADLAR = 0) LINK [ADCH(7:0):ADCL(7:6)]); io_analo.bmp AD Converter Feature list: 10-bit Resolution. 0.5 LSB Integral Non-Linearity. +-2 LSB Absolute Accuracy. TBD - 260 µs Conversion Time. Up to TBD kSPS at maximum resolution. 8 Multiplexed Single Ended Input Channels. 7 Differential input channels (TQFP package only). 2 Differential input channels with optional gain of 10x and 200x (TQFP package only). Optional left adjustment for ADC result readout. 0 - VCC ADC Input Voltage Range. Selectable 2.56 V ADC reference voltage. Free Running or Single Conversion Mode. Interrupt on ADC Conversion Complete. Sleep Mode Noise ADMUX The ADC multiplexer Selection Register 0x07 0x27 io_analo.bmp Y REFS1 Reference Selection Bit 1 These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin. RW 0 REFS0 Reference Selection Bit 0 These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin. RW 0 ADLAR Left Adjust Result The ADLAR bit affects the presentation of the ADC conversion result in the ADC data register. If ADLAR is cleared, the result is right adjusted. If ADLAR is set, the result is left adjusted. Changing the ADLAR bit will affect the ADC data register immediately, regardless of any ongoing conversions. For a complete description of this bit, see “The ADC Data Register -ADCL and ADCH” on page 198. RW 0 MUX3 Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). RW 0 MUX2 Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). RW 0 MUX1 Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). RW 0 MUX0 Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). RW 0 ADCSRA ADCSR The ADC Control and Status register 0x06 0x26 io_flag.bmp Y ADEN ADC Enable Writing a logical ‘1’ to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion. RW 0 ADSC ADC Start Conversion In Single Conversion Mode, a logical ‘1’ must be written to this bit to start each conversion. In Free Running Mode, a logical ‘1’ must be written to this bit to start the first conversion. The first time ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, an extended conversion will result. This extended conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. When a dummy conversion precedes a real conversion, ADSC will stay high until the real conversion completes. Writing a 0 to this bit has no effect RW 0 ADFR ADC Free Running Select When this bit is set (one) the ADC operates in Free Running Mode. In this mode, the ADC samples and updates the data registers continuously. Clearing this bit (zero) will terminate Free Running Mode. RW 0 ADIF ADC Interrupt Flag This bit is set (one) when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set (one). ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a read-modify-write on ADCSR, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used. RW 0 ADIE ADC Interrupt Enable When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Complete Interrupt is activated. RW 0 ADPS2 ADC Prescaler Select Bits These bits determine the division factor between the XTAL frequency and the input clock to the ADC. RW 0 ADPS1 ADC Prescaler Select Bits These bits determine the division factor between the XTAL frequency and the input clock to the ADC. RW 0 ADPS0 ADC Prescaler Select Bits These bits determine the division factor between the XTAL frequency and the input clock to the ADC. RW 0 ADCH ADC Data Register High Byte When an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. The selected channel is differential if MUX4..0 are between ‘01000’ and ‘11101’, otherwise the selected channel is single ended. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8 bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUX4..0 bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adju 0x05 0x25 io_analo.bmp N ADCH7 ADC Data Register High Byte Bit 7 RW 0 ADCH6 ADC Data Register High Byte Bit 6 RW 0 ADCH5 ADC Data Register High Byte Bit 5 RW 0 ADCH4 ADC Data Register High Byte Bit 4 RW 0 ADCH3 ADC Data Register High Byte Bit 3 RW 0 ADCH2 ADC Data Register High Byte Bit 2 RW 0 ADCH1 ADC Data Register High Byte Bit 1 RW 0 ADCH0 ADC Data Register High Byte Bit 0 RW 0 ADCL ADC Data Register Low Byte When an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. The selected channel is differential if MUX4..0 are between ‘01000’ and ‘11101’, otherwise the selected channel is single ended. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8 bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUX4..0 bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right ad 0x04 0x24 io_analo.bmp N ADCL7 ADC Data Register Low Byte Bit 7 RW 0 ADCL6 ADC Data Register Low Byte Bit 6 RW 0 ADCL5 ADC Data Register Low Byte Bit 5 RW 0 ADCL4 ADC Data Register Low Byte Bit 4 RW 0 ADCL3 ADC Data Register Low Byte Bit 3 RW 0 ADCL2 ADC Data Register Low Byte Bit 2 RW 0 ADCL1 ADC Data Register Low Byte Bit 1 RW 0 ADCL0 ADC Data Register Low Byte Bit 0 RW 0 [ICE50:SIMULATOR:STK500:STK500_2:AVRISPmkII:AVRDragon] 0x05 0x0F 0x0F 0x0F 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x0F 0x0F 0x0F 0x15 0x14 0x14 0x0000045f 0x00000000 0x00000000 0x00000000 0x000001FF 0x00001FFF 0x00000FFF 0x00000FFF 0x00000FFF 0x00000FFF 0x0000045f 0x0000FFFF 0x000001FF 0x00000000 0x00000000 0x00000000 0x0023FFFF 0x00000FFF 0x00000060 0xD9 0xe1 0xff 0x51 0xc7 ATmega8.bin 0x02 0x00 1000000 20000000 2 ; INTOSC = 1, INTRC=2;EXTCLK=4 1 ;NOTUSE = 1, EXTERNAL = 4, INTERNAL = 2 1 0 0x00 0x01 0x00 0x01 0x00000600 0x00000600 Boot Size 128 Words, 4 pages, $F80-$FFF, Boot reset $F80 0x00000600 0x00000400 Boot Size 256 Words, 8 pages, $F00-$FFF, Boot reset $F00 0x00000600 0x00000200 Boot Size 512 Words, 16 pages, $E00-$FFF, Boot reset $E00 0x00000600 0x00000000 Boot Size 1024 Words, 32 pages, $C00-$FFF, Boot reset $C00 0x00000031 0x00000000 258 CK, 4 ms 0x00000031 0x00000010 258 CK, 64 ms 0x00000031 0x00000020 1K CK 0x00000031 0x00000030 1K CK, 4 ms 0x00000031 0x00000001 1K CK, 64 ms 0x00000031 0x00000011 16K CK 0x00000031 0x00000021 16K CK, 4 ms 0x00000031 0x00000031 16K CK, 64 ms 0x00000030 0x00000000 6 CK 0x00000030 0x00000010 6 CK, 4 ms 0x00000030 0x00000020 6 CK, 64 ms 0x00000030 0x00000000 6 CK 0x00000030 0x00000010 6 CK, 4 ms 0x00000030 0x00000020 6 CK, 64 ms 0x0000103f 0x0000002b 0x0000103f 0x00001021 1.0 0x0000103f 0x00001022 2.0 0x0000103f 0x00001023 4.0 0x0000103f 0x00001024 8.0 0x0000103f 0x00001020 0x00000100 0x00000100 Application reset, address $0 0x00000100 0x00000000 Boot loader reset 0x0c000000 0x0c000000 No restrictions for SPM or (E)LPM 0x0c000000 0x08000000 No write to the Application section 0x0c000000 0x00000000 No write to Application section, No read from the Application section 0x0c000000 0x04000000 No read from the Application section 0x30000000 0x30000000 No restrictions for SPM or (E)LPM 0x30000000 0x20000000 No write to the Boot Loader section 0x30000000 0x00000000 No write to Boot Loader section, No read from the Boot Loader section 0x30000000 0x10000000 No read from the Boot Loader section 0x00004000 0x00000000 Watchdog always ON 0x00004000 0x00004000 Watchdog disabled 0x00008000 0x00000000 RSTDSBL Fuse 0x00008000 0x00008000 RSTDSBL 0x000000C0 0x000000C0 BOD disabled 0x000000C0 0x00000080 BOD enabled, 2.7 V 0x000000C0 0x00000000 BOD enabled, 4.0 V AVRSimCoreV2.SimCoreV2 AVRSimMemory8bit.SimMemory8bit AVRSimInterrupt.SimInterrupt 0x0f 0 14 AVRSimIOPort.SimIOPort N AVRSimIOPort.SimIOPort N AVRSimIOPort.SimIOPort N AVRSimIOExtInterrupt.SimIOExtInterrupt 0x01 0x3B 0x40 0x3A 0x40 0x10 0x04 0x35 0x03 AVRSimIOExtInterrupt.SimIOExtInterrupt 0x02 0x3B 0x80 0x3A 0x80 0x10 0x08 0x35 0x0c AVRSimIOTimert81.SimIOTimert81 0x09 0x10 0x10 AVRSimIOTimert16pwm1.SimIOTimert16pwm1 0x05 0x06 0x07 0x08 0x10 0x20 0x16 0x01 0x16 0x02 0x16 0x04 AvrMasterTimer.MasterTimer 0x03 0x04 PORTB 3 1:8:32:64:128:256:1024 AVRSimIOSPM.SimIOSPM 0x12 AVRSimIOSpi.SimIOSpi 0x0A 0x16 0x20 0x16 0x10 0x16 0x08 0x16 0x17 0x04 AVRSimIOUsart.SimIOUsart 0x0B 0x0D 0x0C 0x10 0x02 0x10 0x01 AVRSimAC.SimIOAC 0x10 AVRSimADC.SimADC 0x0E AvrSimTWI.SimTWI 0x11 0x99 0xff 0xe1 0xff 0x72 1 1 1 0xFF 0xFF 0xFF 0 1 2001002532030x53112000x2164100x400x4C0x200xFF0x000x04128200xC00x000xA00xFF0xFF25625644440x0E 0x1E 0x0F 0x1F 0x2E 0x3E 0x2F 0x3F 0x4E 0x5E 0x4F 0x5F 0x6E 0x7E 0x6F 0x7F 0x66 0x76 0x67 0x77 0x6A 0x7A 0x6B 0x7B 0xBE 0xFD 0x00 0x01 0x00 0x00 0x00 0x001000511520151501050x0D25625650x052562560505