[ADMIN:PACKAGE:MEMORY:CORE:INTERRUPT_VECTOR:FUSE:LOCKBIT:PROGRAMMING:IO_MODULE:ICE_SETTINGS] ATmega88 20MHZ 214 RELEASED $1E $93 $0A [TQFP:MLF:PDIP] 32 [PD3:PCINT19:OC2B:INT1] INT1,External Interrupt source 1:The PD3 pin can serve as an external interrupt source. [PD4:XCK:T0:PCINT20] XCK, USART external clock. T0,Timer/Counter0 counter source. [GND] [VCC] [GND] [VCC] [PB6:XTAL1:TOSC1:PCINT6] XTAL1:Chipclock oscillator pin 1.Used for all chipclock sources except internal calibratable RC oscillator.When used as a clock pin,the pin can not be used as an I/O pin.When using internal calibratable RC oscillator as chip clock source,PB6 functions as an ordinary I/O pin. TOSC1:Timer Oscillator pin 1.Used only if internal calibratable RC oscillator is selected as chip clock source,and the asynchronous timer is enabled by the correct setting in ASSR.When the AS2 bit in ASSR is set (one)to enable asynchronous clocking of Timer/Counter1,pin PB6 is disconnected from the port,and becomes the input of the inverting oscillator amplifier.In this mode,a crystal oscillator is connected to this pin,and the pin can not be used as an I/O pin. If PB6 is used as a clock pin,DDB6,PORTB6 and PINB6 will all rea [PB7:XTAL2:TOSC2:PCINT7] XTAL2:Chip clock oscillator pin 2.Used as clock pin for all chip clock sources except internal calibratable RC oscillator and external clock.When used as a clock pin,the pin can not be used as an I/O pin.When using internal calibratable RC oscillator or external clock as chipclock sources,PB7 functions as an ordinary I/O pin. TOSC2:Timer Oscillator pin 2.Used only if internal calibratable RC oscillator is selected as chip clock source,and the asynchronous timer is enabled by the correct setting in ASSR.When the AS2 bit in ASSR is set (one)to enable asynchro- nous clocking of Timer/Counter2,pin PB7 is disconnected from the port,and becomes the inverting output of the oscillator amplifier.In this mode,a crystal oscillator is connected to this pin,and the pin can not be used as an I/O pin. If PB7 is used as a clock pin,DDB7,PORTB7 and PINB7 will all read [PD5:T1:OC0B:PCINT21] T1,Timer/Counter1 counter source. [PD6:AIN0:OC0A:PCINT22] AIN0,Analog Comparator Positive Input.Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the analog comparator. [PD7:AIN1:PCINT23] AIN1,Analog Comparator Negative Input.Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the analog comparator. [PB0:ICP1:CLKO:PCINT0] ICP1 -Input Capture Pin:The PB0 pin can act as an input capture pin for Timer/Counter1. [PB1:OC1A:PCINT1] OC1A,Output compare match output:The PB1 pin can serve as an external output for the Timer/Counter1 compare match A.The PB1 pin has to be configured as an output (DDB1 set (one))to serve this function.The OC1A pin is also the output pin for the PWM mode timer function. [PB2:'SS:OC1B:PCINT2] SS:Slave Select input.When the SPI is enabled as a slave,this pin is configured as an input regardless of the setting of DDB4.As a slave,the SPI is activated when this pin is driven low.When the SPI is enabled as a master,the data direction of this pin is controlled by DDB4.When the pin is forced by the SPI to be an input,the pull-up can still be controlled by the PORTB4 bit. OC1B,Output compare match output:The PB2 pin can serve as an external output for the Timer/Counter1 compare match B.The PB2 pin has to be configured as an output (DDB2 set (one))to serve this function.The OC1B pin is also the output pin for the PWM mode timer fu [PB3:MOSI:OC2A:PCINT3] MOSI:SPI Master data output,slave data input for SPI channel.When the SPI is enabled as a slave,this pin is configured as an input regardless of the setting of DDB5.When the SPI is enabled as a master,the data direction of this pin is controlled by DDB5.When the pin is forced by the SPI to be an input,the pull-up can still be controlled by the PORTB bit. [PB4:MISO:PCINT4] MISO:Master data Input,Slave data Output pin for SPI channel.When the SPI is enabled as a master,this pin is configured as an input regardless of the setting of DDB6.When the SPI is enabled as a slave,the data direction of this pin is controlled by DDB6.When the pin is forced by the SPI to be an input,the pull-up can still be controlled by the PORTB6 bit. [PB5:SCK:PCINT5] SCK:Master clock output,slave clock input pin for SPI channel.When the SPI is enabled as a slave,this pin is configured as an input regardless of the setting of DDB7.When the SPI is enabled as a master,the data direction of this pin is controlled by DDB7.When the pin is forced by the SPI to be an input,the pull-up can still be controlled by the PORTB7 bit. [AVCC] [ADC6] [AREF] [GND] [ADC7] [PC0:ADC0:PCINT8] PC0 can also be used as ADC input Channel 0.Note that ADC input channel 0 uses analog ground. [PC1:ADC1:PCINT9] PC1 can also be used as ADC input Channel 1.Note that ADC input channel 1 uses analog ground. [PC2:ADC2:PCINT10] PC2 can also be used as ADC input Channel 2.Note that ADC input channel 2 uses analog ground. [PC3:ADC3:PCINT11] PC3 can also be used as ADC input Channel 3.Note that ADC input channel 3 uses analog ground. [PC4:ADC4:SDA:PCINT12] SDA,2-wire Serial Interface Data:When the TWEN bit in TWCR is set (one)to enable the 2-wire Serial Interface,pin PC1 is disconnected from the port and becomes the Serial Data I/O pin for the 2-wire Serial Interface.In this mode,there is a spike filter on the pin to suppress spikes shorter than 0 ns on the input signal,and the pin is driven by an open drain driver with slew-rate limitation. PC4 can also be used as ADC input Channel 4.Note that ADC input channel 4 uses digital ground. [PC5:ADC5:SCL:PCINT13] SCL,2-wire Serial Interface Clock:When the TWEN bit in TWCR is set (one)to enable the 2-wire Serial Interface,pin PC1 is disconnected from the port and becomes the Serial Clock I/O pin for the 2-wire Serial Interface.In this mode,there is a spike filter on the pin to suppress spikes shorter than 0 ns on the input signal,and the pin is driven by an open drain driver with slew-rate limitation. PC can also be used as ADC input Channel 5.Note that ADC input channel uses digital ground. [PC6:'RESET:PCINT14] RESET, Reset pin: When the RSTDISBL fuse is set,this pin functions as a normal I/O pin,and the part will have to rely on Power-On Reset and Brown-Out Reset as its reset sources.When the RSTDISBL fuse is cleared,the reset circuitry is connected to the pin,and the pin can not be used as an I/O pin. If PC6 is used as a reset pin,DDC6,PORTC6 and PINC6 will all read 0. [PD0:RXD:PCINT16] RXD,Receive Data (Data input pin for the USART).When the USART receiver is enabled this pin is configured as an input regardless of the value of DDD0.When the USART forces this pin to be an input,the pull-up can still be controlled by the PORTD0 bit. [PD1:TXD:PCINT17] TXD,Transmit Data (Data output pin for the USART).When the USART transmitter is enabled,this pin is configured as an output regardless of the value of DDD1. [PD2:INT0:PCINT18] INT0,External Interrupt source 0:The PD2 pin can serve as an external interrupt source. 32 [PD3:PCINT19:OC2B:INT1] INT1,External Interrupt source 1:The PD3 pin can serve as an external interrupt source. [PD4:XCK:T0:PCINT20] XCK, USART external clock. T0,Timer/Counter0 counter source. [GND] [VCC] [GND] [VCC] [PB6:XTAL1:TOSC1:PCINT6] XTAL1:Chipclock oscillator pin 1.Used for all chipclock sources except internal calibratable RC oscillator.When used as a clock pin,the pin can not be used as an I/O pin.When using internal calibratable RC oscillator as chip clock source,PB6 functions as an ordinary I/O pin. TOSC1:Timer Oscillator pin 1.Used only if internal calibratable RC oscillator is selected as chip clock source,and the asynchronous timer is enabled by the correct setting in ASSR.When the AS2 bit in ASSR is set (one)to enable asynchronous clocking of Timer/Counter1,pin PB6 is disconnected from the port,and becomes the input of the inverting oscillator amplifier.In this mode,a crystal oscillator is connected to this pin,and the pin can not be used as an I/O pin. If PB6 is used as a clock pin,DDB6,PORTB6 and PINB6 will all rea [PB7:XTAL2:TOSC2:PCINT7] XTAL2:Chip clock oscillator pin 2.Used as clock pin for all chip clock sources except internal calibratable RC oscillator and external clock.When used as a clock pin,the pin can not be used as an I/O pin.When using internal calibratable RC oscillator or external clock as chipclock sources,PB7 functions as an ordinary I/O pin. TOSC2:Timer Oscillator pin 2.Used only if internal calibratable RC oscillator is selected as chip clock source,and the asynchronous timer is enabled by the correct setting in ASSR.When the AS2 bit in ASSR is set (one)to enable asynchro- nous clocking of Timer/Counter2,pin PB7 is disconnected from the port,and becomes the inverting output of the oscillator amplifier.In this mode,a crystal oscillator is connected to this pin,and the pin can not be used as an I/O pin. If PB7 is used as a clock pin,DDB7,PORTB7 and PINB7 will all read [PD5:T1:OC0B:PCINT21] T1,Timer/Counter1 counter source. [PD6:AIN0:OC0A:PCINT22] AIN0,Analog Comparator Positive Input.Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the analog comparator. [PD7:AIN1:PCINT23] AIN1,Analog Comparator Negative Input.Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the analog comparator. [PB0:ICP:CLKO:PCINT0] ICP -Input Capture Pin:The PB0 pin can act as an input capture pin for Timer/Counter1. [PB1:OC1A:PCINT1] OC1A,Output compare match output:The PB1 pin can serve as an external output for the Timer/Counter1 compare match A.The PB1 pin has to be configured as an output (DDB1 set (one))to serve this function.The OC1A pin is also the output pin for the PWM mode timer function. [PB2:'SS:OC1B:PCINT2] SS:Slave Select input.When the SPI is enabled as a slave,this pin is configured as an input regardless of the setting of DDB4.As a slave,the SPI is activated when this pin is driven low.When the SPI is enabled as a master,the data direction of this pin is controlled by DDB4.When the pin is forced by the SPI to be an input,the pull-up can still be controlled by the PORTB4 bit. OC1B,Output compare match output:The PB2 pin can serve as an external output for the Timer/Counter1 compare match B.The PB2 pin has to be configured as an output (DDB2 set (one))to serve this function.The OC1B pin is also the output pin for the PWM mode timer fu [PB3:MOSI:OC2A:PCINT3] MOSI:SPI Master data output,slave data input for SPI channel.When the SPI is enabled as a slave,this pin is configured as an input regardless of the setting of DDB5.When the SPI is enabled as a master,the data direction of this pin is controlled by DDB5.When the pin is forced by the SPI to be an input,the pull-up can still be controlled by the PORTB bit. [PB4:MISO:PCINT4] MISO:Master data Input,Slave data Output pin for SPI channel.When the SPI is enabled as a master,this pin is configured as an input regardless of the setting of DDB6.When the SPI is enabled as a slave,the data direction of this pin is controlled by DDB6.When the pin is forced by the SPI to be an input,the pull-up can still be controlled by the PORTB6 bit. [PB5:SCK:PCINT5] SCK:Master clock output,slave clock input pin for SPI channel.When the SPI is enabled as a slave,this pin is configured as an input regardless of the setting of DDB7.When the SPI is enabled as a master,the data direction of this pin is controlled by DDB7.When the pin is forced by the SPI to be an input,the pull-up can still be controlled by the PORTB7 bit. [AVCC] [ADC6] [AREF] [GND] [ADC7] [PC0:ADC0:PCINT8] PC0 can also be used as ADC input Channel 0.Note that ADC input channel 0 uses analog ground. [PC1:ADC1:PCINT9] PC1 can also be used as ADC input Channel 1.Note that ADC input channel 1 uses analog ground. [PC2:ADC2:PCINT10] PC2 can also be used as ADC input Channel 2.Note that ADC input channel 2 uses analog ground. [PC3:ADC3:PCINT11] PC3 can also be used as ADC input Channel 3.Note that ADC input channel 3 uses analog ground. [PC4:ADC4:SDA:PCINT12] SDA,2-wire Serial Interface Data:When the TWEN bit in TWCR is set (one)to enable the 2-wire Serial Interface,pin PC1 is disconnected from the port and becomes the Serial Data I/O pin for the 2-wire Serial Interface.In this mode,there is a spike filter on the pin to suppress spikes shorter than 0 ns on the input signal,and the pin is driven by an open drain driver with slew-rate limitation. PC4 can also be used as ADC input Channel 4.Note that ADC input channel 4 uses digital ground. [PC5:ADC5:SCL:PCINT13] SCL,2-wire Serial Interface Clock:When the TWEN bit in TWCR is set (one)to enable the 2-wire Serial Interface,pin PC1 is disconnected from the port and becomes the Serial Clock I/O pin for the 2-wire Serial Interface.In this mode,there is a spike filter on the pin to suppress spikes shorter than 0 ns on the input signal,and the pin is driven by an open drain driver with slew-rate limitation. PC can also be used as ADC input Channel 5.Note that ADC input channel uses digital ground. [PC6:'RESET:PCINT14] RESET, Reset pin: When the RSTDISBL fuse is set,this pin functions as a normal I/O pin,and the part will have to rely on Power-On Reset and Brown-Out Reset as its reset sources.When the RSTDISBL fuse is cleared,the reset circuitry is connected to the pin,and the pin can not be used as an I/O pin. If PC6 is used as a reset pin,DDC6,PORTC6 and PINC6 will all read 0. [PD0:RXD:PCINT16] RXD,Receive Data (Data input pin for the USART).When the USART receiver is enabled this pin is configured as an input regardless of the value of DDD0.When the USART forces this pin to be an input,the pull-up can still be controlled by the PORTD0 bit. [PD1:TXD:PCINT17] TXD,Transmit Data (Data output pin for the USART).When the USART transmitter is enabled,this pin is configured as an output regardless of the value of DDD1. [PD2:INT0:PCINT18] INT0,External Interrupt source 0:The PD2 pin can serve as an external interrupt source. 28 [PC6:'RESET:PCINT14] RESET, Reset pin: When the RSTDISBL fuse is set,this pin functions as a normal I/O pin,and the part will have to rely on Power-On Reset and Brown-Out Reset as its reset sources.When the RSTDISBL fuse is cleared,the reset circuitry is connected to the pin,and the pin can not be used as an I/O pin. If PC6 is used as a reset pin,DDC6,PORTC6 and PINC6 will all read 0. [PD0:RXD:PCINT16] RXD,Receive Data (Data input pin for the USART).When the USART receiver is enabled this pin is configured as an input regardless of the value of DDD0.When the USART forces this pin to be an input,the pull-up can still be controlled by the PORTD0 bit. [PD1:TXD:PCINT17] TXD,Transmit Data (Data output pin for the USART).When the USART transmitter is enabled,this pin is configured as an output regardless of the value of DDD1. [PD2:INT0:PCINT18] INT0,External Interrupt source 0:The PD2 pin can serve as an external interrupt source. [PD3:PCINT19:OC2B:INT1] INT1,External Interrupt source 1:The PD3 pin can serve as an external interrupt source. [PD4:XCK:T0:PCINT20] XCK, USART external clock. T0,Timer/Counter0 counter source. [VCC] [GND] [PB6:XTAL1:TOSC1:PCINT6] XTAL1:Chipclock oscillator pin 1.Used for all chipclock sources except internal calibratable RC oscillator.When used as a clock pin,the pin can not be used as an I/O pin.When using internal calibratable RC oscillator as chip clock source,PB6 functions as an ordinary I/O pin. TOSC1:Timer Oscillator pin 1.Used only if internal calibratable RC oscillator is selected as chip clock source,and the asynchronous timer is enabled by the correct setting in ASSR.When the AS2 bit in ASSR is set (one)to enable asynchronous clocking of Timer/Counter1,pin PB6 is disconnected from the port,and becomes the input of the inverting oscillator amplifier.In this mode,a crystal oscillator is connected to this pin,and the pin can not be used as an I/O pin. If PB6 is used as a clock pin,DDB6,PORTB6 and PINB6 will all rea [PB7:XTAL2:TOSC2:PCINT7] XTAL2:Chip clock oscillator pin 2.Used as clock pin for all chip clock sources except internal calibratable RC oscillator and external clock.When used as a clock pin,the pin can not be used as an I/O pin.When using internal calibratable RC oscillator or external clock as chipclock sources,PB7 functions as an ordinary I/O pin. TOSC2:Timer Oscillator pin 2.Used only if internal calibratable RC oscillator is selected as chip clock source,and the asynchronous timer is enabled by the correct setting in ASSR.When the AS2 bit in ASSR is set (one)to enable asynchro- nous clocking of Timer/Counter2,pin PB7 is disconnected from the port,and becomes the inverting output of the oscillator amplifier.In this mode,a crystal oscillator is connected to this pin,and the pin can not be used as an I/O pin. If PB7 is used as a clock pin,DDB7,PORTB7 and PINB7 will all read [PD5:T1:OC0B:PCINT21] T1,Timer/Counter1 counter source. [PD6:AIN0:OC0A:PCINT22] AIN0,Analog Comparator Positive Input.Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the analog comparator. [PD7:AIN1:PCINT23] AIN1,Analog Comparator Negative Input.Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the analog comparator. [PB0:ICP1:CLKO:PCINT0] ICP1 -Input Capture Pin1:The PB0 pin can act as an input capture pin for Timer/Counter1. [PB1:OC1A:PCINT1] OC1A,Output compare match output:The PB1 pin can serve as an external output for the Timer/Counter1 compare match A.The PB1 pin has to be configured as an output (DDB1 set (one))to serve this function.The OC1A pin is also the output pin for the PWM mode timer function. [PB2:'SS:OC1B:PCINT2] SS:Slave Select input.When the SPI is enabled as a slave,this pin is configured as an input regardless of the setting of DDB4.As a slave,the SPI is activated when this pin is driven low.When the SPI is enabled as a master,the data direction of this pin is controlled by DDB4.When the pin is forced by the SPI to be an input,the pull-up can still be controlled by the PORTB4 bit. OC1B,Output compare match output:The PB2 pin can serve as an external output for the Timer/Counter1 compare match B.The PB2 pin has to be configured as an output (DDB2 set (one))to serve this function.The OC1B pin is also the output pin for the PWM mode timer fun [PB3:MOSI:OC2A:PCINT3] MOSI:SPI Master data output,slave data input for SPI channel.When the SPI is enabled as a slave,this pin is configured as an input regardless of the setting of DDB5.When the SPI is enabled as a master,the data direction of this pin is controlled by DDB5.When the pin is forced by the SPI to be an input,the pull-up can still be controlled by the PORTB bit. [PB4:MISO:PCINT4] MISO:Master data Input,Slave data Output pin for SPI channel.When the SPI is enabled as a master,this pin is configured as an input regardless of the setting of DDB6.When the SPI is enabled as a slave,the data direction of this pin is controlled by DDB6.When the pin is forced by the SPI to be an input,the pull-up can still be controlled by the PORTB6 bit. [PB5:SCK:PCINT5] SCK:Master clock output,slave clock input pin for SPI channel.When the SPI is enabled as a slave,this pin is configured as an input regardless of the setting of DDB7.When the SPI is enabled as a master,the data direction of this pin is controlled by DDB7.When the pin is forced by the SPI to be an input,the pull-up can still be controlled by the PORTB7 bit. [AVCC] [AREF] [GND] [PC0:ADC0:PCINT8] PC0 can also be used as ADC input Channel 0.Note that ADC input channel 0 uses analog ground. [PC1:ADC1:PCINT9] PC1 can also be used as ADC input Channel 1.Note that ADC input channel 1 uses analog ground. [PC2:ADC2:PCINT10] PC2 can also be used as ADC input Channel 2.Note that ADC input channel 2 uses analog ground. [PC3:ADC3:PCINT11] PC3 can also be used as ADC input Channel 3.Note that ADC input channel 3 uses analog ground. [PC4:ADC4:SDA:PCINT12] SDA,2-wire Serial Interface Data:When the TWEN bit in TWCR is set (one)to enable the 2-wire Serial Interface,pin PC1 is disconnected from the port and becomes the Serial Data I/O pin for the 2-wire Serial Interface.In this mode,there is a spike filter on the pin to suppress spikes shorter than 0 ns on the input signal,and the pin is driven by an open drain driver with slew-rate limitation. PC4 can also be used as ADC input Channel 4.Note that ADC input channel 4 uses digital ground. [PC5:ADC5:SCL:PCINT13] SCL,2-wire Serial Interface Clock:When the TWEN bit in TWCR is set (one)to enable the 2-wire Serial Interface,pin PC1 is disconnected from the port and becomes the Serial Clock I/O pin for the 2-wire Serial Interface.In this mode,there is a spike filter on the pin to suppress spikes shorter than 0 ns on the input signal,and the pin is driven by an open drain driver with slew-rate limitation. PC can also be used as ADC input Channel 5.Note that ADC input channel uses digital ground. AVRSimMemory8bit.SimMemory8bit 8192 512 1024 $100 0 NA $00 $3F $60 $FF $20 $FF NA 0xC6 0x010x020x040x080x100x200x400x80 NA 0xC5 0x010x020x040x08 NA 0xC4 0x010x020x040x080x100x200x400x80 NA 0xC2 0x010x020x040x080x100x200x400x80 NA 0xC1 0x010x020x040x080x100x200x400x80 NA 0xC0 0x010x020x040x080x100x200x400x80 NA 0xBD 0x020x040x080x100x200x400x80 NA 0xBC 0x010x040x080x100x200x400x80 NA 0xBB 0x010x020x040x080x100x200x400x80 NA 0xBA 0x010x020x040x080x100x200x400x80 NA 0xB9 0x010x020x080x100x200x400x80 NA 0xB8 0x010x020x040x080x100x200x400x80 NA 0xB6 0x010x020x040x080x100x200x40 NA 0xB4 0x010x020x040x080x100x200x400x80 NA 0xB3 0x010x020x040x080x100x200x400x80 NA 0xB2 0x010x020x040x080x100x200x400x80 NA 0xB1 0x010x020x040x080x400x80 NA 0xB0 0x010x020x100x200x400x80 NA 0x8B 0x010x020x040x080x100x200x400x80 NA 0x8A 0x010x020x040x080x100x200x400x80 NA 0x89 0x010x020x040x080x100x200x400x80 NA 0x88 0x010x020x040x080x100x200x400x80 NA 0x87 0x010x020x040x080x100x200x400x80 NA 0x86 0x010x020x040x080x100x200x400x80 NA 0x85 0x010x020x040x080x100x200x400x80 NA 0x84 0x010x020x040x080x100x200x400x80 NA 0x82 0x400x80 NA 0x81 0x010x020x040x080x100x400x80 NA 0x80 0x010x020x100x200x400x80 NA 0x7F 0x010x02 NA 0x7E 0x010x020x040x080x100x20 NA 0x7C 0x010x020x040x080x200x400x80 NA 0x7B 0x010x020x040x40 NA 0x7A 0x010x020x040x080x100x200x400x80 NA 0x79 0x010x020x040x080x100x200x400x80 NA 0x78 0x010x020x040x080x100x200x400x80 NA 0x70 0x010x020x04 NA 0x6F 0x010x020x040x20 NA 0x6E 0x010x020x04 NA 0x6D 0x010x020x040x080x100x200x400x80 NA 0x6C 0x010x020x040x080x100x200x40 NA 0x6B 0x010x020x040x080x100x200x400x80 NA 0x69 0x010x020x040x08 NA 0x68 0x010x020x04 NA 0x66 0x010x020x040x080x100x200x400x80 NA 0x64 0x010x020x040x080x200x400x80 NA 0x61 0x010x020x040x080x80 NA 0x60 0x010x020x040x080x100x200x400x80 0x3F 0x5F 0x010x020x040x080x100x200x400x80 0x3E 0x5E 0x04 0x010x020x04 0x3D 0x5D 0xFF 0x010x020x040x080x100x200x400x80 0x37 0x57 0x010x020x040x080x100x400x80 0x35 0x55 0x010x020x10 0x34 0x54 0x010x020x040x08 0x33 0x53 0x010x020x040x08 0x30 0x50 0x010x020x040x080x100x200x400x80 0x2E 0x4E 0x010x020x040x080x100x200x400x80 0x2D 0x4D 0x010x400x80 0x2c 0x4C 0x010x020x040x080x100x200x400x80 0x2B 0x4B 0x010x020x040x080x100x200x400x80 0x2A 0x4A 0x010x020x040x080x100x200x400x80 0x28 0x48 0x010x020x040x080x100x200x400x80 0x27 0x47 0x010x020x040x080x100x200x400x80 0x26 0x46 0x010x020x040x080x100x200x400x80 0x25 0x45 0x010x020x040x080x400x80 0x24 0x44 0x010x020x100x200x400x80 0x23 0x43 0x010x800x02 0x22 0x42 0x01 0x21 0x41 0x010x020x040x080x100x200x400x80 0x20 0x40 0x010x020x040x080x100x200x400x80 0x1F 0x3F 0x010x020x040x080x100x20 0x1E 0x3E 0x010x020x040x080x100x200x400x80 0x1D 0x3D 0x010x02 0x1C 0x3C 0x010x02 0x1B 0x3B 0x010x020x04 0x17 0x37 0x010x020x04 0x16 0x36 0x010x020x040x20 0x15 0x35 0x010x020x04 0x0B 0x2B 0x010x020x040x080x100x200x400x80 0x0A 0x2A 0x010x020x040x080x100x200x400x80 0x09 0x29 0x010x020x040x080x100x200x400x80 0x08 0x28 0x010x020x040x080x100x200x40 0x07 0x27 0x010x020x040x080x100x200x40 0x06 0x26 0x010x020x040x080x100x200x40 0x05 0x25 0x010x020x040x080x100x200x400x80 0x04 0x24 0x010x020x040x080x100x200x400x80 0x03 0x23 0x010x020x040x080x100x200x400x80 $C00 $FFF $0 $BFF 32 128 4 $0 $F80 $F80 256 8 $0 $F00 $F00 512 16 $0 $E00 $E00 1024 32 $0 $C00 $C00 V2E AVRSimCoreV2.SimCoreV2 [] [] [] 32 $00 $1B $1A $1D $1C $1F $1E 26 AVRSimInterrupt.SimInterrupt $000 RESET External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset $001 INT0 External Interrupt Request 0 $002 INT1 External Interrupt Request 1 $003 PCINT0 Pin Change Interrupt Request 0 $004 PCINT1 Pin Change Interrupt Request 0 $005 PCINT2 Pin Change Interrupt Request 1 $006 WDT Watchdog Time-out Interrupt $007 TIMER2 COMPA Timer/Counter2 Compare Match A $008 TIMER2 COMPB Timer/Counter2 Compare Match A $009 TIMER2 OVF Timer/Counter2 Overflow $00A TIMER1 CAPT Timer/Counter1 Capture Event $00B TIMER1 COMPA Timer/Counter1 Compare Match A $00C TIMER1 COMPB Timer/Counter1 Compare Match B $00D TIMER1 OVF Timer/Counter1 Overflow $00E TIMER0 COMPA TimerCounter0 Compare Match A $00F TIMER0 COMPB TimerCounter0 Compare Match B $010 TIMER0 OVF Timer/Couner0 Overflow $011 SPI, STC SPI Serial Transfer Complete $012 USART, RX USART Rx Complete $013 USART, UDRE USART, Data Register Empty $014 USART, TX USART Tx Complete $015 ADC ADC Conversion Complete $016 EE READY EEPROM Ready $017 ANALOG COMP Analog Comparator $018 TWI Two-wire Serial Interface $019 SPM Ready Store Program Memory Read [LOW:HIGH:EXTENDED] 8 CKDIV8 Divide clock by 8 0 CKOUT Clock output 1 SUT1 Select start-up time 1 SUT0 Select start-up time 0 CKSEL3 Select Clock Source 0 CKSEL2 Select Clock Source 0 CKSEL1 Select Clock Source 1 CKSEL0 Select Clock Source 0 57 0x80 0x00 Divide clock by 8 internally; [CKDIV8=0] 0x40 0x00 Clock output on PORTB0; [CKOUT=0] 0x3F 0x00 Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms; [CKSEL=0000 SUT=00] 0x3F 0x10 Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms; [CKSEL=0000 SUT=01] 0x3F 0x20 Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms; [CKSEL=0000 SUT=10] 0x3F 0x02 Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms; [CKSEL=0010 SUT=00] 0x3F 0x12 Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms; [CKSEL=0010 SUT=01] 0x3F 0x22 Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms; [CKSEL=0010 SUT=10]; default value 0x3F 0x03 Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms; [CKSEL=0011 SUT=00] 0x3F 0x13 Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms; [CKSEL=0011 SUT=01] 0x3F 0x23 Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms; [CKSEL=0011 SUT=10] 0x3F 0x04 Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 0 ms; [CKSEL=0100 SUT=00] 0x3F 0x14 Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4.1 ms; [CKSEL=0100 SUT=01] 0x3F 0x24 Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 65 ms; [CKSEL=0100 SUT=10] 0x3F 0x05 Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 0 ms; [CKSEL=0101 SUT=00] 0x3F 0x15 Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 4.1 ms; [CKSEL=0101 SUT=01] 0x3F 0x25 Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 65 ms; [CKSEL=0101 SUT=10] 0x3F 0x06 Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms;[CKSEL=0110 SUT=00] 0x3F 0x16 Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms; [CKSEL=0110 SUT=01] 0x3F 0x26 Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms; [CKSEL=0110 SUT=10] 0x3F 0x36 Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms;[CKSEL=0110 SUT=11] 0x3F 0x07 Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms; [CKSEL=0111 SUT=00] 0x3F 0x17 Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms; [CKSEL=0111 SUT=01] 0x3F 0x27 Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms;[CKSEL=0111 SUT=10] 0x3F 0x37 Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms; [CKSEL=0111 SUT=11] 0x3F 0x08 Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms; [CKSEL=1000 SUT=00] 0x3F 0x18 Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms; [CKSEL=1000 SUT=01] 0x3F 0x28 Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms; [CKSEL=1000 SUT=10] 0x3F 0x38 Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms; [CKSEL=1000 SUT=11] 0x3F 0x09 Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms; [CKSEL=1001 SUT=00] 0x3F 0x19 Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms; [CKSEL=1001 SUT=01] 0x3F 0x29 Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms; [CKSEL=1001 SUT=10] 0x3F 0x39 Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms; [CKSEL=1001 SUT=11] 0x3F 0x0A Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms; [CKSEL=1010 SUT=00] 0x3F 0x1A Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms; [CKSEL=1010 SUT=01] 0x3F 0x2A Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms; [CKSEL=1010 SUT=10] 0x3F 0x3A Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms; [CKSEL=1010 SUT=11] 0x3F 0x0B Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms; [CKSEL=1011 SUT=00] 0x3F 0x1B Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms; [CKSEL=1011 SUT=01] 0x3F 0x2B Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms; [CKSEL=1011 SUT=10] 0x3F 0x3B Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms; [CKSEL=1011 SUT=11] 0x3F 0x0C Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms; [CKSEL=1100 SUT=00] 0x3F 0x1C Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms; [CKSEL=1100 SUT=01] 0x3F 0x2C Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms; [CKSEL=1100 SUT=10] 0x3F 0x3C Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms; [CKSEL=1100 SUT=11] 0x3F 0x0D Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms; [CKSEL=1101 SUT=00] 0x3F 0x1D Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms; [CKSEL=1101 SUT=01] 0x3F 0x2D Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms; [CKSEL=1101 SUT=10] 0x3F 0x3D Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms; [CKSEL=1101 SUT=11] 0x3F 0x0E Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms; [CKSEL=1110 SUT=00] 0x3F 0x1E Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms; [CKSEL=1110 SUT=01] 0x3F 0x2E Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms; [CKSEL=1110 SUT=10] 0x3F 0x3E Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms; [CKSEL=1110 SUT=11] 0x3F 0x0F Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms; [CKSEL=1111 SUT=00] 0x3F 0x1F Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms; [CKSEL=1111 SUT=01] 0x3F 0x2F Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms; [CKSEL=1111 SUT=10] 0x3F 0x3F Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms; [CKSEL=1111 SUT=11] 8 RSTDISBL External reset disable 1 DWEN debugWIRE Enable 1 SPIEN Enable Serial programming and Data Downloading 0 WDTON Watchdog Timer Always On 1 EESAVE EEPROM memory is preserved through chip erase 1 BODLEVEL2 Brown-out Detector trigger level 1 BODLEVEL1 Brown-out Detector trigger level 1 BODLEVEL0 Brown-out Detector trigger level 1 9 0x80 0x00 Reset Disabled (Enable PC6 as i/o pin); [RSTDISBL=0] 0x40 0x00 Debug Wire enable; [DWEN=0] 0x20 0x00 Serial program downloading (SPI) enabled; [SPIEN=0] 0x10 0x00 Watch-dog Timer always on; [WDTON=0] 0x08 0x00 Preserve EEPROM memory through the Chip Erase cycle; [EESAVE=0] 0x07 0x04 Brown-out detection level at VCC=4.3 V; [BODLEVEL=100] 0x07 0x05 Brown-out detection level at VCC=2.7 V; [BODLEVEL=101] 0x07 0x06 Brown-out detection level at VCC=1.8 V; [BODLEVEL=110] 0x07 0x07 Brown-out detection disabled; [BODLEVEL=111] 3 BOOTSZ1 Select boot size 0 BOOTSZ0 Select boot size 0 BOOTRST Select reset vector 1 5 0x06 0x06 Boot Flash section size=128 words Boot start address=$0F80; [BOOTSZ=11] 0x06 0x04 Boot Flash section size=256 words Boot start address=$0F00; [BOOTSZ=10] 0x06 0x02 Boot Flash section size=512 words Boot start address=$0E00; [BOOTSZ=01] 0x06 0x00 Boot Flash section size=1024 words Boot start address=$0C00; [BOOTSZ=00] ; default value 0x01 0x00 Boot Reset vector Enabled (default address=$0000); [BOOTRST=0] [LB1 = 1 : LB2 = 1] No memory lock features enabled. [LB1 = 0 : LB2 = 1] Further programming of Flash and EEPROM is enabled. [LB1 = 0 : LB2 = 0] Same as previous, but verify is also disabled 6 11 0x03 0x03 Mode 1: No memory lock features enabled 0x03 0x02 Mode 2: Further programming disabled 0x03 0x00 Mode 3: Further programming and verification disabled 0x0C 0x0C Application Protection Mode 1: No lock on SPM and LPM in Application Section 0x0C 0x08 Application Protection Mode 2: SPM prohibited in Application Section 0x0C 0x00 Application Protection Mode 3: LPM and SPM prohibited in Application Section 0x0C 0x04 Application Protection Mode 4: LPM prohibited in Application Section 0x30 0x30 Boot Loader Protection Mode 1: No lock on SPM and LPM in Boot Loader Section 0x30 0x20 Boot Loader Protection Mode 2: SPM prohibited in Boot Loader Section 0x30 0x00 Boot Loader Protection Mode 3: LPM and SPM prohibited in Boot Loader Section 0x30 0x10 Boot Loader Protection Mode 4: LPM prohibited in Boot Loader Section LB1 Lock bit LB2 Lock bit BLB01 Boot Lock bit BLB02 Boot Lock bit BLB11 Boot lock bit BLB12 Boot lock bit 0xff,0xdf,0xff 0xff,0xdf,0xff 1,0x20,0x20,WARNING! These fuse settings will disable the ISP interface! 1,0x80,0x00,WARNING! Disabling external reset will make the ISP interface inaccessible! 1,0x40,0x00,WARNING! Enabling DEBUGWIRE will make the ISP interface inaccessible! 0,0x3F,0x03,WARNING! Using this clock option together with the CKDIV8 fuse bit will require a slow ISP speed ~2kHz. 0,0x3F,0x13,WARNING! Using this clock option together with the CKDIV8 fuse bit will require a slow ISP speed ~2kHz. 0,0x3F,0x23,WARNING! Using this clock option together with the CKDIV8 fuse bit will require a slow ISP speed ~2kHz. 1,0x20,0x20,WARNING! These fuse settings will disable the ISP interface! 1,0x80,0x00,WARNING! Disabling external reset will make the ISP interface inaccessible! 1,0x40,0x00,WARNING! Enabling DEBUGWIRE will make the ISP interface inaccessible! 0,0x3F,0x03,WARNING! Using this clock option together with the CKDIV8 fuse bit will require a slow ISP speed ~2kHz. 0,0x3F,0x13,WARNING! Using this clock option together with the CKDIV8 fuse bit will require a slow ISP speed ~2kHz. 0,0x3F,0x23,WARNING! Using this clock option together with the CKDIV8 fuse bit will require a slow ISP speed ~2kHz. 0x00,8.0 MHz 64 4 [USART0:TWI:TIMER_COUNTER_1:TIMER_COUNTER_2:AD_CONVERTER:ANALOG_COMPARATOR:PORTB:PORTC:PORTD:TIMER_COUNTER_0:EXTERNAL_INTERRUPT:SPI:CPU:WATCHDOG:EEPROM] [UDR0:UCSR0A:UCSR0B:UCSR0C:UBRR0H:UBRR0L] [UBRR0H:UBRR0L] io_com.bmp The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. The main features are: • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • High Resolution Baud Rate Generator • Supports Serial Frames with 5, 6, 7, 8 or 9 Data Bits and 1 or 2 Stop Bits • Odd or Even Parity Generation and Parity Check Supported by Hardware • Data OverRun Detection • Framing Error Detection • Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter • Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete • Multi-processor Communication Mode • Double Speed Asynchronous Communica UDR0 USART I/O Data Register The UDR0 register is actually two physically separate registers sharing the same I/O address. When writing to the register, the USART Transmit Data register is written. When reading from UDR0, the USART Receive Data register is read. NA 0xC6 io_com.bmp N UDR0-7 USART I/O Data Register bit 7 RW 0 UDR0-6 USART I/O Data Register bit 6 RW 0 UDR0-5 USART I/O Data Register bit 5 RW 0 UDR0-4 USART I/O Data Register bit 4 RW 0 UDR0-3 USART I/O Data Register bit 3 RW 0 UDR0-2 USART I/O Data Register bit 2 RW 0 UDR0-1 USART I/O Data Register bit 1 RW 0 UDR0-0 USART I/O Data Register bit 0 RW 0 UCSR0A USART Control and Status Register A NA 0xC0 io_flag.bmp Y RXC0 USART Receive Complete This bit is set (one) when a received character is transferred from the Receiver Shift register to UDR0. The bit is set regard-less of any detected framing errors. When the RXCIE bit in UCR is set, the USART Receive Complete interrupt will be executed when RXC is set(one). RXC is cleared by reading UDR0. When interrupt-driven data reception is used, the USART Receive Complete Interrupt routine must read UDRin order to clear RXC, otherwise a new interrupt will occur once the interrupt routine terminates. R 0 TXC0 USART Transmitt Complete This bit is set (one) when the entire character (including the stop bit) in the Transmit Shift register has been shifted out and no new data has been written to UDR0. This flag is especially useful in half-duplex communications interfaces, where a transmitting application must enter receive mode and free the communications bus immediately after completing the transmission. When the TXCIE bit in UCR is set, setting of TXC causes the USART Transmit Complete interrupt to be executed. TXC is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the TXC bit is cleared (zero) by writing a logical one to the b RW 0 UDRE0 USART Data Register Empty This bit is set (one) when a character written to UDRis transferred to the Transmit shift register. Setting of this bit indicates that the transmitter is ready to receive a new character for transmission. When the UDR0IE bit in UCR is set, the USART Transmit Complete interrupt to be executed as long as UDR0E is set. UDR0E is cleared by writing UDR0. When interrupt-driven data transmittal is used, the USART Data Register Empty Interrupt routine must write UDRin order to clear UDR0E, otherwise a new interrupt will occur once the interrupt routine terminates. UDR0E is set (one) during reset to indicate that the transmitter is re R 1 FE0 Framing Error This bit is set if a Framing Error condition is detected, i.e. when the stop bit of an incoming character is zero. The FE bit is cleared when the stop bit of received data is one. R 0 DOR0 Data overRun This bit is set if an Overrun condition is detected, i.e. when a character already present in the UDRregister is not read before the next character has been shifted into the Receiver Shift register. The OR bit is buffered, which means that it will be set once the valid data still in UDR0E is read. The OR bit is cleared (zero) when data is received and transferred to UDR0. R 0 UPE0 Parity Error This bit is set if the next character in the receive buffer had a Parity Error when received and the parity checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer (UDR0) is read. Always set this bit to zero when writing to UCSR0A. R 0 U2X0 Double the USART transmission speed This bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation. Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous communication. RW 0 MPCM0 Multi-processor Communication Mode This bit enables the Multi-processor Communication Mode. When the MPCM bit is written to one, all the incoming frames received by the USART receiver that do not contain address information will be ignored. The transmitter is unaffected by the MPCM setting. For more detailed information see “Multi-processor Communication Mode” on page 152. RW 0 UCSR0B USART Control and Status Register B NA 0xC1 io_flag.bmp Y RXCIE0 RX Complete Interrupt Enable Writing this bit to one enables interrupt on the RXC flag. A USART Receive Complete interrupt will be generated only if the RXCIE bit is written to one, the global interrupt flag in SREG is written to one and the RXC bit in UCSR0A is set. RW 0 TXCIE0 TX Complete Interrupt Enable Writing this bit to one enables interrupt on the TXC flag. A USART Transmit Complete interrupt will be generated only if the TXCIE bit is written to one, the global interrupt flag in SREG is written to one and the TXC bit in UCSR0A is set. RW 0 UDRIE0 USART Data register Empty Interrupt Enable Writing this bit to one enables interrupt on the UDR0E flag. A Data Register Empty interrupt will be generated only if the UDR0IE bit is written to one, the global interrupt flag in SREG is written to one and the UDR0E bit in UCSR0A is set. RW 1 RXEN0 Receiver Enable Writing this bit to one enables the USART receiver. The receiver will override normal port operation for the RxD pin when enabled. Disabling the receiver will flush the receive buffer invalidating the FE, DOR and PE flags. RW 0 TXEN0 Transmitter Enable Writing this bit to one enables the USART transmitter. The transmitter will override normal port operation for the TxD pin when enabled. The disabling of the transmitter (writing TXEN to zero) will not become effective until ongoing and pending transmissions are completed, i.e. when the transmit shift register and transmit buffer register does not contain data to be transmitted. When disabled, the transmitter will no longer override the TxD port. RW 0 UCSZ02 Character Size The UCSZ2 bits combined with the UCSZ1:0 bit in UCSR0C sets the number of data bits (character size) in a frame the receiver and transmitter use. RW 0 RXB80 Receive Data Bit 8 RXB8 is the 9th data bit of the received character when operating with serial frames with 9 data bits. Must be read before reading the low bits from UDR0. R 0 TXB80 Transmit Data Bit 8 TXB8 is the 9th data bit in the character to be transmitted when operating with serial frames with 9 data bits. Must be writ-ten before writing the low bits to UDR0. W 0 UCSR0C USART Control and Status Register C NA 0xC2 io_flag.bmp Y UMSEL01 UMSEL1 USART Mode Select RW 0 UMSEL00 UMSEL0 USART Mode Select RW 0 UPM01 Parity Mode Bit 1 This bit enable and set type of parity generation and check. If enabled, the transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value for the incoming data and compare it to the UPM0 setting. If a mismatch is detected, the PE flag in UCSR0A will be set. RW 0 UPM00 Parity Mode Bit 0 This bit enable and set type of parity generation and check. If enabled, the transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value for the incoming data and compare it to the UPM0 setting. If a mismatch is detected, the PE flag in UCSR0A will be set. RW 0 USBS0 Stop Bit Select 0: 1-bit. 1: 2-bit. RW 0 UCSZ01 UDORD0 Character Size Character Size: 0 0 0 = 5-bit. 0 0 1 = 6-bit. 0 1 0 = 7 bit. 0 1 1 = 8-bit. 1 1 1 = 9 bit. RW 0 UCSZ00 UCPHA0 Character Size Character Size: 0 0 0 = 5-bit. 0 0 1 = 6-bit. 0 1 0 = 7 bit. 0 1 1 = 8-bit. 1 1 1 = 9 bit. RW 1 UCPOL0 Clock Polarity This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOL bit sets the relationship between data output change and data input sample, and the synchronous clock (XCK). RW 0 UBRR0H USART Baud Rate Register High Byte This is a 12-bit register which contains the USART baud rate. The UBRR0H contains the 4 most significant bits, and the UBRR0L contains the 8 least significant bits of the USART baud rate. Ongoing transmissions by the transmitter and receiver will be corrupted if the baud rate is changed. Writing UBRR0L will trigger an immediate update of the baud rate prescaler. NA 0xC5 io_com.bmp N UBRR11 USART Baud Rate Register bit 11 RW 0 UBRR10 USART Baud Rate Register bit 10 RW 0 UBRR9 USART Baud Rate Register bit 9 RW 0 UBRR8 USART Baud Rate Register bit 8 RW 0 UBRR0L USART Baud Rate Register Low Byte This is a 12-bit register which contains the USART baud rate. The UBRR0H contains the 4 most significant bits, and the UBRR0L contains the 8 least significant bits of the USART baud rate. Ongoing transmissions by the transmitter and receiver will be corrupted if the baud rate is changed. Writing UBRR0L will trigger an immediate update of the baud rate prescaler. NA 0xC4 io_com.bmp N UBRR7 USART Baud Rate Register bit 7 RW 0 UBRR6 USART Baud Rate Register bit 6 RW 0 UBRR5 USART Baud Rate Register bit 5 RW 0 UBRR4 USART Baud Rate Register bit 4 RW 0 UBRR3 USART Baud Rate Register bit 3 RW 0 UBRR2 USART Baud Rate Register bit 2 RW 0 UBRR1 USART Baud Rate Register bit 1 RW 0 UBRR0 USART Baud Rate Register bit 0 RW 0 [TWAMR:TWBR:TWCR:TWSR:TWDR:TWAR] io_com.bmp TWI: Simple yet powerful and flexible communications interface, only two bus lines needed. Both master and slave operation supported. Device can operate as transmitter or receiver. 7-bit address space allows up to 128 different slave addresses. Multi-master arbitration support Up to 400 kHz data transfer speed Slew-rate limited output drivers Noise suppression circuitry rejects spikes on bus lines Fully programmable slave address with general call support Address recognition causes wake-up when AVR is in sleep mode The Two-Wire Serial Interface (TWI) is ideally suited to typical microcontroller applications. The TWI protocol allows the systems designer to interconnect up to 128 different devices using only two bidirectional bus lines, one for clock (SCL) andone for data (SDA). The only external hardware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines. All devices connected to the bus have individual addresses, and mechanisms for resolving bus contention are inherent in the TWI pr TWAMR TWI (Slave) Address Mask Register The TWAMR can be loaded with a 7-bit Salve Address mask. Each of the bits in TWAMR can mask (disable) the corresponding address bits in the TWI Address Register (TWAR). If the mask bit is set to one then the address match logic ingnores the compare between the incomming address bit and the corresponding bit in TWAR. NA 0xBD io_com.bmp Y TWAM6 TWAMR6 RW 0 TWAM5 TWAMR5 RW 0 TWAM4 TWAMR4 RW 0 TWAM3 TWAMR3 RW 0 TWAM2 TWAMR2 RW 0 TWAM1 TWAMR1 RW 0 TWAM0 TWAMR0 RW 0 TWBR TWI Bit Rate register TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency divider which generates the SCL clock frequency in the master modes. See “Bit Rate Generator Unit” on page 165 for calculating bit rates. NA 0xB8 io_com.bmp N TWBR7 RW 0 TWBR6 RW 0 TWBR5 RW 0 TWBR4 RW 0 TWBR3 RW 0 TWBR2 RW 0 TWBR1 RW 0 TWBR0 RW 0 TWCR TWI Control Register The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate a master access by applying a START condition to the bus, to generate a receiver acknowledge, to generate a stop condition, and to control halting of the bus while the data to be written to the bus are written to the TWDR. It also indicates a write collision if data is attempted written to TWDR while the register is inaccessible. NA 0xBC io_flag.bmp Y TWINT TWI Interrupt Flag This bit is set by hardware when the TWI has finished its current job and expects application software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the TWI interrupt vector. While the TWINT flag is set, the SCL low period is stretched. The TWINT flag must be cleared by software by writing a logic one to it. Note that this flag is not automatically cleared by hardware when executing the interrupt routine. Also note that clearing this flag starts the operation of the TWI, so all accesses to the TWI Address Register (TWAR), TWI Status Register (TWSR), and TWI Data Register (TWDR) must be complete before clearing this flag RW 0 TWEA TWI Enable Acknowledge Bit The TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is written to one, the ACK pulse is gener-ated on the TWI bus if the following conditions are met: 1. The device’s own slave address has been received. 2. A general call has been received, while the TWGCE bit in the TWAR is set. 3. A data byte has been received in master receiver or slave receiver mode. By writing the TWEA bit to zero, the device can be virtually disconnected from the 2-wire Serial Bus temporarily. Address recognition can then be resumed by writing the TWEA bit to one again RW 0 TWSTA TWI Start Condition Bit The application writes the TWSTA bit to one when it desires to become a master on the 2-wire Serial Bus. The TWI hard-ware checks if the bus is available, and generates a START condition on the bus if it is free. However, if the bus is not free, the TWI waits until a STOP condition is detected, and then generates a new START condition to claim the bus Master sta-tus. TWSTA is cleared by the TWI hardware when the START condition has been transmitted. RW 0 TWSTO TWI Stop Condition Bit Writing the TWSTO bit to one in master mode will generate a STOP condition on the 2-wire Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit is cleared automatically. In slave mode, setting the TWSTO bit can be used to recover from an error condition. This will not generate a STOP condition, but the TWI returns to a well-defined unaddressed slave mode and releases the SCL and SDA lines to a high impedance state. RW 0 TWWC TWI Write Collition Flag The TWWC bit is set when attempting to write to the TWI Data Register - TWDR when TWINT is low. This flag is cleared by writing the TWDR register when TWINT is high. RW 0 TWEN TWI Enable Bit The TWEN bit enables TWI operation and activates the TWI interface. When TWEN is written to one, the TWI takes control over the I/O pins connected to the SCL and SDA pins, enabling the slew-rate limiters and spike filters. If this bit is written to zero, the TWI is switched off and all TWI transmissions are terminated, regardless of any ongoing operation. RW 0 TWIE TWI Interrupt Enable When this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request will be activated for as long as the TWINT flag is high. RW 0 TWSR TWI Status Register NA 0xB9 io_flag.bmp Y TWS7 TWI Status Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient c RW 0 TWS6 TWI Status Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient co RW 0 TWS5 TWI Status Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient c RW 0 TWS4 TWI Status Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient co RW 0 TWS3 TWI Status Bits 7..3: These 5 bits reflect the status of the TWI logic and the 2-Wire Serial Bus. The different status codes are described later in this chapter. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should consider masking the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. If the prescaler setting remains unchanged in the application, the prescaler bits need not be masked. Instead, bit 1:0 in the values that TWSR is compared to can be modified to match the prescaler setting. This will yield more efficient co RW 0 TWPS1 TWI Prescaler Bits 1..0: These bits can be read and written, and control the bit rate prescaler. See “Bit Rate Generator Unit” on page 165 for calculating bit rates. RW 0 TWPS0 TWI Prescaler Bits 1..0: These bits can be read and written, and control the bit rate prescaler. See “Bit Rate Generator Unit” on page 165 for calculating bit rates. RW 0 TWDR TWI Data register In transmit mode, TWDR contains the next byte to be transmitted. In receive mode, the TWDR contains the last byte received. It is writable while the TWI is not in the process of shifting a byte. This occurs when the TWI interrupt flag (TWINT) is set by hardware. Note that the data register cannot be initialized by the user before the first interrupt occurs. The data in TWDR remains stable as long as TWINT is set. While data is shifted out, data on the bus is simultaneously shifted in. TWDR always contains the last byte present on the bus, except after a wake up from a sleep mode by the TWI interrupt. In this case, the contents of TWDR is undefined. In the case of a lost bus arbitration, no data is lost in the transi-tion from Master to Slave. Handling of the ACK bit is controlled automatically by the TWI logic, the CPU cannot access the ACK bit directl NA 0xBB io_com.bmp N TWD7 TWI Data Register Bit 7 RW 1 TWD6 TWI Data Register Bit 6 RW 1 TWD5 TWI Data Register Bit 5 RW 1 TWD4 TWI Data Register Bit 4 RW 1 TWD3 TWI Data Register Bit 3 RW 1 TWD2 TWI Data Register Bit 2 RW 1 TWD1 TWI Data Register Bit 1 RW 1 TWD0 TWI Data Register Bit 0 RW 1 TWAR TWI (Slave) Address register The TWAR should be loaded with the 7-bit slave address (in the seven most significant bits of TWAR) to which the TWI will respond when programmed as a slave transmitter or receiver, and not needed in the master modes. In multimaster sys-tems, TWAR must be set in masters which can be addressed as slaves by other masters. The LSB of TWAR is used to enable recognition of the general call address ($00). There is an associated address compar-ator that looks for the slave address (or general call address if enabled) in the received serial address. If a match is found, an interrupt request is genera NA 0xBA io_com.bmp Y TWA6 TWI (Slave) Address register Bit 6 RW 0 TWA5 TWI (Slave) Address register Bit 5 RW 0 TWA4 TWI (Slave) Address register Bit 4 RW 0 TWA3 TWI (Slave) Address register Bit 3 RW 0 TWA2 TWI (Slave) Address register Bit 2 RW 0 TWA1 TWI (Slave) Address register Bit 1 RW 0 TWA0 TWI (Slave) Address register Bit 0 RW 0 TWGCE TWI General Call Recognition Enable Bit RW 0 [TIMSK1:TIFR1:TCCR1A:TCCR1B:TCCR1C:TCNT1H:TCNT1L:OCR1AH:OCR1AL:OCR1BH:OCR1BL:ICR1H:ICR1L:GTCCR] [TCNT1H:TCNT1L];[OCR1AH:OCR1AL];[OCR1BH:OCR1BL];[ICR1H:ICR1L] io_timer.bmp t16pwm1_12.xml TIMSK1 Timer/Counter Interrupt Mask Register NA 0x6F io_flag.bmp Y ICIE1 Timer/Counter1 Input Capture Interrupt Enable When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on pin 31, ICP, i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR. RW 0 OCIE1B Timer/Counter1 Output CompareB Match Interrupt Enable When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter1 occurs, i.e., when the OCF1B bit is set in the Timer/Counter Interrupt Flag Register - TIFR. R 0 OCIE1A Timer/Counter1 Output CompareA Match Interrupt Enable When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a CompareA match in Timer/Counter1 occurs, i.e., when the OCF1A bit is set in the Timer/Counter Interrupt Flag Register - TIFR. RW 0 TOIE1 Timer/Counter1 Overflow Interrupt Enable When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $006) is executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR. RW 0 TIFR1 Timer/Counter Interrupt Flag register 0x16 0x36 io_flag.bmp Y ICF1 Input Capture Flag 1 The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to the input capture register - ICR1. ICF1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF1 is cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable), and ICF1 are set (one), the Timer/Counter1 Capture Interrupt is executed. RW 0 OCF1B Output Compare Flag 1B The OCF1B bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1B - Output Compare Register 1B. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1B (Timer/Counter1 Compare match InterruptB Enable), and the OCF1B are set (one), the Timer/Counter1 Compare B match Interrupt is executed. RW 0 OCF1A Output Compare Flag 1A The OCF1A bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare match InterruptA Enable), and the OCF1A are set (one), the Timer/Counter1 Compare A match Interrupt is executed. RW 0 TOV1 Timer/Counter1 Overflow Flag The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the cor-responding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter1 changes counting direction at $0000. RW 0 TCCR1A Timer/Counter1 Control Register A NA 0x80 io_flag.bmp Y COM1A1 Compare Output Mode 1A, bit 1 The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA. This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10. RW 0 COM1A0 Comparet Ouput Mode 1A, bit 0 The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA. This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 10. RW 0 COM1B1 Compare Output Mode 1B, bit 1 The COM1B1 and COM1B0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin. RW 0 COM1B0 Compare Output Mode 1B, bit 0 The COM1B1 and COM1B0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1B - Output CompareB. This is an alternative function to an I/O port, and the corre-sponding direction control bit must be set (one) to control an output pin. RW 0 WGM11 Waveform Generation Mode Combined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table. RW 0 WGM10 Waveform Generation Mode Combined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table. RW 0 TCCR1B Timer/Counter1 Control Register B NA 0x81 io_flag.bmp Y ICNC1 Input Capture 1 Noise Canceler When the ICNC1 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the ICP - input capture pin - as specified. When the ICNC1 bit is set (one), four successive samples are measures on the ICP - input capture pin, and all samples must be high/low according to the input capture trigger specification in the ICES1 bit. The actual sampling frequency is XTAL clock frequency. RW 0 ICES1 Input Capture 1 Edge Select While the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the falling edge of the input capture pin - ICP. While the ICES1 bit is set (one), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the rising edge of the input capture pin - ICP. RW 0 WGM13 Waveform Generation Mode Combined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table. RW 0 WGM12 Waveform Generation Mode Combined with the WGM13:2 bits found in the TCCR1B register,these bits control the counting sequence of the counter, the source for maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter),Clear Timer on Compare match (CTC)mode,and three types of Pulse Width Modulation (PWM)modes. PLease refer to the manual for a Mode Bit Description Table. RW 0 CS12 Prescaler source of Timer/Counter 1 Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge. RW 0 CS11 Prescaler source of Timer/Counter 1 Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge. RW 0 CS10 Prescaler source of Timer/Counter 1 Select Prescaling Clock Source of Timer/Counter1. (0:0:0) = Stop. (0:0:1) = CK. (0:1:0) = CK / 8. (0:1:1) = CK / 64. (1:0:0) = CK / 256. (1:0:1) = CK / 1024. (1:1:0) = External Pin T1, falling edge. (1:1:1) = External Pin 1, rising edge. RW 0 TCCR1C Timer/Counter1 Control Register C NA 0x82 io_flag.bmp Y FOC1A RW 0 FOC1B RW 0 TCNT1H Timer/Counter1 High Byte This 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR1A, OCR1B and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt rou NA 0x85 io_timer.bmp N TCNT1H7 Timer/Counter1 High Byte bit 7 RW 0 TCNT1H6 Timer/Counter1 High Byte bit 6 RW 0 TCNT1H5 Timer/Counter1 High Byte bit 5 RW 0 TCNT1H4 Timer/Counter1 High Byte bit 4 RW 0 TCNT1H3 Timer/Counter1 High Byte bit 3 RW 0 TCNT1H2 Timer/Counter1 High Byte bit 2 RW 0 TCNT1H1 Timer/Counter1 High Byte bit 1 RW 0 TCNT1H0 Timer/Counter1 High Byte bit 0 RW 0 TCNT1L Timer/Counter1 Low Byte This 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR1A, OCR1B and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interru NA 0x84 io_timer.bmp N TCNT1L7 Timer/Counter1 Low Byte bit 7 RW 0 TCNT1L6 Timer/Counter1 Low Byte bit 6 RW 0 TCNT1L5 Timer/Counter1 Low Byte bit 5 RW 0 TCNT1L4 Timer/Counter1 Low Byte bit 4 RW 0 TCNT1L3 Timer/Counter1 Low Byte bit 3 RW 0 TCNT1L2 Timer/Counter1 Low Byte bit 2 RW 0 TCNT1L1 Timer/Counter1 Low Byte bit 1 RW 0 TCNT1L0 Timer/Counter1 Low Byte bit 0 RW 0 OCR1AH Timer/Counter1 Outbut Compare Register High Byte The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interru NA 0x89 io_timer.bmp N OCR1AH7 Timer/Counter1 Outbut Compare Register High Byte bit 7 RW 0 OCR1AH6 Timer/Counter1 Outbut Compare Register High Byte bit 6 RW 0 OCR1AH5 Timer/Counter1 Outbut Compare Register High Byte bit 5 RW 0 OCR1AH4 Timer/Counter1 Outbut Compare Register High Byte bit 4 RW 0 OCR1AH3 Timer/Counter1 Outbut Compare Register High Byte bit 3 RW 0 OCR1AH2 Timer/Counter1 Outbut Compare Register High Byte bit 2 RW 0 OCR1AH1 Timer/Counter1 Outbut Compare Register High Byte bit 1 RW 0 OCR1AH0 Timer/Counter1 Outbut Compare Register High Byte bit 0 RW 0 OCR1AL Timer/Counter1 Outbut Compare Register Low Byte The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interru NA 0x88 io_timer.bmp N OCR1AL7 Timer/Counter1 Outbut Compare Register Low Byte Bit 7 RW 0 OCR1AL6 Timer/Counter1 Outbut Compare Register Low Byte Bit 6 RW 0 OCR1AL5 Timer/Counter1 Outbut Compare Register Low Byte Bit 5 RW 0 OCR1AL4 Timer/Counter1 Outbut Compare Register Low Byte Bit 4 RW 0 OCR1AL3 Timer/Counter1 Outbut Compare Register Low Byte Bit 3 RW 0 OCR1AL2 Timer/Counter1 Outbut Compare Register Low Byte Bit 2 RW 0 OCR1AL1 Timer/Counter1 Outbut Compare Register Low Byte Bit 1 RW 0 OCR1AL0 Timer/Counter1 Outbut Compare Register Low Byte Bit 0 RW 0 OCR1BH Timer/Counter1 Output Compare Register High Byte The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt ro NA 0x8B io_timer.bmp N OCR1BH7 Timer/Counter1 Output Compare Register High Byte bit 7 RW 0 OCR1BH6 Timer/Counter1 Output Compare Register High Byte bit 6 RW 0 OCR1BH5 Timer/Counter1 Output Compare Register High Byte bit 5 RW 0 OCR1BH4 Timer/Counter1 Output Compare Register High Byte bit 4 RW 0 OCR1BH3 Timer/Counter1 Output Compare Register High Byte bit 3 RW 0 OCR1BH2 Timer/Counter1 Output Compare Register High Byte bit 2 RW 0 OCR1BH1 Timer/Counter1 Output Compare Register High Byte bit 1 RW 0 OCR1BH0 Timer/Counter1 Output Compare Register High Byte bit 0 RW 0 OCR1BL Timer/Counter1 Output Compare Register Low Byte The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt rout NA 0x8A io_timer.bmp N OCR1BL7 Timer/Counter1 Output Compare Register Low Byte bit 7 R 0 OCR1BL6 Timer/Counter1 Output Compare Register Low Byte bit 6 RW 0 OCR1BL5 Timer/Counter1 Output Compare Register Low Byte bit 5 RW 0 OCR1BL4 Timer/Counter1 Output Compare Register Low Byte bit 4 RW 0 OCR1BL3 Timer/Counter1 Output Compare Register Low Byte bit 3 RW 0 OCR1BL2 Timer/Counter1 Output Compare Register Low Byte bit 2 RW 0 OCR1BL1 Timer/Counter1 Output Compare Register Low Byte bit 1 RW 0 OCR1BL0 Timer/Counter1 Output Compare Register Low Byte bit 0 RW 0 ICR1H Timer/Counter1 Input Capture Register High Byte The input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES1) of the signal at the input capture pin -ICP - is detected, the current value of the Timer/Counter1 is transferred to the Input Capture Register - ICR1. At the same time, the input capture flag - ICF1 - is set (one). Since the Input Capture Register - ICR1 - is a 16-bit register, a temporary register TEMP is used when ICR1 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR1L, the data is sent to the CPU and the data of the high byte ICR1H is placed in the TEMP register. When the CPU reads the data in the high byte ICR1H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR1L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT1, OCR1A and OCR1B. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt NA 0x87 io_timer.bmp N ICR1H7 Timer/Counter1 Input Capture Register High Byte bit 7 RW 0 ICR1H6 Timer/Counter1 Input Capture Register High Byte bit 6 R 0 ICR1H5 Timer/Counter1 Input Capture Register High Byte bit 5 R 0 ICR1H4 Timer/Counter1 Input Capture Register High Byte bit 4 R 0 ICR1H3 Timer/Counter1 Input Capture Register High Byte bit 3 R 0 ICR1H2 Timer/Counter1 Input Capture Register High Byte bit 2 R 0 ICR1H1 Timer/Counter1 Input Capture Register High Byte bit 1 R 0 ICR1H0 Timer/Counter1 Input Capture Register High Byte bit 0 R 0 ICR1L Timer/Counter1 Input Capture Register Low Byte The input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES1) of the signal at the input capture pin -ICP - is detected, the current value of the Timer/Counter1 is transferred to the Input Capture Register - ICR1. At the same time, the input capture flag - ICF1 - is set (one). Since the Input Capture Register - ICR1 - is a 16-bit register, a temporary register TEMP is used when ICR1 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR1L, the data is sent to the CPU and the data of the high byte ICR1H is placed in the TEMP register. When the CPU reads the data in the high byte ICR1H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR1L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT1, OCR1A and OCR1B. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within inter NA 0x86 io_timer.bmp N ICR1L7 Timer/Counter1 Input Capture Register Low Byte bit 7 R 0 ICR1L6 Timer/Counter1 Input Capture Register Low Byte bit 6 R 0 ICR1L5 Timer/Counter1 Input Capture Register Low Byte bit 5 R 0 ICR1L4 Timer/Counter1 Input Capture Register Low Byte bit 4 R 0 ICR1L3 Timer/Counter1 Input Capture Register Low Byte bit 3 R 0 ICR1L2 Timer/Counter1 Input Capture Register Low Byte bit 2 R 0 ICR1L1 Timer/Counter1 Input Capture Register Low Byte bit 1 R 0 ICR1L0 Timer/Counter1 Input Capture Register Low Byte bit 0 R 0 GTCCR General Timer/Counter Control Register 0x23 0x43 io_flag.bmp Y TSM Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSR2 and PSR10 bits is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSR2 and PSR10 bits are cleared by hardware, and the Timer/Counters start counting simultaneous RW 0 PSRSYNC Prescaler Reset Timer/Counter1 and Timer/Counter0 When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. RW 0 [TIMSK2:TIFR2:TCCR2A:TCCR2B:TCNT2:OCR2A:OCR2B:ASSR:GTCCR] io_timer.bmp At8pwm2_07 The 8-bit Timer/Counter2 can select clock source from CK, prescaled CK, or external crystal input TOSC1. It can also be stopped as described in the section “Timer/Counter2 Control Register - TCCR2”. The status flags (overflow and compare match) are found in the Timer/Counter Interrupt Flag Register - TIFR. Control signals are found in the Timer/Counter Control Register TCCR2. The interrupt enable/disable settings are found in “The Timer/Counter Interrupt Mask Register - TIMSK”. When Timer/Counter2 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. This module features a high resolution and a high accuracy usage with the lower prescaling opportunities. Similarly, the high prescaling opportunities make this unit useful for lower speed functions or exact timing functions with infrequent actions. Timer/Counter2 can also be used as an 8-bit Pulse Width Modulator. In this mode, Timer/Counter2 and the output compare register serve as a glitch-free, stand-alone PWM with centered puls TIMSK2 Timer/Counter Interrupt Mask register NA 0x70 io_flag.bmp Y OCIE2B Timer/Counter2 Output Compare Match B Interrupt Enable When the OCIE2B bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match B interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter2 occurs, i.e., when the OCF2B bit is set in the Timer/Counter 2 Interrupt Flag Register – TIFR2. RW 0 OCIE2A Timer/Counter2 Output Compare Match A Interrupt Enable When the OCIE2A bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match A interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter2 occurs, i.e., when the OCF2A bit is set in the Timer/Counter 2 Interrupt Flag Register – TIFR2. RW 0 TOIE2 TOIE2A Timer/Counter2 Overflow Interrupt Enable When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is set in the Timer/Counter2 Interrupt Flag Register – TIFR2. RW 0 TIFR2 Timer/Counter Interrupt Flag Register 0x17 0x37 io_flag.bmp Y OCF2B Output Compare Flag 2B The OCF2B bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2B – Output Compare Register2. OCF2B is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF2B is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2B (Timer/Counter2 Compare match Interrupt Enable), and OCF2B are set (one), the Timer/Counter2 Compare match Interrupt is executed. RW 0 OCF2A Output Compare Flag 2A The OCF2A bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2A – Output Compare Register2. OCF2A is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF2A is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2A (Timer/Counter2 Compare match Interrupt Enable), and OCF2A are set (one), the Timer/Counter2 Compare match Interrupt is executed. RW 0 TOV2 Timer/Counter2 Overflow Flag The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE2A (Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter2 changes counting direction at 0x00. RW 0 TCCR2A Timer/Counter2 Control Register A NA 0xB0 io_flag.bmp Y COM2A1 Compare Output Mode bit 1 The COM21 and COM20 control bits determine any output pin action following a compare match in Timer/Counter2. Output pin actions affect pin PD7(OC2). This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. (COM21:COM20) description: (0:0) = Timer/Counter disconnected from output pin OC2. (0:1) = Toggle the OC2 output line. (1:0) = Clear the OC2 output line (to zero). (1:1) = Set the OC2 output line (to one). Note: In PWM mode, these bits have a different function RW 0 COM2A0 Compare Output Mode bit 1 The COM21 and COM20 control bits determine any output pin action following a compare match in Timer/Counter2. Output pin actions affect pin PD7(OC2). This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. (COM21:COM20) description: (0:0) = Timer/Counter disconnected from output pin OC2. (0:1) = Toggle the OC2 output line. (1:0) = Clear the OC2 output line (to zero). (1:1) = Set the OC2 output line (to one). Note: In PWM mode, these bits have a different function RW 0 COM2B1 Compare Output Mode bit 1 The COM21 and COM20 control bits determine any output pin action following a compare match in Timer/Counter2. Output pin actions affect pin PD7(OC2). This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. (COM21:COM20) description: (0:0) = Timer/Counter disconnected from output pin OC2. (0:1) = Toggle the OC2 output line. (1:0) = Clear the OC2 output line (to zero). (1:1) = Set the OC2 output line (to one). Note: In PWM mode, these bits have a different function RW 0 COM2B0 Compare Output Mode bit 0 The COM21 and COM20 control bits determine any output pin action following a compare match in Timer/Counter2. Output pin actions affect pin PD7(OC2). This is an alternative function to an I/O port, and the corresponding direction control bit must be set (one) to control an output pin. (COM21:COM20) description: (0:0) = Timer/Counter disconnected from output pin OC2. (0:1) = Toggle the OC2 output line. (1:0) = Clear the OC2 output line (to zero). (1:1) = Set the OC2 output line (to one). Note: In PWM mode, these bits have a different functio RW 0 WGM21 Waveform Genration Mode These bits control the counting sequence of the counter,the source for hte maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter), Clear Timer on Compare match (CTC)mode,and two types of Pulse Width Modulation (PWM)modes. Please refer to the manual for more information. RW 0 WGM20 Waveform Genration Mode These bits control the counting sequence of the counter,the source for hte maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter), Clear Timer on Compare match (CTC)mode,and two types of Pulse Width Modulation (PWM)modes. Please refer to the manual for more information. RW 0 TCCR2B Timer/Counter2 Control Register B NA 0xB1 io_flag.bmp Y FOC2A Force Output Compare A Writing a logical one to this bit, forces a change in the compare match output pin PD7 (OC2) according to the values already set in COM21 and COM20. If the COM21 and COM20 bits are written in the same cycle as FOC2, the new settings will not take effect until next compare match or forced output compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM21 and COM20 happens as if a Compare Match had occurred, but no interrupt is generated, and the Timer/Counter will not be cleared even if CTC2 is set. The corresponding I/O pin must be set as an output pin for the FOC2 bit to have effect on the pin. The FOC2 bit will always be read as zero. Setting the FOC2 bit has no effect in PWM mode RW 0 FOC2B Force Output Compare B Writing a logical one to this bit, forces a change in the compare match output pin PD7 (OC2) according to the values already set in COM21 and COM20. If the COM21 and COM20 bits are written in the same cycle as FOC2, the new settings will not take effect until next compare match or forced output compare match occurs. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in the timer. The automatic action programmed in COM21 and COM20 happens as if a Compare Match had occurred, but no interrupt is generated, and the Timer/Counter will not be cleared even if CTC2 is set. The corresponding I/O pin must be set as an output pin for the FOC2 bit to have effect on the pin. The FOC2 bit will always be read as zero. Setting the FOC2 bit has no effect in PWM mode RW 0 WGM22 Waveform Generation Mode These bits control the counting sequence of the counter,the source for hte maximum (TOP)counter value,and what type of waveform generation to be used.Modes of operation supported by the timer/counter unit are:Normal mode (counter), Clear Timer on Compare match (CTC)mode,and two types of Pulse Width Modulation (PWM)modes. Please refer to the manual for more information. RW 0 CS22 Clock Select bit 2 The Clock Select bits 2,1, and 0 define the prescaling source of Timer/Counter2. (CS22:CS21:CS20) Description. (0:0:0) Timer/Counter2 is stopped. (0:0:1) PCK2. (0:1:0) PCK2/8. (0:1:1) PCK2/32. (1:0:0) PCK2/64. (1:0:1) PCK2/128. (1:1:0) PCK2/256. (1:1:1) PCK2/1024. The Stop condition provides a Timer Enable/Disable function. The prescaled modes are scaled directly from the PCK2 clock. RW 0 CS21 Clock Select bit 1 The Clock Select bits 2,1, and 0 define the prescaling source of Timer/Counter2. (CS22:CS21:CS20) Description. (0:0:0) Timer/Counter2 is stopped. (0:0:1) PCK2. (0:1:0) PCK2/8. (0:1:1) PCK2/32. (1:0:0) PCK2/64. (1:0:1) PCK2/128. (1:1:0) PCK2/256. (1:1:1) PCK2/1024. The Stop condition provides a Timer Enable/Disable function. The prescaled modes are scaled directly from the PCK2 clock. RW 0 CS20 Clock Select bit 0 The Clock Select bits 2,1, and 0 define the prescaling source of Timer/Counter2. (CS22:CS21:CS20) Description. (0:0:0) Timer/Counter2 is stopped. (0:0:1) PCK2. (0:1:0) PCK2/8. (0:1:1) PCK2/32. (1:0:0) PCK2/64. (1:0:1) PCK2/128. (1:1:0) PCK2/256. (1:1:1) PCK2/1024. The Stop condition provides a Timer Enable/Disable function. The prescaled modes are scaled directly from the PCK2 clock. RW 0 TCNT2 Timer/Counter2 This 8-bit register contains the value of Timer/Counter2. Timer/Counters2 is implemented as an up or up/down (in PWM mode) counter with read and write access. If the Timer/Counter2iswritten to and a clocksourceisselected,it continues counting in the timer clock cycle following the write operation. NA 0xB2 io_timer.bmp N TCNT2-7 Timer/Counter 2 bit 7 RW 0 TCNT2-6 Timer/Counter 2 bit 6 RW 0 TCNT2-5 Timer/Counter 2 bit 5 RW 0 TCNT2-4 Timer/Counter 2 bit 4 RW 0 TCNT2-3 Timer/Counter 2 bit 3 RW 0 TCNT2-2 Timer/Counter 2 bit 2 RW 0 TCNT2-1 Timer/Counter 2 bit 1 RW 0 TCNT2-0 Timer/Counter 2 bit 0 RW 0 OCR2B Timer/Counter2 Output Compare Register B The output compare register is an 8-bit read/write register. The Timer/Counter Output Compare Register contains the data to be continuously compared with Timer/Counter2. Actions on compare matches are specified in TCCR2. A compare match does only occur if Timer/Counter2 counts to the OCR2 value. A software write that sets TCNT2 and OCR2 to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Timer/Counter2 in PWM Mode When PWM mode is selected, the Timer/Counter2 either wraps (overflows) when it reaches $FF or it acts as an up/down counter. If the up/down mode is selected, the Timer/Counter2 and the Output Compare Register - OCR2 form an 8-bit, free-running, glitch-free, and phase correct PWM with outputs on the PD7(OC2) pin. If the overflow mode is selected, the Timer/Counter2 and the Output Compare Register - OCR2 form an 8-bit, free-running, and glitch-free PWM, operating with twice the speed of the up/down counting mode. PWM Modes (Up/Down and Overflow). The two different PWM modes are selected by the CTC2 bit in the Timer/Counter Control Register - TCCR2. If CTC2 is cleared and PWM mode is selected, the Timer/Counter acts as an up/down counter, counting up from $00 to $FF, where it turns and counts down again to zero before the cycle is repeated. When the counter value matches the con-tents of the Output Compare Register, the PD7(OC2) pin is set or cleared according to the settings of the COM21/COM20 bits in the Timer/Counter Control Register TCCR2. If CTC2 is set and PWM mode is selected, the Timer/Counters will wrap and start counting from $00 after reaching $FF. The PD7(OC2) pin will be set or cleared according to the settings of COM21/COM20 on a Timer/Counter overflow or when the counter value matches the contents of the Output Compare Register. Note that in PWM mode, the value to be written to the Output Compare Register is first transferred to a temporary location, and then latched into OCR2 when the Timer/Counter reaches $FF. This prevents the occurrence of odd-length PWM pulses (glitches) in the event of an unsynchronized OCR2 write. (CTC2:COM21:COM20) Effect on Compare Pin Frequency: (0:0:0) = Not connected. (0:0:1) = Not connected. (0:1:0) = Cleared on compare match, up-counting. Set on compare match, down-counting (non-inverted PWM). f TCK0/2 /510. (0:1:1) = Cleared on compare match, down-counting. Set on compare match, up-counting (inverted PWM). f TCK0/2 /510. (1:0:0) = Not connected. (1:0:1) = Not connected. (1:1:0) = Cleared on compare match, set on overflow. f TCK0/2 /256. (1:1:1) = Set on compare match, cleared on overflow. f TCK0/ NA 0xB4 io_timer.bmp N OCR2-7 Timer/Counter2 Output Compare Register Bit 7 RW 0 OCR2-6 Timer/Counter2 Output Compare Register Bit 6 RW 0 OCR2-5 Timer/Counter2 Output Compare Register Bit 5 RW 0 OCR2-4 Timer/Counter2 Output Compare Register Bit 4 RW 0 OCR2-3 Timer/Counter2 Output Compare Register Bit 3 RW 0 OCR2-2 Timer/Counter2 Output Compare Register Bit 2 RW 0 OCR2-1 Timer/Counter2 Output Compare Register Bit 1 RW 0 OCR2-0 Timer/Counter2 Output Compare Register Bit 0 RW 0 OCR2A Timer/Counter2 Output Compare Register A The output compare register is an 8-bit read/write register. The Timer/Counter Output Compare Register contains the data to be continuously compared with Timer/Counter2. Actions on compare matches are specified in TCCR2. A compare match does only occur if Timer/Counter2 counts to the OCR2 value. A software write that sets TCNT2 and OCR2 to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Timer/Counter2 in PWM Mode When PWM mode is selected, the Timer/Counter2 either wraps (overflows) when it reaches $FF or it acts as an up/down counter. If the up/down mode is selected, the Timer/Counter2 and the Output Compare Register - OCR2 form an 8-bit, free-running, glitch-free, and phase correct PWM with outputs on the PD7(OC2) pin. If the overflow mode is selected, the Timer/Counter2 and the Output Compare Register - OCR2 form an 8-bit, free-running, and glitch-free PWM, operating with twice the speed of the up/down counting mode. PWM Modes (Up/Down and Overflow). The two different PWM modes are selected by the CTC2 bit in the Timer/Counter Control Register - TCCR2. If CTC2 is cleared and PWM mode is selected, the Timer/Counter acts as an up/down counter, counting up from $00 to $FF, where it turns and counts down again to zero before the cycle is repeated. When the counter value matches the con-tents of the Output Compare Register, the PD7(OC2) pin is set or cleared according to the settings of the COM21/COM20 bits in the Timer/Counter Control Register TCCR2. If CTC2 is set and PWM mode is selected, the Timer/Counters will wrap and start counting from $00 after reaching $FF. The PD7(OC2) pin will be set or cleared according to the settings of COM21/COM20 on a Timer/Counter overflow or when the counter value matches the contents of the Output Compare Register. Note that in PWM mode, the value to be written to the Output Compare Register is first transferred to a temporary location, and then latched into OCR2 when the Timer/Counter reaches $FF. This prevents the occurrence of odd-length PWM pulses (glitches) in the event of an unsynchronized OCR2 write. (CTC2:COM21:COM20) Effect on Compare Pin Frequency: (0:0:0) = Not connected. (0:0:1) = Not connected. (0:1:0) = Cleared on compare match, up-counting. Set on compare match, down-counting (non-inverted PWM). f TCK0/2 /510. (0:1:1) = Cleared on compare match, down-counting. Set on compare match, up-counting (inverted PWM). f TCK0/2 /510. (1:0:0) = Not connected. (1:0:1) = Not connected. (1:1:0) = Cleared on compare match, set on overflow. f TCK0/2 /256. (1:1:1) = Set on compare match, cleared on overflow. f TCK0/ NA 0xB3 io_timer.bmp N OCR2-7 Timer/Counter2 Output Compare Register Bit 7 RW 0 OCR2-6 Timer/Counter2 Output Compare Register Bit 6 RW 0 OCR2-5 Timer/Counter2 Output Compare Register Bit 5 RW 0 OCR2-4 Timer/Counter2 Output Compare Register Bit 4 RW 0 OCR2-3 Timer/Counter2 Output Compare Register Bit 3 RW 0 OCR2-2 Timer/Counter2 Output Compare Register Bit 2 RW 0 OCR2-1 Timer/Counter2 Output Compare Register Bit 1 RW 0 OCR2-0 Timer/Counter2 Output Compare Register Bit 0 RW 0 ASSR Asynchronous Status Register NA 0xB6 io_flag.bmp Y EXCLK Enable External Clock Input When EXCLK is written to one, and asynchronous clock is selected, the external clock input buffer is enabled and an external clock can be input on Timer Oscillator 1 (TOSC1) pin instead of a 32 kHz crystal. Writing to EXCLK should be done before asynchronous operation is selected. Note that the crystal Oscillator will only run when this bit is zero. RW 0 AS2 Asynchronous Timer/Counter2 When AS2 is written to zero, Timer/Counter2 is clocked from the I/O clock, clkI/O. When AS2 is written to one, Timer/Counter2 is clocked from a crystal Oscillator connected to the Timer Oscillator 1 (TOSC1) pin. When the value of AS2 is changed, the contents of TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B might be corrupted. RW 0 TCN2UB Timer/Counter2 Update Busy When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set. When TCNT2 has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCNT2 is ready to be updated with a new value. R 0 OCR2AUB Output Compare Register2 Update Busy When Timer/Counter2 operates asynchronously and OCR2A is written, this bit becomes set. When OCR2A has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that OCR2A is ready to be updated with a new value. R 0 OCR2BUB Output Compare Register 2 Update Busy When Timer/Counter2 operates asynchronously and OCR2B is written, this bit becomes set. When OCR2B has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that OCR2B is ready to be updated with a new value. R 0 TCR2AUB Timer/Counter Control Register2 Update Busy When Timer/Counter2 operates asynchronously and TCCR2A is written, this bit becomes set. When TCCR2A has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCCR2A is ready to be updated with a new value. R 0 TCR2BUB Timer/Counter Control Register2 Update Busy When Timer/Counter2 operates asynchronously and TCCR2B is written, this bit becomes set. When TCCR2B has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCCR2B is ready to be updated with a new value. R 0 GTCCR General Timer Counter Control register 0x23 0x43 io_flag.bmp Y TSM Timer/Counter Synchronization Mode RW 0 PSRASY PSR2 Prescaler Reset Timer/Counter2 When this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally cleared immediately by hardware. If the bit is written when Timer/Counter2 is operating in asynchronous mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by hardware if the TSM bit is set. Refer to the description of the “Bit 7 – TSM: Timer/Counter Synchronization Mode” on page 107 for a description of the Timer/Counter Synchronization mode. RW 0 [ADMUX:ADCSRA:ADCSRB:ADCH:ADCL:DIDR0] ((IF ADMUX.ADLAR = 1) LINK [ADCH(1:0):ADCL(7:0)]); (IF ADMUX.ADLAR = 0) LINK [ADCH(7:0):ADCL(7:6)]); io_analo.bmp AD Converter Feature list: 10-bit Resolution. 0.5 LSB Integral Non-Linearity. +-2 LSB Absolute Accuracy. TBD - 260 µs Conversion Time. Up to TBD kSPS at maximum resolution. 8 Multiplexed Single Ended Input Channels. 7 Differential input channels (TQFP package only). 2 Differential input channels with optional gain of 10x and 200x (TQFP package only). Optional left adjustment for ADC result readout. 0 - VCC ADC Input Voltage Range. Selectable 2.56 V ADC reference voltage. Free Running or Single Conversion Mode. Interrupt on ADC Conversion Complete. Sleep Mode No ADMUX The ADC multiplexer Selection Register NA 0x7C io_analo.bmp Y REFS1 Reference Selection Bit 1 These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin. RW 0 REFS0 Reference Selection Bit 0 These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin. RW 0 ADLAR Left Adjust Result The ADLAR bit affects the presentation of the ADC conversion result in the ADC data register. If ADLAR is cleared, the result is right adjusted. If ADLAR is set, the result is left adjusted. Changing the ADLAR bit will affect the ADC data register immediately, regardless of any ongoing conversions. For a complete description of this bit, see “The ADC Data Register -ADCL and ADCH” on page 198. RW 0 MUX3 Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). RW 0 MUX2 Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). RW 0 MUX1 Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). RW 0 MUX0 Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). RW 0 ADCH ADC Data Register High Byte When an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. The selected channel is differential if MUX4..0 are between ‘01000’ and ‘11101’, otherwise the selected channel is single ended. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8 bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUX4..0 bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adju NA 0x79 io_analo.bmp N ADCH7 ADC Data Register High Byte Bit 7 RW 0 ADCH6 ADC Data Register High Byte Bit 6 RW 0 ADCH5 ADC Data Register High Byte Bit 5 RW 0 ADCH4 ADC Data Register High Byte Bit 4 RW 0 ADCH3 ADC Data Register High Byte Bit 3 RW 0 ADCH2 ADC Data Register High Byte Bit 2 RW 0 ADCH1 ADC Data Register High Byte Bit 1 RW 0 ADCH0 ADC Data Register High Byte Bit 0 RW 0 ADCL ADC Data Register Low Byte When an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. The selected channel is differential if MUX4..0 are between ‘01000’ and ‘11101’, otherwise the selected channel is single ended. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8 bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUX4..0 bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right ad NA 0x78 io_analo.bmp N ADCL7 ADC Data Register Low Byte Bit 7 RW 0 ADCL6 ADC Data Register Low Byte Bit 6 RW 0 ADCL5 ADC Data Register Low Byte Bit 5 RW 0 ADCL4 ADC Data Register Low Byte Bit 4 RW 0 ADCL3 ADC Data Register Low Byte Bit 3 RW 0 ADCL2 ADC Data Register Low Byte Bit 2 RW 0 ADCL1 ADC Data Register Low Byte Bit 1 RW 0 ADCL0 ADC Data Register Low Byte Bit 0 RW 0 ADCSRA The ADC Control and Status register A NA 0x7A io_flag.bmp Y ADEN ADC Enable Writing a logical ‘1’ to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion. RW 0 ADSC ADC Start Conversion In Single Conversion Mode, a logical ‘1’ must be written to this bit to start each conversion. In Free Running Mode, a logical ‘1’ must be written to this bit to start the first conversion. The first time ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, an extended conversion will result. This extended conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. When a dummy conversion precedes a real conversion, ADSC will stay high until the real conversion completes. Writing a 0 to this bit has no effect RW 0 ADATE ADC Auto Trigger Enable When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a conversion on a positive edge of the selected trigger signal. The trigger source is selected by setting the ADC Trigger Select bits, ADTS in ADCSRB. RW 0 ADIF ADC Interrupt Flag This bit is set (one) when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set (one). ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a read-modify-write on ADCSR, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used. RW 0 ADIE ADC Interrupt Enable When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Complete Interrupt is activated. RW 0 ADPS2 ADC Prescaler Select Bits These bits determine the division factor between the XTAL frequency and the input clock to the ADC. RW 0 ADPS1 ADC Prescaler Select Bits These bits determine the division factor between the XTAL frequency and the input clock to the ADC. RW 0 ADPS0 ADC Prescaler Select Bits These bits determine the division factor between the XTAL frequency and the input clock to the ADC. RW 0 ADCSRB The ADC Control and Status register B NA 0x7B io_flag.bmp Y ACME RW 0 ADTS2 ADC Auto Trigger Source bit 2 Please refer to table on page 240 in datasheet for trigger selection. RW 0 ADTS1 ADC Auto Trigger Source bit 1 Please refer to table on page 240 in datasheet for trigger selection. RW 0 ADTS0 ADC Auto Trigger Source bit 0 Please refer to table on page 240 in datasheet for trigger selection. RW 0 DIDR0 Digital Input Disable Register When this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. NA 0x7E io_analo.bmp Y ADC5D RW 0 ADC4D RW 0 ADC3D RW 0 ADC2D RW 0 ADC1D RW 0 ADC0D RW 0 [ACSR:DIDR1] io_analo.bmp AlgComp_06 ACSR Analog Comparator Control And Status Register 0x30 0x50 io_analo.bmp Y ACD Analog Comparator Disable When this bit is written logic one, the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed. RW 0 ACBG Analog Comparator Bandgap Select When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. See “Internal Voltage Reference” on page 42. RW 0 ACO Analog Compare Output The output of the analog comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1-2 clock cycles. R NA ACI Analog Comparator Interrupt Flag This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hard-ware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag. RW 0 ACIE Analog Comparator Interrupt Enable When the ACIE bit is written logic one and the I-bit in the Status Register is set, the analog comparator interrupt is acti-vated. When written logic zero, the interrupt is disabled. RW 0 ACIC RW 0 ACIS1 Analog Comparator Interrupt Mode Select bit 1 These bits determine which comparator events that trigger the Analog Comparator interrupt. RW 0 ACIS0 Analog Comparator Interrupt Mode Select bit 0 These bits determine which comparator events that trigger the Analog Comparator interrupt. RW 0 DIDR1 Digital Input Disable Register 1 When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. NA 0x7F io_analo.bmp Y AIN1D AIN1 Digital Input Disable RW 0 AIN0D AIN0 Digital Input Disable RW 0 [PORTB:DDRB:PINB] io_port.bmp AVRSimIOPort.SimIOPort PORTB Port B Data Register 0x05 0x25 io_port.bmp N PORTB7 Port B Data Register bit 7 RW 0 PORTB6 Port B Data Register bit 6 RW 0 PORTB5 Port B Data Register bit 5 RW 0 PORTB4 Port B Data Register bit 4 RW 0 PORTB3 Port B Data Register bit 3 RW 0 PORTB2 Port B Data Register bit 2 RW 0 PORTB1 Port B Data Register bit 1 RW 0 PORTB0 Port B Data Register bit 0 RW 0 DDRB Port B Data Direction Register 0x04 0x24 io_flag.bmp N DDB7 Port B Data Direction Register bit 7 RW 0 DDB6 Port B Data Direction Register bit 6 RW 0 DDB5 Port B Data Direction Register bit 5 RW 0 DDB4 Port B Data Direction Register bit 4 RW 0 DDB3 Port B Data Direction Register bit 3 RW 0 DDB2 Port B Data Direction Register bit 2 RW 0 DDB1 Port B Data Direction Register bit 1 RW 0 DDB0 Port B Data Direction Register bit 0 RW 0 PINB Port B Input Pins The Port B Input Pins address - PINB - is not a register, and this address enables access to the physical value on each Port B pin. When reading PORTB, the Port B Data Latch is read, and when reading PINB, the logical values present on the pins are read. 0x03 0x23 io_port.bmp N PINB7 Port B Input Pins bit 7 R 0 PINB6 Port B Input Pins bit 6 R 0 PINB5 Port B Input Pins bit 5 R 0 PINB4 Port B Input Pins bit 4 R 0 PINB3 Port B Input Pins bit 3 R 0 PINB2 Port B Input Pins bit 2 R 0 PINB1 Port B Input Pins bit 1 R 0 PINB0 Port B Input Pins bit 0 R 0 [PORTC:DDRC:PINC] io_port.bmp AVRSimIOPort.SimIOPort PORTC Port C Data Register 0x08 0x28 io_port.bmp N PORTC6 Port C Data Register bit 6 RW 0 PORTC5 Port C Data Register bit 5 RW 0 PORTC4 Port C Data Register bit 4 RW 0 PORTC3 Port C Data Register bit 3 RW 0 PORTC2 Port C Data Register bit 2 RW 0 PORTC1 Port C Data Register bit 1 RW 0 PORTC0 Port C Data Register bit 0 RW 0 DDRC Port C Data Direction Register 0x07 0x27 io_flag.bmp N DDC6 Port C Data Direction Register bit 6 RW 0 DDC5 Port C Data Direction Register bit 5 RW 0 DDC4 Port C Data Direction Register bit 4 RW 0 DDC3 Port C Data Direction Register bit 3 RW 0 DDC2 Port C Data Direction Register bit 2 RW 0 DDC1 Port C Data Direction Register bit 1 RW 0 DDC0 Port C Data Direction Register bit 0 RW 0 PINC Port C Input Pins The Port C Input Pins address - PINC - is not a register, and this address enables access to the physical value on each Port C pin. When reading PORTC, the Port C Data Latch is read, and when reading PINC, the logical values present on the pins are read. 0x06 0x26 io_port.bmp N PINC6 Port C Input Pins bit 6 R 0 PINC5 Port C Input Pins bit 5 R 0 PINC4 Port C Input Pins bit 4 R 0 PINC3 Port C Input Pins bit 3 R 0 PINC2 Port C Input Pins bit 2 R 0 PINC1 Port C Input Pins bit 1 R 0 PINC0 Port C Input Pins bit 0 R 0 [PORTD:DDRD:PIND] io_port.bmp AVRSimIOPort.SimIOPort PORTD Port D Data Register 0x0B 0x2B io_port.bmp N PORTD7 Port D Data Register bit 7 RW 0 PORTD6 Port D Data Register bit 6 RW 0 PORTD5 Port D Data Register bit 5 RW 0 PORTD4 Port D Data Register bit 4 RW 0 PORTD3 Port D Data Register bit 3 RW 0 PORTD2 Port D Data Register bit 2 RW 0 PORTD1 Port D Data Register bit 1 RW 0 PORTD0 Port D Data Register bit 0 RW 0 DDRD Port D Data Direction Register 0x0A 0x2A io_flag.bmp N DDD7 Port D Data Direction Register bit 7 RW 0 DDD6 Port D Data Direction Register bit 6 RW 0 DDD5 Port D Data Direction Register bit 5 RW 0 DDD4 Port D Data Direction Register bit 4 RW 0 DDD3 Port D Data Direction Register bit 3 RW 0 DDD2 Port D Data Direction Register bit 2 RW 0 DDD1 Port D Data Direction Register bit 1 RW 0 DDD0 Port D Data Direction Register bit 0 RW 0 PIND Port D Input Pins The Port D Input Pins address - PIND - is not a register, and this address enables access to the physical value on each Port D pin. When reading PORTD, the Port D Data Latch is read, and when reading PIND, the logical values present on the pins are read. 0x09 0x29 io_port.bmp N PIND7 Port D Input Pins bit 7 R 0 PIND6 Port D Input Pins bit 6 R 0 PIND5 Port D Input Pins bit 5 R 0 PIND4 Port D Input Pins bit 4 R 0 PIND3 Port D Input Pins bit 3 R 0 PIND2 Port D Input Pins bit 2 R 0 PIND1 Port D Input Pins bit 1 R 0 PIND0 Port D Input Pins bit 0 R 0 [TIMSK0:TIFR0:TCCR0A:TCCR0B:TCNT0:OCR0A:OCR0B:GTCCR] io_timer.bmp At8pwm0_01 OCR0B Timer/Counter0 Output Compare Register The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC0 pin. 0x28 0x48 io_timer.bmp N OCR0B_7 RW 0 OCR0B_6 RW 0 OCR0B_5 RW 0 OCR0B_4 RW 0 OCR0B_3 RW 0 OCR0B_2 RW 0 OCR0B_1 RW 0 OCR0B_0 RW 0 OCR0A Timer/Counter0 Output Compare Register The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC0 pin. 0x27 0x47 io_timer.bmp N OCROA_7 RW 0 OCROA_6 RW 0 OCROA_5 RW 0 OCROA_4 RW 0 OCROA_3 RW 0 OCROA_2 RW 0 OCROA_1 RW 0 OCROA_0 RW 0 TCNT0 Timer/Counter0 The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT0 register blocks (removes) the compare match on the following timer clock. Modifying the counter (TCNT0) while the counter is running, introduces a risk of missing a compare match between TCNT0 the OCR0 register. 0x26 0x46 io_timer.bmp N TCNT0_7 RW 0 TCNT0_6 RW 0 TCNT0_5 RW 0 TCNT0_4 RW 0 TCNT0_3 RW 0 TCNT0_2 RW 0 TCNT0_1 RW 0 TCNT0_0 RW 0 TCCR0B Timer/Counter Control Register B 0x25 0x45 io_flag.bmp Y FOC0A Force Output Compare A W 0 FOC0B Force Output Compare B W 0 WGM02 RW 0 CS02 Clock Select RW 0 CS01 Clock Select RW 0 CS00 Clock Select RW 0 TCCR0A Timer/Counter Control Register A 0x24 0x44 io_flag.bmp Y COM0A1 Compare Output Mode, Phase Correct PWM Mode RW 0 COM0A0 Compare Output Mode, Phase Correct PWM Mode RW 0 COM0B1 Compare Output Mode, Fast PWm W 0 COM0B0 Compare Output Mode, Fast PWm RW 0 WGM01 Waveform Generation Mode RW 0 WGM00 Waveform Generation Mode RW 0 TIMSK0 Timer/Counter0 Interrupt Mask Register NA 0x6E io_flag.bmp Y OCIE0B Timer/Counter0 Output Compare Match B Interrupt Enable RW 0 OCIE0A Timer/Counter0 Output Compare Match A Interrupt Enable RW 0 TOIE0 Timer/Counter0 Overflow Interrupt Enable RW 0 TIFR0 Timer/Counter0 Interrupt Flag register 0x15 0x35 io_flag.bmp Y OCF0B Timer/Counter0 Output Compare Flag 0B RW 0 OCF0A Timer/Counter0 Output Compare Flag 0A RW 0 TOV0 Timer/Counter0 Overflow Flag RW 0 GTCCR General Timer/Counter Control Register 0x23 0x43 io_flag.bmp Y TSM Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSR2 and PSR10 bits is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSR2 and PSR10 bits are cleared by hardware, and the Timer/Counters start counting simultaneousl RW 0 PSRSYNC PSR10 Prescaler Reset Timer/Counter1 and Timer/Counter0 When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. RW 0 [EICRA:EIMSK:EIFR:PCICR:PCMSK2:PCMSK1:PCMSK0:PCIFR] [PCMSK1:PCMSK0] io_ext.bmp The external interrupts are triggered by the INT7:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT7:0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The external inter-rupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the Exter-nal Interrupt Control Registers - EICRA (INT3:0) and EICRB (INT7:4). When the external interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT7:4 requires the presence of an I/O clock, described in “Clock Systems and their Distribution” on page 29. Low level interrupts and the edge interrupt on INT3:0 are detected asynchronously. This implies that these inter-rupts can be used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode. Note that if a level triggered interrupt is used for wake-up from Power Down Mode, the changed level must be held for some time to wake up the MCU. This makes the MCU less sensitive to noise. The changed level is sampled twice by the watchdog oscillator clock. The period of the watchdog oscillator is 1 µs (nominal) at 5.0V and 25°C. The frequency of the watchdog oscillator is voltage dependent as shown in the Electrical Characteristics section. The MCU will wake up if the input has the required level during this sampling or if it is held until the end of the start-up time. The start-up time is defined by the SUT fuses as described in “Clock Systems and their Distribution” on page 29. If the level is sampled twice by the watchdog oscillator clock but disappears before the end of the start-up time, the MCU will still wake up, but no interrupt will be generated. The required level must be held long enough for the MCU to complete the wake up to trigger the level interrup EICRA External Interrupt Control Register The External Interrupt Control Register A contains control bits for interrupt sense control. NA 0x69 io_flag.bmp Y ISC11 External Interrupt Sense Control 1 Bit 1 The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT1 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt. RW 0 ISC10 External Interrupt Sense Control 1 Bit 0 The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT1 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt. RW 0 ISC01 External Interrupt Sense Control 0 Bit 1 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT0 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt. RW 0 ISC00 External Interrupt Sense Control 0 Bit 0 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set.The value on the INT0 pin is sampled before detecting edges.If edge or toggle interrupt is selected,pulses that last longer than one clock period will generate an interrupt.Shorter pulses are not guaranteed to generate an interrupt.If low level interrupt is selected,the lowlevel must be held until the completion of the currently executing instruction to generate an interrupt. RW 0 EIMSK External Interrupt Mask Register 0x1D 0x3D io_flag.bmp Y INT1 External Interrupt Request 1 Enable When the INT1 bit is set (one)and the I-bit in the Status Register (SREG)is set (one),the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10)in the External Interrupt Control Register A (EICRA)define whether the external interrupt is activated on rising and/or falling edge of the INT1 pin or level sensed.Activity on the pin will cause an interrupt request even if INT1 is configured as an output.The corresponding interrupt of External Interrupt Request 1 is executed from the INT1 interrupt vector. RW 0 INT0 External Interrupt Request 0 Enable When the INT0 bit is set (one)and the I-bit in the Status Register (SREG)is set (one),the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00)in the External Interrupt Control Register A (EICRA)define whether the external interrupt is activated on rising and/or falling edge of the INT0 pin or level sensed.Activity on the pin will cause an interrupt request even if INT0 is configured as an output.The corresponding interrupt of External Interrupt Request 0 is executed from the INT0 interrupt vector. RW 0 EIFR External Interrupt Flag Register 0x1C 0x3C io_flag.bmp Y INTF1 External Interrupt Flag 1 When an edge or logic change on the INT1 pin triggers an interrupt request,INTF1 becomes set (one).If the I-bit in SREG and the INT1 bit in EIMSK are set (one),the MCU will jump to the corresponding interrupt vector.The flag is cleared when the interrupt routine is executed.Alternatively,the flag can be cleared by writing a logical one to it.This flag is always cleared when INT0 is configured as a level interrupt. RW 0 INTF0 External Interrupt Flag 0 When an edge or logic change on the INT0 pin triggers an interrupt request,INTF0 becomes set (one).If the I-bit in SREG and the INT0 bit in EIMSK are set (one),the MCU will jump to the corresponding interrupt vector.The flag is cleared when the interrupt routine is executed.Alternatively,the flag can be cleared by writing a logical one to it.This flag is always cleared when INT0 is configured as a level interrupt. RW 0 PCICR NA 0x68 io_cpu.bmp Y PCIE2 R/W 0 PCIE1 R/W 0 PCIE0 R/W 0 PCMSK2 Pin Change Mask Register 2 Each PCINT15..8 bit selects whether pin change interrupt is enabled on the corresponding I/O pin.If PCINT15..8 is set and the PCIE1 bit in EIMSK is set,pin change interrupt is enabled on the corresponding I/O pin.If PCINT15..8 is cleared,pin change interrupt on the corresponding I/O pin is disabled. NA 0x6D io_flag.bmp Y PCINT23 Pin Change Enable Mask 23 RW 0 PCINT22 Pin Change Enable Mask 22 RW 0 PCINT21 Pin Change Enable Mask 21 RW 0 PCINT20 Pin Change Enable Mask 20 RW 0 PCINT19 Pin Change Enable Mask 19 RW 0 PCINT18 Pin Change Enable Mask 18 RW 0 PCINT17 Pin Change Enable Mask 17 RW 0 PCINT16 Pin Change Enable Mask 16 RW 0 PCMSK1 Pin Change Mask Register 1 Each PCINT15..8 bit selects whether pin change interrupt is enabled on the corresponding I/O pin.If PCINT15..8 is set and the PCIE1 bit in EIMSK is set,pin change interrupt is enabled on the corresponding I/O pin.If PCINT15..8 is cleared,pin change interrupt on the corresponding I/O pin is disabled. NA 0x6C io_flag.bmp Y PCINT14 Pin Change Enable Mask 14 RW 0 PCINT13 Pin Change Enable Mask 13 RW 0 PCINT12 Pin Change Enable Mask 12 RW 0 PCINT11 Pin Change Enable Mask 11 RW 0 PCINT10 Pin Change Enable Mask 10 RW 0 PCINT9 Pin Change Enable Mask 9 RW 0 PCINT8 Pin Change Enable Mask 8 RW 0 PCMSK0 Pin Change Mask Register 0 Each PCINT7..0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin.If PCINT7..0 is set and the PCIE0 bit in EIMSK is set,pin change interrupt is enabled on the corresponding I/O pin.If PCINT7..0 is cleared,pin change interrupt on the corresponding I/O pin is disabled. NA 0x6B io_flag.bmp Y PCINT7 Pin Change Enable Mask 7 RW 0 PCINT6 Pin Change Enable Mask 6 RW 0 PCINT5 Pin Change Enable Mask 5 RW 0 PCINT4 Pin Change Enable Mask 4 RW 0 PCINT3 Pin Change Enable Mask 3 RW 0 PCINT2 Pin Change Enable Mask 2 RW 0 PCINT1 Pin Change Enable Mask 1 RW 0 PCINT0 Pin Change Enable Mask 0 RW 0 PCIFR Pin Change Interrupt Flag Register 0x1B 0x3B io_flag.bmp Y PCIF2 Pin Change Interrupt Flag 2 When a logic change on any PCINT23..16 pin triggers an interrupt request, PCIF2 becomes set (one). If the I-bit in SREG and the PCIE2 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. RW 0 PCIF1 Pin Change Interrupt Flag 1 When a logic change on any PCINT14..8 pin triggers an interrupt request, PCIF1 becomes set (one). If the I-bit in SREG and the PCIE1 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. RW 0 PCIF0 Pin Change Interrupt Flag 0 When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0 becomes set (one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. RW 0 [SPDR:SPSR:SPCR] io_com.bmp SPI_01 The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the device and peripheral devices or between several AVR devices. The SPI includes the following features: • Full-duplex, 3-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Seven Programmable Bit Rates • End of Transmission Interrupt Flag • Write Collision Flag Protection • Wake-up from Idle Mode • Double Speed (CK/2) Master SPI Mode SPDR SPI Data Register The SPI Data Register is a read/write register used for data transfer between the register file and the SPI Shift register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read. 0x2E 0x4E io_com.bmp N SPDR7 SPI Data Register bit 7 RW X SPDR6 SPI Data Register bit 6 RW X SPDR5 SPI Data Register bit 5 RW X SPDR4 SPI Data Register bit 4 RW X SPDR3 SPI Data Register bit 3 RW X SPDR2 SPI Data Register bit 2 RW X SPDR1 SPI Data Register bit 1 R 0 SPDR0 SPI Data Register bit 0 R 0 SPSR SPI Status Register 0x2D 0x4D io_flag.bmp Y SPIF SPI Interrupt Flag When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is generated if SPIE in SPCR is set (one) and global interrupts are enabled. If SS is an input and is driven low when the SPI is in master mode, this will also set the SPIF flag. SPIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the SPI status register when SPIF is set (one), then accessing the SPI Data Register (SPDR). R 0 WCOL Write Collision Flag The WCOL bit is set if the SPI data register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Register when WCOL is set (one), and then accessing the SPI Data Register. R 0 SPI2X Double SPI Speed Bit When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in master mode (see Table 71). This means that the minimum SCK period will be 2 CPU clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at f ck / 4 or lower. The SPI interface on the ATmega104 is also used for program memory and EEPROM downloading or uploading. See page 253 for serial programming and verification. RW 0 SPCR SPI Control Register 0x2c 0x4C io_flag.bmp Y SPIE SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR register is set and the global interrupts are enabled. RW 0 SPE SPI Enable When the SPE bit is set (one), the SPI is enabled. This bit must be set to enable any SPI operations. RW 0 DORD Data Order When the DORD bit is set (one), the LSB of the data word is transmitted first. When the DORD bit is cleared (zero), the MSB of the data word is transmitted first. RW 0 MSTR Master/Slave Select This bit selects Master SPI mode when set (one), and Slave SPI mode when cleared (zero). If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI master mode. RW 0 CPOL Clock polarity When this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is low when idle. Refer to Figure 36 and Figure 37 for additional information. RW 0 CPHA Clock Phase Refer to Figure 36 or Figure 37 for the functionality of this bit. RW 0 SPR1 SPI Clock Rate Select 1 RW 0 SPR0 SPI Clock Rate Select 0 RW 0 [SREG:SPH:SPL:OSCCAL:CLKPR:SPMCSR:MCUCR:MCUSR:SMCR:GPIOR2:GPIOR1:GPIOR0:PRR] [SPH:SPL] io_cpu.bmp PRR Power Reduction Register The Power Reduction Register, PRR, provides a method to stop the clock to individual peripherals to reduce power consumption. NA 0x64 io_cpu.bmp Y PRTWI Power Reduction TWI R/W 0 PRTIM2 Power Reduction Timer/Counter2 R/W 0 PRTIM0 Power Reduction Timer/Counter0 R/W 0 PRTIM1 Power Reduction Timer/Counter1 R/W 0 PRSPI Power Reduction Serial Peripheral Interface R/W 0 PRUSART0 Power Reduction USART R/W 0 PRADC Power Reduction ADC R/W 0 OSCCAL Oscillator Calibration Value Writing the calibration byte to this address will trim the internal oscillator to remove process variations from the oscillator frequency. This is done automatically during chip reset. When OSCCAL is zero, the lowest available frequency is chosen. Writing non-zero values to this register will increase the frequency of the internal oscillator. Writing $FF to the register gives the highest available frequency. The calibrated oscillator is used to time EEPROM and Flash access. If EEPROM or Flash is written, do not calibrate to more than 10% above the nominal frequency. Otherwise, the EEPROM or Flash write may fail. Note that the Oscillator is intended for calibration to 1.0 MHz, 2.0 MHz, 4.0 MHz, or 8.0MHz. Tuning to other values is not guaranteed, as indicated in Table 14 NA 0x66 io_cpu.bmp N CAL7 Oscillator Calibration Value Bit7 R/W 0 CAL6 Oscillator Calibration Value Bit6 R/W 0 CAL5 Oscillator Calibration Value Bit5 R/W 0 CAL4 Oscillator Calibration Value Bit4 R/W 0 CAL3 Oscillator Calibration Value Bit3 R/W 0 CAL2 Oscillator Calibration Value Bit2 R/W 0 CAL1 Oscillator Calibration Value Bit1 R/W 0 CAL0 Oscillator Calibration Value Bit0 R/W 0 CLKPR Clock Prescale Register NA 0x61 io_flag.bmp Y CLKPCE Clock Prescaler Change Enable The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is cleared by hardware four cycles after it is written or when CLKPS bits are written. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the CLKPCE bit. RW 0 CLKPS3 Clock Prescaler Select Bit 3 These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. RW 0 CLKPS2 Clock Prescaler Select Bit 2 These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. RW 0 CLKPS1 Clock Prescaler Select Bit 1 These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. RW 0 CLKPS0 Clock Prescaler Select Bit 0 These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. RW 0 SREG Status Register 0x3F 0x5F io_sreg.bmp Y I Global Interrupt Enable The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable bit is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. RW 0 T Bit Copy Storage The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction. RW 0 H Half Carry Flag The half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed information. RW 0 S Sign Bit The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruc-tion Set Description for detailed information. RW 0 V Two's Complement Overflow Flag The two’s complement overflow flag V supports two’s complement arithmetics. See the Instruction Set Description for detailed information. RW 0 N Negative Flag The negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information. RW 0 Z Zero Flag The zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information. RW 0 C Carry Flag The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software. RW 0 SPH Stack Pointer High The general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the AT90S4414/8515 supports up to 64 kB external SRAM, all 16-bits are used. The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or return from interrupt R 0x3E 0x5E io_sph.bmp N SP10 Stack pointer bit 10 RW 0 SP9 Stack pointer bit 9 RW 0 SP8 Stack pointer bit 8 RW 0 SPL Stack Pointer Low The general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the AT90S4414/8515 supports up to 64 kB external SRAM, all 16-bits are used. The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or return from interrupt 0x3D 0x5D io_sph.bmp N SP7 Stack pointer bit 7 RW 0 SP6 Stack pointer bit 6 RW 0 SP5 Stack pointer bit 5 RW 0 SP4 Stack pointer bit 4 RW 0 SP3 Stack pointer bit 3 RW 0 SP2 Stack pointer bit 2 RW 0 SP1 Stack pointer bit 1 RW 0 SP0 Stack pointer bit 0 RW 0 SPMCSR Store Program Memory Control Register 0x37 0x57 io_cpu.bmp Y SPMIE SPM Interrupt Enable When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN bit in the SPMCR register is cleared. R/W 0 RWWSB Read-While-Write Section Busy R 0 RWWSRE Read-While-Write section read enable R/W 0 BLBSET Boot Lock Bit Set If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles sets Boot Lock bits, according to the data in R0. The data in R1 and the address in the Z pointer are ignored. The BLBSET bit will automatically be cleared upon completion of the lock bit set, or if no SPM instruction is executed within four clock cycles. R/W 0 PGWRT Page Write If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed. R/W 0 PGERS Page Erase If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page erase. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a page erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed. R/W 0 SELFPRGEN Self Programming Enable The explanation is to long to include here. Please refer to the printed documentation. R/W 0 MCUCR MCU Control Register The MCU Control Register contains control bits for general MCU functions. 0x35 0x55 io_flag.bmp Y PUD RW 0 IVSEL RW 0 IVCE RW 0 MCUSR MCU Status Register The MCU Status Register provides information on which reset source caused a MCU reset. 0x34 0x54 io_flag.bmp Y WDRF Watchdog Reset Flag This bit is set if a watchdog reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag. R/W 0 BORF Brown-out Reset Flag This bit is set if a brown-out reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag. R/W 0 EXTRF EXTREF External Reset Flag This bit is set if an external reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag. R/W 0 PORF Power-on reset flag This bit is set if a power-on reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the reset flags to identify a reset condition, the user should read and then reset the MCUCSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags. R/W 0 SMCR 0x33 0x53 io_flag.bmp Y SM2 RW 0 SM1 RW 0 SM0 RW 0 SE RW 0 GPIOR2 General Purpose I/O Register 2 0x2B 0x4B io_flag.bmp N GPIOR27 RW 0 GPIOR26 RW 0 GPIOR25 RW 0 GPIOR24 RW 0 GPIOR23 GPIOR22 RW 0 GPIOR21 RW 0 GPIOR20 RW 0 GPIOR1 General Purpose I/O Register 1 0x2A 0x4A io_flag.bmp N GPIOR17 RW 0 GPIOR16 RW 0 GPIOR15 RW 0 GPIOR14 RW 0 GPIOR13 GPIOR12 RW 0 GPIOR11 RW 0 GPIOR10 RW 0 GPIOR0 General Purpose I/O Register 0 0x1E 0x3E io_flag.bmp N GPIOR07 RW 0 GPIOR06 RW 0 GPIOR05 RW 0 GPIOR04 RW 0 GPIOR03 GPIOR02 RW 0 GPIOR01 RW 0 GPIOR00 RW 0 [WDTCSR] io_watch.bmp WDTCSR Watchdog Timer Control Register NA 0x60 io_flag.bmp Y WDIF Watchdog Timeout Interrupt Flag RW 0 WDIE Watchdog Timeout Interrupt Enable RW 0 WDP3 Watchdog Timer Prescaler Bit 3 RW 0 WDCE Watchdog Change Enable RW 0 WDE Watch Dog Enable When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog RW 0 WDP2 Watch Dog Timer Prescaler bit 2 RW 0 WDP1 Watch Dog Timer Prescaler bit 1 RW 0 WDP0 Watch Dog Timer Prescaler bit 0 RW 0 [EEARL:EEARH:EEDR:EECR] io_cpu.bmp EEPROM Read/Write Access. The EEPROM access registers are accessible in the I/O space. The write access time for the EEPROM is given in Table 1. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page 19. for details on how to avoid problems in these situations.In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When theEEPROM is written, the CPU is halted for two clock cycles before the next instruction is execut EEARH EEPROM Address Register High Byte 0x22 0x42 io_cpu.bmp N EEAR8 EEPROM Read/Write Access Bit 0 RW 0 EEARL EEPROM Address Register Low Byte 0x21 0x41 io_cpu.bmp N EEAR7 EEPROM Read/Write Access Bit 7 RW 0 EEAR6 EEPROM Read/Write Access Bit 6 RW 0 EEAR5 EEPROM Read/Write Access Bit 5 RW 0 EEAR4 EEPROM Read/Write Access Bit 4 RW 0 EEAR3 EEPROM Read/Write Access Bit 3 RW 0 EEAR2 EEPROM Read/Write Access Bit 2 RW 0 EEAR1 EEPROM Read/Write Access Bit 1 RW 0 EEAR0 EEPROM Read/Write Access Bit 0 RW 0 EEDR EEPROM Data Register For the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR. 0x20 0x40 io_cpu.bmp N EEDR7 EEPROM Data Register bit 7 RW 0 EEDR6 EEPROM Data Register bit 6 RW 0 EEDR5 EEPROM Data Register bit 5 RW 0 EEDR4 EEPROM Data Register bit 4 RW 0 EEDR3 EEPROM Data Register bit 3 RW 0 EEDR2 EEPROM Data Register bit 2 RW 0 EEDR1 EEPROM Data Register bit 1 RW 0 EEDR0 EEPROM Data Register bit 0 RW 0 EECR EEPROM Control Register 0x1F 0x3F io_flag.bmp Y EEPM1 EEPROM Programming Mode Bit 1 The EEPROM Programming mode bit setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in Table 2. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming. RW X EEPM0 EEPROM Programming Mode Bit 0 The EEPROM Programming mode bit setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in Table 2. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming. RW X EERIE EEPROM Ready Interrupt Enable EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared. RW 0 EEMPE EEPROM Master Write Enable The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is written to one, writing EEWE to one within 4 clock cycles will write data to the EEPROM at the selected address. If EEMWE is zero, writing EEWE to one will have no effect. When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure. RW 0 EEPE EEPROM Write Enable The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential): 1. Wait until EEWE becomes zero. 2. Wait until SPMEN in SPMCR becomes zero. 3. Write new EEPROM address to EEAR (optional). 4. Write new EEPROM data to EEDR (optional). 5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR. 6. Within four clock cycles after setting EEMWE, write a logical one to EEWE. The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a boot loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See “Boot Loader Support - Read While Write self-programming” on page 228 for details about boot programming. Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR regis-ter will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the 4 last steps to avoid these problems. When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruc-tion is executed RW X EERE EEPROM Read Enable The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR register. The calibrated oscillator is used to time the EEPROM accesses. Table 1 lists the typical programming time for EEPROM access from the CPU RW 0 [ICE50:SIMULATOR:JTAGICEmkII:STK500:STK500_2:AVRISPmkII:AVRDragon] 0x05 0x0F 0x0F 0x0F 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x0F 0x0F 0x0F 0x15 0x14 0x14 0x000004FF 0x00000000 0x00000000 0x00000000 0x000001FF 0x00001FFF 0x00000FFF 0x00000FFF 0x00000FFF 0x00000FFF 0x000004FF 0x0000FFFF 0x000001FF 0x00000000 0x00000000 0x00000000 0x0023FFFF 0x00000FFF 0x000000FF 0xDF 0xF9 0x62 0xff 0x66 0xc7 ATmega48.bin 0x02 0x00 1000000 24000000 2 ; INTOSC = 1, INTRC=2;EXTCLK=4 1 ;NOTUSE = 1, EXTERNAL = 4, INTERNAL = 2 1 0 0x40 0x40 0x00 0x80 8 0x00060000 0x00060000 Boot Size 128 Words, 4 pages, $F80-$FFF, Boot reset $F80 0x00060000 0x00040000 Boot Size 256 Words, 8 pages, $F00-$FFF, Boot reset $F00 0x00060000 0x00020000 Boot Size 512 Words, 16 pages, $E00-$FFF, Boot reset $E00 0x00060000 0x00000000 Boot Size 1024 Words, 32 pages, $C00-$FFF, Boot reset $C00 0x00010000 0x00010000 Application reset, address $0 0x00010000 0x0000000 Boot loader reset 0x0C000000 0x0C000000 No restrictions for SPM or (E)LPM 0x0C000000 0x08000000 No write to the Application section 0x0C000000 0x00000000 No write to Application section, No read from the Application section 0x0C000000 0x04000000 No read from the Application section 0x30000000 0x30000000 No restrictions for SPM or (E)LPM 0x30000000 0x20000000 No write to the Boot Loader section 0x30000000 0x00000000 No write to Boot Loader section, No read from the Boot Loader section 0x30000000 0x10000000 No read from the Boot Loader section 0x00000040 0x00000000 CKOUT fuse 0x00000040 0x00000040 CKOUT fuse 0x00000031 0x00000000 1K CK, 14CK 0x00000031 0x00000010 1K CK, 14CK + 4.1 ms 0x00000031 0x00000020 1K CK, 14CK + 65 ms 0x00000031 0x00000001 321K CK, 14CK 0x00000031 0x00000011 32K CK, 14CK + 4.1 ms 0x00000031 0x00000021 32K CK, 14CK + 65 ms 0x00000031 0x00000000 258 CK, 14CK + 4.1 ms 0x00000031 0x00000010 258 CK, 14CK +65 ms 0x00000031 0x00000020 1K CK, 14CK 0x00000031 0x00000030 1K CK, 14CK + 4.1 ms 0x00000031 0x00000001 1K CK, 14CK + 65 ms 0x00000031 0x00000011 16K CK, 14CK 0x00000031 0x00000021 16K CK, 14CK + 4.1 ms 0x00000031 0x00000031 16K CK, 14CK + 65 ms 0x00000030 0x00000000 6 CK, 14CK 0x00000030 0x00000010 6 CK, 14CK + 4.1 ms 0x00000030 0x00000020 6 CK, 14CK + 65 ms 0x00000030 0x00000000 6 CK, 14 CK 0x00000030 0x00000010 6 CK, 14CK + 4.1 ms 0x00000030 0x00000020 6 CK, 14CK + 65 ms 0x0000000e 0x00000004 0x0000000e 0x00000006 0x0000000f 0x00000002 8.0 0x0000000f 0x00000000 0x00001000 0x00000000 Watchdog always ON 0x00001000 0x00001000 Watchdog disabled 0x00008000 0x00000000 RSTDSBL Fuse 0x00008000 0x00008000 RSTDSBL 0x00000700 0x00000700 BOD disabled 0x00000700 0x00000600 BOD enabled, 1.8 V 0x00000700 0x00000500 BOD enabled, 2.7 V 0x00000700 0x00000400 BOD enabled, 4.3 V 8 0x00000080 0x00000000 CKDIV8 Fuse 0x00000080 0x00000080 CKDIV8 Fuse AVRSimCoreV2.SimCoreV2 AVRSimMemory8bit.SimMemory8bit AVRSimInterrupt.SimInterrupt 0x16 0 18 AVRSimIOPort.SimIOPort Y AVRSimIOPort.SimIOPort Y AVRSimIOPort.SimIOPort Y AVRSimIOPinChangeInterrupt.SimIOPinChangeInterrupt 0x03 0x48 0x01 0x3B 0x01 0x4b 0x03 0xff AVRSimIOPinChangeInterrupt.SimIOPinChangeInterrupt 0x04 0x48 0x02 0x1B 0x02 0x06 07f 0x4c AVRSimIOPinChangeInterrupt.SimIOPinChangeInterrupt 0x05 0x48 0x04 0x1B 0x04 0x09 0xff 0x4d AVRSimIOExtInterrupt.SimIOExtInterrupt 0x01 0x1D 0x01 0x1C 0x01 0x09 0x04 0x49 0x03 AVRSimIOExtInterrupt.SimIOExtInterrupt 0x02 0x1D 0x02 0x1C 0x02 0x09 0x08 0x49 0x0c AvrSimIOtim8pwmsync2.tim8pwmsync2 0x010 0x00E 0x00F PORTD PORTD 6 5 PIND 4 AVRSimIOTimert16pwm1.SimIOTimert16pwm1 0x0A 0x00B 0x00C 0x00D 0x09 0x20 0x03 0x01 0x05 0x02 0x05 0x04 AvrMasterTimer.MasterTimer 0x007 0x008 0x009 PORTB 3 PORTD 3 1:8:32:64:128:256:1024 AVRSimIOSPM.SimIOSPM 0x019 AVRSimIOSpi.SimIOSpi 0x011 0x03 0x20 0x03 0x10 0x03 0x08 0x03 0x04 0x04 AVRSimIOUsart.SimIOUsart 0x012 0x014 0x013 0x09 0x02 0x09 0x01 AvrMasterTimer.MasterTimer 128 1 0x006 2048:4096:8192:16384:32768:65536:131072:262144:524288:1048576 AVRSimAC.SimIOAC 0x17 AVRSimADC.SimADC 0x15 AvrSimTWI.SimTWI 0x18 0x99 0xff 0xe1 0xff 0x930A DebugWire 0xF8,0x0F,0xE0,0xF8,0xFF,0x3D,0xB9,0xE0 0xB0,0x0D,0x00,0xE0,0xFF,0x1D,0xB8,0xE0 0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00 0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00 0x53,0xFB,0x01,0xDF,0xF7,0x0F,0x00,0x00,0x00,0x00,0x5F,0x3F,0x37,0x00,0x00,0x00,0x00,0x00,0x00,0x00 0x00,0xFB,0x01,0xD8,0xF7,0x0F,0x00,0x00,0x00,0x00,0x5F,0x2F,0x36,0x00,0x00,0x00,0x00,0x00,0x00,0x00 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 0x00 0X00 0X00 64 4 0x0F80 0x0F80 0x0F00 0x0E00 0x0C00 0xC6 0x2000 0x0000,32 0x0020,64 0x00 0x40 0x00 0x00 0x20 0x00 0xBD,0xF2,0xBD,0xE1,0xBB,0xCF,0xB4,0x00,0xBE,0x01,0xB6,0x01,0xBC,0x00,0xBB,0xBF,0x99,0xF9,0xBB,0xAF 0xB6,0x01,0x11 0x3e 0x3d 0x31 0x10 0x00 0x00 0xF80 0x00 0x3f 0x73 1 1 1 0xFF 0xFF 0xFF 0 1 2001002532030x53114510x4164100x400x4C0x000x000x000x41450xC10xC20x000x000x0025625644440x0E 0x1E 0x0F 0x1F 0x2E 0x3E 0x2F 0x3F 0x4E 0x5E 0x4F 0x5F 0x6E 0x7E 0x6F 0x7F 0x66 0x76 0x67 0x77 0x6A 0x7A 0x6B 0x7B 0xBE 0xFD 0x00 0x01 0x00 0x00 0x00 0x001000511510151501050x0D25625650x052562560505