[ADMIN:CORE:INTERRUPT_VECTOR:PACKAGE:MEMORY:FUSE:PROGRAMMING:LOCKBIT:IO_MODULE:ICE_SETTINGS]ATtiny128MHZ193RELEASED$1E$90$05V0EAVRSimCoreV0.SimCoreV0[][][]32$00$1B$1A$1D$1C$1F$1E6$000External Reset, Power-on Reset and Watchdog Reset$001External Interrupt 0$002External Interrupt Request 0$003Timer/Counter0 Overflow$004EEPROM Ready$005Analog Comparator[DIP]8['RESET][PB3:CLOCK][PB4][GND][PB0:MOSI][PB1:MISO:INT0][PB2:SCK:T0][VCC]AVRSimMemory8bit.SimMemory8bit1024640NA0NA$00$3F$20$5F$3FNA0x010x020x040x080x100x200x400x80$3BNA0x200x40$3ANA0x200x40$39NA0x02$38NA0x02$35NA0x010x020x100x200x40$34NA0x010x020x040x08$33NA0x010x020x04$32NA0x010x020x040x080x100x200x400x80$31NA0x010x020x040x080x100x200x400x80$21NA0x010x020x040x080x10$1ENA0x010x020x040x080x100x20$1DNA0x010x020x040x080x100x200x400x80$1CNA0x010x020x040x08$18NA$1f0x010x020x040x080x10$17NA$3f0x010x020x040x080x100x20$16NA$3f0x010x020x040x080x100x20$08NA0x010x020x080x100x200x400x80[LOW]2180x800x80Brown-out detection level at VCC=1.8 V0x800x00Brown-out detection level at VCC=2.7 V0x400x00Brown-out detection enabled0x200x00Serial program downloading (SPI) enabled0x100x00External reset function of PB5 disabled0x0F0x0FCKSEL=1111 External Crystal / Ceramic Resonator0x0F0x0ECKSEL=1110 External Crystal / Ceramic Resonator0x0F0x0DCKSEL=1101 External Crystal / Ceramic Resonator0x0F0x0CCKSEL=1100 External Crystal / Ceramic Resonator0x0F0x0BCKSEL=1011 External Crystal / Ceramic Resonator0x0F0x0ACKSEL=1010 External Crystal / Ceramic Resonator0x0F0x09CKSEL=1001 External Low-Frequency Crystal0x0F0x08CKSEL=1000 External Low-Frequency Crystal0x0F0x07CKSEL=0111 External RC Ocsillator0x0F0x06CKSEL=0110 External RC Ocsillator0x0F0x05CKSEL=0101 External RC Ocsillator0x0F0x04CKSEL=0100 Internal RC Ocsillator0x0F0x03CKSEL=0011 Internal RC Ocsillator0x0F0x02CKSEL=0010 Internal RC Ocsillator ; default value0x0F0x01CKSEL=0001 External Clock0x0F0x00CKSEL=0000 External Clock0,0x20,0x20,WARNING! These fuse settings will disable the ISP interface!0,0x10,0x00,WARNING! Disabling external reset will make the ISP interface inaccessible!0,0x20,0x20,WARNING! These fuse settings will disable the ISP interface!0,0x10,0x00,WARNING! Disabling external reset will make the ISP interface inaccessible!0x00,1.2 MHz02[LB1 = 1 : LB2 = 1] No memory lock features enabled. [LB1 = 0 : LB2 = 1] Further programming of Flash and EEPROM is enabled. [LB1 = 0 : LB2 = 0] Same as previous, but verify is also disabled320x060x06Mode 1: No memory lock features enabled0x060x04Mode 2: Further programming disabled0x060x00Mode 3: Further programming and verification disabledLB1LockbitLB2Lockbit[ANALOG_COMPARATOR:CPU:EXTERNAL_INTERRUPT:EEPROM:PORTB:TIMER_COUNTER_0:WATCHDOG][ACSR]io_analo.bmpThe analog comparator compares the input values on the positive input PB2 (AIN0) and negative input PB3 (AIN1). When the voltage on the positive input PB2 (AIN0) is higher than the voltage on the negative input PB3 (AIN1), the Analog Com-parator Output, ACO is set (one). The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator. The user can select Inter-rupt triggering on comparator output rise, fall or toggleACSRAnalog Comparator Control And Status Register$08NAio_analo.bmpYACDAnalog Comparator DisableWhen this bit is set(one), the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.RW0AINBGAnalog Comparator Bandgap SelectRW0ACOAnalog Comparator OutputWhen this bit is set(one), the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.R0ACIAnalog Comparator Interrupt FlagThis bit is set (one) when a comparator output event triggers the interrupt mode defined by ACI1 and ACI0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set (one) and the I-bit in SREG is set (one). ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag. Observe however, that if another bit in this register is modified using the SBI or CBI instruction, ACI will be cleared if it has become set before the operationRW0ACIEAnalog Comparator Interrupt EnableWhen the ACIE bit is set (one) and the I-bit in the Status Register is set (one), the analog comparator interrupt is activated. When Cleared (Zero), the interrupt is disabled. RW0ACIS1Analog Comparator Interrupt Mode Select bit 1These bits determine which comparator events that trigger the Analog Comparator interrupt.RW0ACIS0Analog Comparator Interrupt Mode Select bit 0These bits determine which comparator events that trigger the Analog Comparator interrupt.RW0[SREG:MCUCR:MCUSR:OSCCAL]io_cpu.comSREGStatus Register$3FNAio_sreg.bmpYIGlobal Interrupt EnableThe global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable bit is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts.RW0TBit Copy StorageThe bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction.RW0HHalf Carry FlagThe half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed information.RW0SSign BitThe S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruc-tion Set Description for detailed information.RW0VTwo's Complement Overflow FlagThe two’s complement overflow flag V supports two’s complement arithmetics. See the Instruction Set Description for detailed information.RW0NNegative FlagThe negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.RW0ZZero FlagThe zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.RW0CCarry FlagThe carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software.RW0MCUCRMCU Control RegisterThe MCU Control Register contains control bits for general MCU functions.$35NAio_cpu.bmpYPUDPull-up DisableRW0SESleep EnableThe SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmers purpose, it is recommended to set the Sleep Enable SE bit just before the execution of the SLEEP instruction.RW0SMSleep ModeThis bit selects between the two available sleep modes. When SM is cleared (zero), Idle Mode is selected as Sleep Mode. When SM is set (one), Power Down mode is selected as sleep mode. For details, refer to the section “Sleep Modes” on page 25.RW0ISC01Interrupt Sense Control 0 bit 1RW0ISC00Interrupt Sense Control 0 bit 0R0MCUSRMCU Status registerThe MCU Status Registerprovides information on which reset source caused a MCU reset.$34NAio_cpu.bmpYWDRFWatchdog Reset FlagRW0BORFBrown-out Reset FlagRW0EXTRFExternal Reset FlagAfter a power-on reset, this bit is undefined (X). It will be set by an external reset. A watchdog reset will leave this bit unchanged.RW0PORFPower-On Reset FlagThis bit is set by a power-on reset. A watchdog reset or an external reset will leave this bit unchangedRW0OSCCALStatus Register$31NAio_sreg.bmpNCAL7Oscillator Calibration Value Bit 7RW0CAL6Oscillator Calibration Value Bit 6RW0CAL5Oscillator Calibration Value Bit 5RW0CAL4Oscillator Calibration Value Bit 4RW0CAL3Oscillator Calibration Value Bit 3RW0CAL2Oscillator Calibration Value Bit 2RW0CAL1Oscillator Calibration Value Bit 1RW0CAL0Oscillator Calibration Value Bit 0RW0[GIMSK:GIFR]io_ext.bmpGIMSKGeneral Interrupt Mask Register$3BNAio_flag.bmpYINT0External Interrupt Request 0 EnableWhen the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from program memory address $001. See also “External Interrupts.” • Bits 5..0 - Res: Reserved bitsRW0PCIEPin Change Interrupt EnableRW0GIFRGeneral Interrupt Flag register$3ANAio_flag.bmpYINTF0External Interrupt Flag 0When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the interrupt vector at address $001. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. RW0PCIFPin Change Interrupt FlagRW0[EEAR:EEDR:EECR]io_cpu.bmpEEPROM_02.xmlEEAREEPROM Read/Write AccessThe EEPROM access register is accessible in the I/O space. The write access time is in the range of 2.5 - 4ms, depending on the V CC voltages. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains code that writes the EEPROM, some pre-caution must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. CPU operation under these conditions is likely cause the program counter to perform unintentional jumps and eventually execute the EEPROM write code. To secure EEPROM integrity, the user is advised to use an external under-voltage reset circuit in this case. In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction$1ENAio_cpu.bmpNEEAR5EEPROM Read/Write Access bit 5RW0EEAR4EEPROM Read/Write Access bit 4RW0EEAR3EEPROM Read/Write Access bit 3RW0EEAR2EEPROM Read/Write Access bit 2RW0EEAR1EEPROM Read/Write Access bit 1RW0EEAR0EEPROM Read/Write Access bit 0RW0EEDREEPROM Data RegisterFor the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.$1DNAio_cpu.bmpNEEDR7EEPROM Data Register bit 7RW0EEDR6EEPROM Data Register bit 6RW0EEDR5EEPROM Data Register bit 5RW0EEDR4EEPROM Data Register bit 4RW0EEDR3EEPROM Data Register bit 3RW0EEDR2EEPROM Data Register bit 2RW0EEDR1EEPROM Data Register bit 1RW0EEDR0EEPROM Data Register bit 0RW0EECREEPROM Control Register$1CNAio_flag.bmpYEERIEEEProm Ready Interrupt EnableWhen the I-bit in SREG and EERIE are set (one), the EEPROM Ready Interrupt is enabled. When cleared (zero), the interrupt is disabled. The EEPROM Ready Interrupt generates a constant interrupt when EEWE is cleared (zero).RW0EEMWEEEPROM Master Write EnableThe EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set(one) setting EEWE will write data to the EEPROM at the selected address If EEMWE is zero, setting EEWE will have no effect. When EEMWE has been set (one) by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for a EEPROM write procedure.RW0EEWEEEPROM Write EnableThe EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 2 and 3 is unessential): 1. Wait until EEWE becomes zero. 2. Write new EEPROM address to EEARL and EEARH (optional). 3. Write new EEPROM data to EEDR (optional). 4. Write a logical one to the EEMWE bit in EECR (to be able to write a logical one to the EEMWE bit, the EEWE bit mustbewritten to zero in thesamecycle). 5. Within four clock cycles after setting EEMWE, write a logical one to EEWE. When the write access time (typically 2.5 ms at V CC =5Vor 4msatV CC = 2.7V) has elapsed, the EEWE bit is cleared (zero) by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted or two cycles before the next instruction is executed. Caution: An interrupt between step 4 and step 5 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR regis-ter will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the 4 last steps to avoid these problems.RW0EEREEEPROM Read EnableThe EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be set. When the EERE bit is cleared (zero) by hardware, requested data is found in the EEDR register. The EEPROM read access takes one instruction and there is no need to poll the EERE bit. When EERE has been set, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress when new data or address is written to the EEPROM I/O registers, the write operation will be interrupted, and the result is undefined.RW0[PORTB:DDRB:PINB]io_port.bmpAVRSimIOPort.SimIOPortPORTBData Register, Port B$18NAio_port.bmpNPORTB4RW0PORTB3RW0PORTB2RW0PORTB1RW0PORTB0RW0DDRBData Direction Register, Port B$17NAio_flag.bmpNDDB5RW0DDB4RW0DDB3RW0DDB2RW0DDB1RW0DDB0RW0PINBInput Pins, Port B$16NAio_port.bmpNPINB5R0PINB4R0PINB3R0PINB2R0PINB1R0PINB0R0[TIMSK:TIFR:TCCR0:TCNT0]io_timer.bmpt81The 8-bit Timer/Counter0 can select clock source from CK, prescaled CK, or an external pin. In addition it can be stopped as described in “Timer/Counter0 Control Register - TCCR0” on page 35. The overflow status flag is found in “The Timer/Counter Interrupt Flag Register - TIFR” on page 29. Control signals are found in the Timer/Counter0 Control Register - TCCR0. The interrupt enable/disable settings for Timer/Counter0 are found in “The Timer/Counter Interrupt Mask Regis-ter - TIMSK” on page 28. When Timer/Counter0 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. The 8-bit Timer/Counter0 features both a high resolution and a high accuracy usage with the lower prescaling opportuni-ties. Similarly, the high prescaling opportuni ties make the Timer/Counter0 useful for lower speed functions or exact timing functions with infrequent actionsTIMSKTimer/Counter Interrupt Mask Register$39NAio_flag.bmpYTOIE0Timer/Counter0 Overflow Interrupt EnableWhen the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.RW0TIFRTimer/Counter Interrupt Flag register$38NAio_flag.bmpYTOV0Timer/Counter0 Overflow FlagThe bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, and TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed.RW0TCCR0Timer/Counter0 Control Register$33NAio_flag.bmpYCS02Clock Select0 bit 2RW0CS01Clock Select0 bit 1RW0CS00Clock Select0 bit 0RW0TCNT0Timer Counter 0The Timer/Counter0 is realized as an up-counter with read and write access. If the Timer/Counter0 is written and a clock source is present, the Timer/Counter0 continues counting in the clock cycle following the write operation.$32NAio_timer.bmpNTCNT07Timer Counter 0 bit 7RW0TCNT06Timer Counter 0 bit 6RW0TCNT05Timer Counter 0 bit 5RW0TCNT04Timer Counter 0 bit 4RW0TCNT03Timer Counter 0 bit 3RW0TCNT02Timer Counter 0 bit 2RW0TCNT01Timer Counter 0 bit 1RW0TCNT00Timer Counter 0 bit 0RW0[WDTCR]io_watch.bmpWDTCRWatchdog Timer Control Register$21NAio_flag.bmpYWDTOEWDDERWThis bit must be set (one) when the WDE bit is cleared. Otherwise, the watchdog will not be disabled. Once set, hardware will clear this bit to zero after four clock cycles. Refer to the description of the WDE bit for a watchdog disable procedure.RW0WDEWatch Dog EnableWhen the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdogRW0WDP2Watch Dog Timer Prescaler bit 2RW0WDP1Watch Dog Timer Prescaler bit 1RW0WDP0Watch Dog Timer Prescaler bit 0RW0[SIMULATOR:STK500:STK500_2:AVRISPmkII]AVRSimCoreV2.SimCoreV2AVRSimMemory8bit.SimMemory8bitAVRSimInterrupt.SimInterrupt0x0405AVRSimIOPort.SimIOPort0xffNAVRSimIOExtInterrupt.SimIOExtInterrupt0x010x3b0x400x3a0x400x160x020x350x03AVRSimIOPinChangeInterrupt.SimIOPinChangeInterrupt0x020x3B0x200x3A0x200x000x160x3FAVRSimIOTimert81.SimIOTimert810x030x160x04AVRSimAC.SimIOAC0x050x121010xFF0xFF0xFF012001002532030x531110000x04128100x400x000x200xFF0x000x046480xC00x000xA00xFF0xFF25625644440x4C 0x0C 0x1C 0x2C 0x3C 0x64 0x74 0x00 0x68 0x78 0x68 0x68 0x00 0x00 0x68 0x78 0x78 0x00 0x6D 0x0C 0x80 0x40 0x20 0x10 0x11 0x08 0x04 0x02 0x03 0x08 0x04 0x00100061125101002540002563256025652562525