[ADMIN:INTERRUPT_VECTOR:MEMORY:PACKAGE:FUSE:CORE:PROGRAMMING:LOCKBIT:IO_MODULE:ICE_SETTINGS] ATtiny13 16MHZ 226 RELEASED $1E $90 $07 10 $000 RESET External Reset, Power-on Reset and Watchdog Reset $001 INT0 External Interrupt 0 $002 PCINT0 External Interrupt Request 0 $003 TIM0_OVF Timer/Counter0 Overflow $004 EE_RDY EEPROM Ready $005 ANA_COMP Analog Comparator $006 TIM0_COMPA Timer/Counter Compare Match A $007 TIM0_COMPB Timer/Counter Compare Match B $008 WDT Watchdog Time-out $009 ADC ADC Conversion Complete AVRSimMemory8bit.SimMemory8bit 1024 64 64 $60 0 NA $00 $3F NA NA $20 $5f $3F $5F 0x010x020x040x080x100x200x400x80 $3D $5D $9F 0x010x020x040x080x100x200x400x80 $3B $5B 0x200x40 $3A $5A 0x200x40 $39 $59 0x020x040x08 $38 $58 0x020x040x08 $37 $57 0x010x020x040x080x10 $36 $56 0x010x020x040x080x100x200x400x80 $35 $55 0x010x020x080x100x200x40 $34 $54 0x010x020x040x08 $33 $53 0x010x020x040x080x400x80 $32 $52 0x010x020x040x080x100x200x400x80 $31 $51 0x010x020x040x080x100x200x40 $2F $4F 0x010x020x100x200x400x80 $2E $4E 0x010x020x040x080x100x200x400x80 $29 $49 0x010x020x040x080x100x200x400x80 $28 $48 0x010x80 $26 $46 0x010x020x040x080x80 $21 $41 0x010x020x040x080x100x200x400x80 $1E $3E 0x010x020x040x080x100x20 $1D $3D 0x010x020x040x080x100x200x400x80 $1C $3C 0x010x020x040x080x100x20 $18 $38 0x010x020x040x080x100x20 $17 $37 0x010x020x040x080x100x20 $16 $36 0x010x020x040x080x100x20 $15 $35 0x010x020x040x080x100x20 $14 $34 0x040x080x100x200x010x02 $08 $28 0x010x020x080x100x200x400x80 $07 $27 0x010x020x200x40 $06 $26 0x010x020x040x080x100x200x400x80 $05 $25 0x010x020x040x080x100x200x400x80 $04 $24 0x010x020x040x080x100x200x400x80 $03 $23 0x010x020x040x40 16 [PDIP:SOIC] 8 [PCINT5:'RESET:ADC0:PB5] [PCINT3:XTAL1:ADC3:PB3] [PCINT4:ADC2:PB4] [GND] [PB0:MOSI:AIN0:OC0A:TXD:PCINT0] [PB1:MISO:INT0:AIN1:OC0B:INT0:RXD:PCINT1] [PB2:SCK:ADC1:T0:PCINT2] [VCC] 8 [PCINT5:'RESET:ADC0:PB5] [PCINT3:XTAL1:ADC3:PB3] [PCINT4:ADC2:PB4] [GND] [PB0:MOSI:AIN0:OC0A:TXD:PCINT0] [PB1:MISO:INT0:AIN1:OC0B:INT0:RXD:PCINT1] [PB2:SCK:ADC1:T0:PCINT2] [VCC] [LOW:HIGH] 8 SPIEN SPI programming enable 0 EESAVE Keep EEprom contents during chip erase 1 WDTON Watch dog timer always on 1 CKDIV8 Start up with system clock divided by 8 0 SUT1 Select start-up time 1 SUT0 Select start-up time 0 CKSEL1 Select Clock Source 1 CKSEL0 Select Clock Source 0 16 0x80 0x00 Serial program downloading (SPI) enabled; [SPIEN=0] 0x40 0x00 Preserve EEPROM memory through the Chip Erase cycle; [EESAVE=0] 0x20 0x00 Watch-dog Timer always on; [WDTON=0] 0x10 0x00 Divide clock by 8 internally; [CKDIV8=0] 0x0F 0x00 Ext. Clock; Start-up time: 14 CK + 0 ms; [CKSEL=00 SUT=00] 0x0F 0x04 Ext. Clock; Start-up time: 14 CK + 4 ms; [CKSEL=00 SUT=01] 0x0F 0x08 Ext. Clock; Start-up time: 14 CK + 64 ms; [CKSEL=00 SUT=10] 0x0F 0x01 Int. RC Osc. 4.8 MHz; Start-up time: 14 CK + 0 ms; [CKSEL=01 SUT=00] 0x0F 0x05 Int. RC Osc. 4.8 MHz; Start-up time: 14 CK + 4 ms; [CKSEL=01 SUT=01] 0x0F 0x09 Int. RC Osc. 4.8 MHz; Start-up time: 14 CK + 64 ms; [CKSEL=01 SUT=10] 0x0F 0x02 Int. RC Osc. 9.6 MHz; Start-up time: 14 CK + 0 ms; [CKSEL=10 SUT=00] 0x0F 0x06 Int. RC Osc. 9.6 MHz; Start-up time: 14 CK + 4 ms; [CKSEL=10 SUT=01] 0x0F 0x0A Int. RC Osc. 9.6 MHz; Start-up time: 14 CK + 64 ms; [CKSEL=10 SUT=10]; default value 0x0F 0x03 Int. RC Osc. 128 kHz; Start-up time: 14 CK + 0 ms; [CKSEL=11 SUT=00] 0x0F 0x07 Int. RC Osc. 128 kHz; Start-up time: 14 CK + 4 ms; [CKSEL=11 SUT=01] 0x0F 0x0B Int. RC Osc. 128 kHz; Start-up time: 14 CK + 64 ms; [CKSEL=11 SUT=10] 5 SELFPRGEN Self Programming Enable 1 DWEN DebugWire Enable 1 BODLEVEL1 Enable BOD and select level 1 BODLEVEL0 Enable BOD and select level 1 RSTDISBL Disable external reset 1 7 0x10 0x00 Self Programming enable; [SELFPRGEN=0] 0x08 0x00 Debug Wire enable; [DWEN=0] 0x06 0x00 Brown-out detection level at VCC=4.3 V; [BODLEVEL=00] 0x06 0x02 Brown-out detection level at VCC=2.7 V; [BODLEVEL=01] 0x06 0x04 Brown-out detection level at VCC=1.8 V; [BODLEVEL=10] 0x06 0x06 Brown-out detection disabled; [BODLEVEL=11] 0x01 0x00 Reset Disabled (Enable PB5 as i/o pin); [RSTDISBL=0] V2 AVRSimCoreV2.SimCoreV2 [lpm rd,z+] [] [] 32 $00 $1B $1A $1D $1C $1F $1E 0x7f,0x1f 0x7f,0x1f 0,0x80,0x80,WARNING! These fuse settings will disable the ISP interface! 0,0x03,0x03, WARNING! When selecting Int RC Osc 128kHz, be sure to not divide the clock using the CLKPR register with more than 16 times. Dividing the clock with 32 times or more when using the Int RC Osc 128kHz willl make the ISP interface inaccessible on STK500/AVRISP! 1,0x01,0x00,WARNING! Disabling external reset will make the ISP interface inaccessible! 1,0x08,0x00,WARNING! These fuse settings will disable the ISP interface! 0,0x80,0x80,WARNING! These fuse settings will disable the ISP interface! 0,0x03,0x03, WARNING! When selecting Int RC Osc 128kHz, be sure to not divide the clock using the CLKPR register with more than 16 times. Dividing the clock with 32 times or more when using the Int RC Osc 128kHz willl make the ISP interface inaccessible on STK500/AVRISP! 1,0x01,0x00,WARNING! Disabling external reset will make the ISP interface inaccessible! 1,0x08,0x00,WARNING! These fuse settings will disable the ISP interface! 0x00,9.6 MHz 0x01,4.8 MHz 32 4 [LB1 = 1 : LB2 = 1] No memory lock features enabled. [LB1 = 0 : LB2 = 1] Further programming of Flash and EEPROM is enabled. [LB1 = 0 : LB2 = 0] Same as previous, but verify is also disabled 3 2 0x03 0x03 Mode 1: No memory lock features enabled 0x03 0x02 Mode 2: Further programming disabled 0x03 0x00 Mode 3: Further programming and verification disabled LB1 Lockbit LB2 Lockbit [AD_CONVERTER:ANALOG_COMPARATOR:EEPROM:CPU:PORTB:EXTERNAL_INTERRUPT:TIMER_COUNTER_0:WATCHDOG] [ADMUX:ADCSRA:ADCH:ADCL:ADCSRB:DIDR0] ((IF ADMUX.ADLAR = 1) LINK [ADCH(1:0):ADCL(7:0)]); (IF ADMUX.ADLAR = 0) LINK [ADCH(7:0):ADCL(7:6)]); io_analo.bmp AD Converter Feature list: 10-bit Resolution. 0.5 LSB Integral Non-Linearity. +-2 LSB Absolute Accuracy. TBD - 260 µs Conversion Time. Up to TBD kSPS at maximum resolution. 8 Multiplexed Single Ended Input Channels. 7 Differential input channels (TQFP package only). 2 Differential input channels with optional gain of 10x and 200x (TQFP package only). Optional left adjustment for ADC result readout. 0 - VCC ADC Input Voltage Range. Selectable 2.56 V ADC reference voltage. Free Running or Single Conversion Mode. Interrupt on ADC Conversion Complete. Sleep Mode Noise ADMUX The ADC multiplexer Selection Register These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin. $07 $27 io_analo.bmp N REFS0 Reference Selection Bit 0 These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin. RW 0 ADLAR Left Adjust Result The ADLAR bit affects the presentation of the ADC conversion result in the ADC data register. If ADLAR is cleared, the result is right adjusted. If ADLAR is set, the result is left adjusted. Changing the ADLAR bit will affect the ADC data register immediately, regardless of any ongoing conversions. For a complete description of this bit, see “The ADC Data Register -ADCL and ADCH” on page 198. RW 0 MUX1 Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). RW 0 MUX0 Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). RW 0 ADCSRA The ADC Control and Status register $06 $26 io_flag.bmp Y ADEN ADC Enable Writing a logical ‘1’ to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion. RW 0 ADSC ADC Start Conversion In Single Conversion Mode, a logical ‘1’ must be written to this bit to start each conversion. In Free Running Mode, a logical ‘1’ must be written to this bit to start the first conversion. The first time ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, an extended conversion will result. This extended conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. When a dummy conversion precedes a real conversion, ADSC will stay high until the real conversion completes. Writing a 0 to this bit has no effect RW 0 ADATE ADC Auto Trigger Enable When this bit is written to one,Auto Triggering of the ADC is enabled.The ADC will start a conversion on a positive edge of the selected trigger signal.The trigger source is selected by setting the ADC Trigger Select bits,ADTS in ADCSRB. RW 0 ADIF ADC Interrupt Flag This bit is set (one) when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set (one). ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a read-modify-write on ADCSR, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used. RW 0 ADIE ADC Interrupt Enable When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Complete Interrupt is activated. RW 0 ADPS2 ADC Prescaler Select Bits These bits determine the division factor between the XTAL frequency and the input clock to the ADC. RW 0 ADPS1 ADC Prescaler Select Bits These bits determine the division factor between the XTAL frequency and the input clock to the ADC. RW 0 ADPS0 ADC Prescaler Select Bits These bits determine the division factor between the XTAL frequency and the input clock to the ADC. RW 0 ADCH ADC Data Register High Byte When an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. The selected channel is differential if MUX4..0 are between ‘01000’ and ‘11101’, otherwise the selected channel is single ended. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8 bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUX4..0 bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adju $05 $25 io_analo.bmp N ADCH7 ADC Data Register High Byte Bit 7 RW 0 ADCH6 ADC Data Register High Byte Bit 6 RW 0 ADCH5 ADC Data Register High Byte Bit 5 RW 0 ADCH4 ADC Data Register High Byte Bit 4 RW 0 ADCH3 ADC Data Register High Byte Bit 3 RW 0 ADCH2 ADC Data Register High Byte Bit 2 RW 0 ADCH1 ADC Data Register High Byte Bit 1 RW 0 ADCH0 ADC Data Register High Byte Bit 0 RW 0 ADCL ADC Data Register Low Byte When an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. The selected channel is differential if MUX4..0 are between ‘01000’ and ‘11101’, otherwise the selected channel is single ended. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8 bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUX4..0 bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right ad $04 $24 io_analo.bmp N ADCL7 ADC Data Register Low Byte Bit 7 RW 0 ADCL6 ADC Data Register Low Byte Bit 6 RW 0 ADCL5 ADC Data Register Low Byte Bit 5 RW 0 ADCL4 ADC Data Register Low Byte Bit 4 RW 0 ADCL3 ADC Data Register Low Byte Bit 3 RW 0 ADCL2 ADC Data Register Low Byte Bit 2 RW 0 ADCL1 ADC Data Register Low Byte Bit 1 RW 0 ADCL0 ADC Data Register Low Byte Bit 0 RW 0 ADCSRB ADC Control and Status Register B $03 $23 io_analo.bmp Y ADTS2 ADC Auto Trigger Source 2 If ADATE in ADCSRA is written to one,the value of these bits selects which source will trigger an ADC conversion.If ADATE is cleared,the ADTS2:0 settings will have no effect.A conversion will be triggered by the rising edge of the selected interrupt flag.Note that switching from a trigger source that is cleared to a trigger source that is set,will generate a positive edge on the trigger signal.If ADEN in ADCSRA is set,this will start a conversion.Switching to Free Running Mode (ADTS [2:0 ]=0)will not cause a trigger event,even if the ADC Interrupt Flag is set . RW 0 ADTS1 ADC Auto Trigger Source 1 If ADATE in ADCSRA is written to one,the value of these bits selects which source will trigger an ADC conversion.If ADATE is cleared,the ADTS2:0 settings will have no effect.A conversion will be triggered by the rising edge of the selected interrupt flag.Note that switching from a trigger source that is cleared to a trigger source that is set,will generate a positive edge on the trigger signal.If ADEN in ADCSRA is set,this will start a conversion.Switching to Free Running Mode (ADTS [2:0 ]=0)will not cause a trigger event,even if the ADC Interrupt Flag is set . RW 0 ADTS0 ADC Auto Trigger Source 0 If ADATE in ADCSRA is written to one,the value of these bits selects which source will trigger an ADC conversion.If ADATE is cleared,the ADTS2:0 settings will have no effect.A conversion will be triggered by the rising edge of the selected interrupt flag.Note that switching from a trigger source that is cleared to a trigger source that is set,will generate a positive edge on the trigger signal.If ADEN in ADCSRA is set,this will start a conversion.Switching to Free Running Mode (ADTS [2:0 ]=0)will not cause a trigger event,even if the ADC Interrupt Flag is set . RW 0 DIDR0 Digital Input Disable Register 0 $14 $34 io_analo.bmp N ADC0D ADC0 Digital input Disable When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. ADC2D ADC2 Digital input Disable When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. ADC3D ADC3 Digital input Disable When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. ADC1D ADC2 Digital input Disable When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. [ADCSRB:ACSR:DIDR0] io_analo.bmp AlgComp_01 ADCSRB ADC Control and Status Register B $03 $23 io_flag.bmp Y ACME Analog Comparator Multiplexer Enable When this bit is written logic one and the ADC is switched off (ADEN in ADCSR is zero), the ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed description of this bit, see “Analog Comparator Multiplexed Input” on page 186. RW 0 ACSR Analog Comparator Control And Status Register $08 $28 io_analo.bmp Y ACD Analog Comparator Disable When this bit is written logic one, the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed. RW 0 ACBG AINBG Analog Comparator Bandgap Select When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. See “Internal Voltage Reference” on page 42. RW 0 ACO Analog Compare Output The output of the analog comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1-2 clock cycles. R NA ACI Analog Comparator Interrupt Flag This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hard-ware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag. RW 0 ACIE Analog Comparator Interrupt Enable When the ACIE bit is written logic one and the I-bit in the Status Register is set, the analog comparator interrupt is acti-vated. When written logic zero, the interrupt is disabled. RW 0 ACIS1 Analog Comparator Interrupt Mode Select bit 1 These bits determine which comparator events that trigger the Analog Comparator interrupt. RW 0 ACIS0 Analog Comparator Interrupt Mode Select bit 0 These bits determine which comparator events that trigger the Analog Comparator interrupt. RW 0 DIDR0 $14 $34 Y AIN1D AIN1 Digital Input Disable When this bit is written logic one,the digital input buffer on the AIN1/0 pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. RW 0 AIN0D AIN0 Digital Input Disable When this bit is written logic one,the digital input buffer on the AIN1/0 pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. RW 0 [EEAR:EEDR:EECR] io_cpu.bmp EEPROM_02.xml EEAR EEARL EEPROM Read/Write Access The EEPROM access register is accessible in the I/O space. The write access time is in the range of 2.5 - 4ms, depending on the V CC voltages. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains code that writes the EEPROM, some pre-caution must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. CPU operation under these conditions is likely cause the program counter to perform unintentional jumps and eventually execute the EEPROM write code. To secure EEPROM integrity, the user is advised to use an external under-voltage reset circuit in this case. In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction $1E $3E io_cpu.bmp N EEAR5 EEPROM Read/Write Access bit 5 RW 0 EEAR4 EEPROM Read/Write Access bit 4 RW 0 EEAR3 EEPROM Read/Write Access bit 3 RW 0 EEAR2 EEPROM Read/Write Access bit 2 RW 0 EEAR1 EEPROM Read/Write Access bit 1 RW 0 EEAR0 EEPROM Read/Write Access bit 0 RW 0 EEDR EEPROM Data Register For the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR. $1D $3D io_cpu.bmp N EEDR7 EEPROM Data Register bit 7 RW 0 EEDR6 EEPROM Data Register bit 6 RW 0 EEDR5 EEPROM Data Register bit 5 RW 0 EEDR4 EEPROM Data Register bit 4 RW 0 EEDR3 EEPROM Data Register bit 3 RW 0 EEDR2 EEPROM Data Register bit 2 RW 0 EEDR1 EEPROM Data Register bit 1 RW 0 EEDR0 EEPROM Data Register bit 0 RW 0 EECR EEPROM Control Register $1C $3C io_flag.bmp Y EEPM1 RW 0 EEPM0 RW 0 EERIE EEProm Ready Interrupt Enable When the I-bit in SREG and EERIE are set (one), the EEPROM Ready Interrupt is enabled. When cleared (zero), the interrupt is disabled. The EEPROM Ready Interrupt generates a constant interrupt when EEWE is cleared (zero). RW 0 EEMWE EEMPE EEPROM Master Write Enable The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set(one) setting EEWE will write data to the EEPROM at the selected address If EEMWE is zero, setting EEWE will have no effect. When EEMWE has been set (one) by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for a EEPROM write procedure. RW 0 EEWE EEPE EEPROM Write Enable The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 2 and 3 is unessential): 1. Wait until EEWE becomes zero. 2. Write new EEPROM address to EEARL and EEARH (optional). 3. Write new EEPROM data to EEDR (optional). 4. Write a logical one to the EEMWE bit in EECR (to be able to write a logical one to the EEMWE bit, the EEWE bit mustbewritten to zero in thesamecycle). 5. Within four clock cycles after setting EEMWE, write a logical one to EEWE. When the write access time (typically 2.5 ms at V CC =5Vor 4msatV CC = 2.7V) has elapsed, the EEWE bit is cleared (zero) by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted or two cycles before the next instruction is executed. Caution: An interrupt between step 4 and step 5 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR regis-ter will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the 4 last steps to avoid these problems. RW 0 EERE EEPROM Read Enable The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be set. When the EERE bit is cleared (zero) by hardware, requested data is found in the EEDR register. The EEPROM read access takes one instruction and there is no need to poll the EERE bit. When EERE has been set, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress when new data or address is written to the EEPROM I/O registers, the write operation will be interrupted, and the result is undefined. RW 0 [SREG:SPL:MCUCR:MCUSR:OSCCAL:CLKPR:DWDR:SPMCSR] io_cpu.com SREG Status Register $3F $5F io_sreg.bmp Y I Global Interrupt Enable The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable bit is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. RW 0 T Bit Copy Storage The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction. RW 0 H Half Carry Flag The half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed information. RW 0 S Sign Bit The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruc-tion Set Description for detailed information. RW 0 V Two's Complement Overflow Flag The two’s complement overflow flag V supports two’s complement arithmetics. See the Instruction Set Description for detailed information. RW 0 N Negative Flag The negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information. RW 0 Z Zero Flag The zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information. RW 0 C Carry Flag The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software. RW 0 SPL Stack Pointer Low Byte $3D $5D io_sreg.bmp N SP7 Stack Pointer Bit 7 RW 0 SP6 Stack Pointer Bit 6 RW 0 SP5 Stack Pointer Bit 5 RW 0 SP4 Stack Pointer Bit 4 RW 0 SP3 Stack Pointer Bit 3 RW 0 SP2 Stack Pointer Bit 2 RW 0 SP1 Stack Pointer Bit 1 RW 0 SP0 Stack Pointer Bit 0 RW 0 MCUCR MCU Control Register The MCU Control Register contains control bits for general MCU functions. $35 $55 io_cpu.bmp Y PUD Pull-up Disable RW 0 SE Sleep Enable The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmers purpose, it is recommended to set the Sleep Enable SE bit just before the execution of the SLEEP instruction. R 0 SM1 Sleep Mode Select Bit 1 RW 0 SM0 Sleep Mode Select Bit 0 RW 0 ISC01 Interrupt Sense Control 0 bit 1 R 0 ISC00 Interrupt Sense Control 0 bit 0 R 0 MCUSR MCU Status register The MCU Status Registerprovides information on which reset source caused a MCU reset. $34 $54 io_cpu.bmp Y WDRF Watchdog Reset Flag RW 0 BORF Brown-out Reset Flag RW 0 EXTRF External Reset Flag After a power-on reset, this bit is undefined (X). It will be set by an external reset. A watchdog reset will leave this bit unchanged. RW 0 PORF Power-On Reset Flag This bit is set by a power-on reset. A watchdog reset or an external reset will leave this bit unchanged RW 0 OSCCAL Oscillator Calibration Register $31 $51 io_sreg.bmp N CAL6 Oscillatro Calibration Value Bit 6 RW 0 CAL5 Oscillatro Calibration Value Bit 5 RW 0 CAL4 Oscillatro Calibration Value Bit 4 RW 0 CAL3 Oscillatro Calibration Value Bit 3 RW 0 CAL2 Oscillatro Calibration Value Bit 2 RW 0 CAL1 Oscillatro Calibration Value Bit 1 RW 0 CAL0 Oscillatro Calibration Value Bit 0 RW 0 CLKPR Clock Prescale Register The ATtiny63 system clock can be divided by setting the Clock Prescale Register – CLKPR. This feature can be used to decrease power consumption when the requirement for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals. $26 $46 io_sreg.bmp N CLKPCE Clock Prescaler Change Enable The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only update when the other bits in CLKPR are simultaniosly written to zero. CLKPCE is cleared by hardware four cycles after it is written or when CLKPS is written. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the CLKPCE bit. RW 0 CLKPS3 Clock Prescaler Select Bit 3 RW 0 CLKPS2 Clock Prescaler Select Bit 2 These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. The division factors are given a table in the device user guide.. To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits: 1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero. 2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE. Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted RW 0 CLKPS1 Clock Prescaler Select Bit 1 These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. The division factors are given a table in the device user guide.. To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits: 1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero. 2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE. Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted RW 0 CLKPS0 Clock Prescaler Select Bit 0 These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. The division factors are given a table in the device user guide.. To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits: 1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero. 2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE. Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted RW 0 DWDR Debug Wire Data Register $2E $4E io_sreg.bmp N DWDR7 Debug Wire Data Register Bit 7 RW 0 DWDR6 Debug Wire Data Register Bit 6 RW 0 DWDR5 Debug Wire Data Register Bit 5 RW 0 DWDR4 Debug Wire Data Register Bit 4 RW 0 DWDR3 Debug Wire Data Register Bit 3 RW 0 DWDR2 Debug Wire Data Register Bit 2 RW 0 DWDR1 Debug Wire Data Register Bit 1 RW 0 DWDR0 Debug Wire Data Register Bit 0 RW 0 SPMCSR Store Program Memory Control and Status Register $37 $57 io_sreg.bmp Y CTPB Clear Temporary Page Buffer If the CTPB bit is written while filling the temporary page buffer, the temporary page buffer will be cleared and the data will be lost. RW 0 RFLB Read Fuse and Lock Bits An LPM instruction within three cycles after RFLB and SPMEN are set in the SPMCSR Register, will read either the Lock bits or the Fuse bits (depending on Z0 in the Zpointer) into the destination register. See “EEPROM Write Prevents Writing to SPMCSR” on page 98 in the data sheet for details. RW 0 PGWRT Page Write If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a Page Write, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page Write operation. RW 0 PGERS Page Erase If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Erase. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a Page Erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page Write operation. RW 0 SPMEN Store program Memory Enable This bit enables the SPM instruction for the next four clock cycles. If written to one together with either CTPB, RFLB, PGWRT, or PGERS, the following SPM instruction will have a special meaning, see description above. If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer. The LSB of the Z-pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During Page Erase and Page Write, the SPMEN bit remains high until the operation is completed. Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in the lower five bits will have no effect RW 0 [PORTB:DDRB:PINB] io_port.bmp AVRSimIOPort.SimIOPort PORTB Data Register, Port B $18 $38 io_port.bmp N PORTB5 RW 0 PORTB4 RW 0 PORTB3 RW 0 PORTB2 RW 0 PORTB1 RW 0 PORTB0 RW 0 DDRB Data Direction Register, Port B $17 $37 io_flag.bmp N DDB5 RW 0 DDB4 RW 0 DDB3 RW 0 DDB2 RW 0 DDB1 RW 0 DDB0 RW 0 PINB Input Pins, Port B $16 $36 io_port.bmp N PINB5 R 0 PINB4 R 0 PINB3 R 0 PINB2 R 0 PINB1 R 0 PINB0 R 0 [MCUCR:GIMSK:GIFR:PCMSK] io_ext.bmp MCUCR MCU Control Register $35 $55 io_cpu.bmp Y ISC01 Interrupt Sense Control 0 Bit 1 RW 0 ISC00 Interrupt Sense Control 0 Bit 0 RW 0 GIMSK GICR General Interrupt Mask Register $3B $5B io_flag.bmp Y INT0 External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from program memory address $001. See also “External Interrupts.” • Bits 5..0 - Res: Reserved bits RW 0 PCIE Pin Change Interrupt Enable RW 0 GIFR General Interrupt Flag register $3A $5A io_flag.bmp Y INTF0 External Interrupt Flag 0 When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the interrupt vector at address $001. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. RW 0 PCIF Pin Change Interrupt Flag RW 0 PCMSK Pin Change Enable Mask $15 $35 io_flag.bmp N PCINT5 Pin Change Enable Mask Bit 5 RW 0 PCINT4 Pin Change Enable Mask Bit 4 RW 0 PCINT3 Pin Change Enable Mask Bit 3 RW 0 PCINT2 Pin Change Enable Mask Bit 2 RW 0 PCINT1 Pin Change Enable Mask Bit 1 RW 0 PCINT0 Pin Change Enable Mask Bit 0 RW 0 [TIMSK0:TIFR0:OCR0A:TCCR0A:TCNT0:TCCR0B:OCR0B:GTCCR] io_timer.bmp At8pwm0_01 TIMSK0 Timer/Counter0 Interrupt Mask Register $39 $59 io_flag.bmp Y OCIE0B Timer/Counter0 Output Compare Match B Interrupt Enable RW 0 OCIE0A Timer/Counter0 Output Compare Match A Interrupt Enable RW 0 TOIE0 Timer/Counter0 Overflow Interrupt Enable RW 0 TIFR0 Timer/Counter0 Interrupt Flag register $38 $58 io_flag.bmp Y OCF0B Timer/Counter0 Output Compare Flag 0B RW 0 OCF0A Timer/Counter0 Output Compare Flag 0A RW 0 TOV0 Timer/Counter0 Overflow Flag RW 0 OCR0A Timer/Counter0 Output Compare Register The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC0 pin. $36 $56 io_timer.bmp N OCR0_7 RW 0 OCR0_6 RW 0 OCR0_5 RW 0 OCR0_4 RW 0 OCR0_3 RW 0 OCR0_2 RW 0 OCR0_1 RW 0 OCR0_0 RW 0 TCCR0A Timer/Counter Control Register A $2F $4F io_flag.bmp Y COM0A1 Compare Match Output A Mode RW 0 COM0A0 Compare Match Output A Mode RW 0 COM0B1 Compare Match Output B Mode RW 0 COM0B0 Compare Match Output B Mode RW 0 WGM01 Waveform Generation Mode RW 0 WGM00 Waveform Generation Mode RW 0 TCNT0 Timer/Counter0 The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT0 register blocks (removes) the compare match on the following timer clock. Modifying the counter (TCNT0) while the counter is running, introduces a risk of missing a compare match between TCNT0 the OCR0 register. $32 $52 io_timer.bmp N TCNT0_7 RW 0 TCNT0_6 RW 0 TCNT0_5 RW 0 TCNT0_4 RW 0 TCNT0_3 RW 0 TCNT0_2 RW 0 TCNT0_1 RW 0 TCNT0_0 RW 0 TCCR0B Timer/Counter Control Register B $33 $53 io_flag.bmp Y FOC0A Force Output Compare A RW 0 FOC0B Force Output Compare B RW 0 WGM02 Waveform Generation Mode RW 0 CS02 Clock Select RW 0 CS01 Clock Select RW 0 CS00 Clock Select RW 0 OCR0B Timer/Counter0 Output Compare Register The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC0 pin. $29 $49 io_timer.bmp N OCR0_7 RW 0 OCR0_6 RW 0 OCR0_5 RW 0 OCR0_4 RW 0 OCR0_3 RW 0 OCR0_2 RW 0 OCR0_1 RW 0 OCR0_0 RW 0 GTCCR General Timer Conuter Register $28 $48 io_timer.bmp Y TSM Timer/Counter Synchronization Mode RW 0 PSR10 Prescaler Reset Timer/Counter0 RW 0 [WDTCR] io_watch.bmp WDTCR Watchdog Timer Control Register $21 $41 io_flag.bmp Y WDTIF Watchdog Timeout Interrupt Flag RW 0 WDTIE Watchdog Timeout Interrupt Enable RW 0 WDP3 Watchdog Timer Prescaler Bit 3 RW 0 WDCE Watchdog Change Enable RW 0 WDE Watch Dog Enable When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog RW 0 WDP2 Watch Dog Timer Prescaler bit 2 RW 0 WDP1 Watch Dog Timer Prescaler bit 1 RW 0 WDP0 Watch Dog Timer Prescaler bit 0 RW 0 [ICE50:SIMULATOR:JTAGICEmkII:STK500:STK500_2:AVRISPmkII:AVRDragon] 0x05 0x0F 0x0F 0x0F 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x0F 0x0F 0x05 0x15 0x14 0x14 0x000000A0 0x00000000 0x00000000 0x00000000 0x0000003F 0x000003FF 0x000001FF 0x000001FF 0x000001FF 0x000001FF 0x000000A0 0x0000FFFF 0x0000003F 0x00000000 0x00000000 0x00000000 0x0023FFFF 0x00000FFF 0x00000060 0xEF 0x6A 0xff 0x51 0x6F ATtiny13.bin 0x02 0x00 1000000 40000000 7 2 ; INTOSC = 1, INTRC=2;EXTCLK=4 1 ;NOTUSE = 1, EXTERNAL = 4, INTERNAL = 2 1 0 0x01 0x00 0x01 8 0x80 0x00001000 0x00000000 SELFPRGEN Fuse 0x00001000 0x00001000 SELFPRGEN Fuse 0x0000000c 0x00000000 6 CK, 14CK 0x0000000c 0x00000004 6 CK, 14CK+4ms 0x0000000c 0x00000008 6 CK, 14CK+64 ms 0x0000000c 0x00000000 6 CK, 14CK 0x0000000c 0x00000004 6 CK, 14CK+4ms 0x0000000c 0x00000008 6 CK, 14CK+64 ms 0x0000000c 0x00000000 6 CK, 14CK 0x0000000c 0x00000004 6 CK, 14CK+4ms 0x0000000c 0x00000008 6 CK, 14CK+64 ms 0x00000003 0x00000003 0x00000003 0x00000001 9.6 0x00000003 0x00000002 4.8 0x00000003 0x00000000 0x00000020 0x00000000 Watchdog always ON 0x00000020 0x00000020 Watchdog disabled 0x00000100 0x00000000 RSTDSBL Fuse 0x00000100 0x00000100 RSTDSBL 8 0x00000010 0x00000000 CLKDIV8 Fuse 0x00000010 0x00000010 CLKDIV8 0x00000600 0x00000600 BOD disabled 0x00000600 0x00000400 BOD enabled, 1.8 V 0x00000600 0x00000200 BOD enabled, 2.7 V 0x00000600 0x00000000 BOD enabled, 4.3 V AVRSimCoreV2.SimCoreV2 AVRSimMemory8bit.SimMemory8bit AVRSimInterrupt.SimInterrupt 0x04 0 7 AVRSimIOPort.SimIOPort Y AVRSimIOExtInterrupt.SimIOExtInterrupt 0x01 0x3B 0x40 0x3A 0x40 0x16 0x02 0x35 0x03 AVRSimIOPinChangeInterrupt.SimIOPinChangeInterrupt 0x02 0x3B 0x20 0x3A 0x20 0x15 0x16 0x3f AvrSimIOTim8pwmsync2.tim8pwmsync2 0x03 0x06 0x07 PORTB PORTB 0 1 PINB 2 AVRSimAC.SimIOAC 0x05 AvrSimADC.SimADC 0x09 AvrMasterTimer.MasterTimer 1 2048:4096:8192:16384:32768:65536:131072:262144:524288:1048576 0x0008 0xff 0xff 0xff 0xff 0x9007 DebugWire 0xF8,0x01,0xF0,0x71,0x42,0x83,0xFE,0xAF 0x88,0x00,0xB0,0x71,0x00,0x83,0x7C,0xAA 0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00 0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 0x00 0X00 0X00 32 4 0x0000 0x0000 0x0000 0x0000 0x0000 0x00 0x400 0x0000,32 0x0020,64 0x00 0x08 0x00 0x00 0x00 0x80 0xBB,0xFE,0xBB,0xEE,0xBB,0xCC,0xB2,0x0D,0xBC,0x0E,0xB4,0x0E,0xBA,0x0D,0xBB,0xBC,0x99,0xE1,0xBB,0xAC 0xB4,0x0E,0x1E 0x00 0x3d 0x2E 0x00 0x00 0x00 0x00 0x00 0x1c 0x14 1 0 1 0xFF 0xFF 0xFF 0 1 2001002532030x53114510x4132100x400x4C0x000x000x000x41450xC10xC20x000x000x0025625644440x4C 0x0C 0x1C 0x2C 0x3C 0x64 0x74 0x66 0x68 0x78 0x68 0x68 0x7A 0x6A 0x68 0x78 0x78 0x7D 0x6D 0x0C 0x80 0x40 0x20 0x10 0x11 0x08 0x04 0x02 0x03 0x08 0x04 0x0010006112510100254000x0B25652560x0525652562525