[ADMIN:INTERRUPT_VECTOR:MEMORY:PACKAGE:FUSE:CORE:PROGRAMMING:LOCKBIT:IO_MODULE:ICE_SETTINGS]ATtiny1316MHZ226RELEASED$1E$90$0710$000External Reset, Power-on Reset and Watchdog Reset$001External Interrupt 0$002External Interrupt Request 0$003Timer/Counter0 Overflow$004EEPROM Ready$005Analog Comparator$006Timer/Counter Compare Match A$007Timer/Counter Compare Match B$008Watchdog Time-out$009ADC Conversion CompleteAVRSimMemory8bit.SimMemory8bit10246464$600NA$00$3FNANA$20$5f$3F$5F0x010x020x040x080x100x200x400x80$3D$5D$9F0x010x020x040x080x100x200x400x80$3B$5B0x200x40$3A$5A0x200x40$39$590x020x040x08$38$580x020x040x08$37$570x010x020x040x080x10$36$560x010x020x040x080x100x200x400x80$35$550x010x020x080x100x200x40$34$540x010x020x040x08$33$530x010x020x040x080x400x80$32$520x010x020x040x080x100x200x400x80$31$510x010x020x040x080x100x200x40$2F$4F0x010x020x100x200x400x80$2E$4E0x010x020x040x080x100x200x400x80$29$490x010x020x040x080x100x200x400x80$28$480x010x80$26$460x010x020x040x080x80$21$410x010x020x040x080x100x200x400x80$1E$3E0x010x020x040x080x100x20$1D$3D0x010x020x040x080x100x200x400x80$1C$3C0x010x020x040x080x100x20$18$380x010x020x040x080x100x20$17$370x010x020x040x080x100x20$16$360x010x020x040x080x100x20$15$350x010x020x040x080x100x20$14$340x040x080x100x200x010x02$08$280x010x020x080x100x200x400x80$07$270x010x020x200x40$06$260x010x020x040x080x100x200x400x80$05$250x010x020x040x080x100x200x400x80$04$240x010x020x040x080x100x200x400x80$03$230x010x020x040x4016[PDIP:SOIC]8[PCINT5:'RESET:ADC0:PB5][PCINT3:XTAL1:ADC3:PB3][PCINT4:ADC2:PB4][GND][PB0:MOSI:AIN0:OC0A:TXD:PCINT0][PB1:MISO:INT0:AIN1:OC0B:INT0:RXD:PCINT1][PB2:SCK:ADC1:T0:PCINT2][VCC]8[PCINT5:'RESET:ADC0:PB5][PCINT3:XTAL1:ADC3:PB3][PCINT4:ADC2:PB4][GND][PB0:MOSI:AIN0:OC0A:TXD:PCINT0][PB1:MISO:INT0:AIN1:OC0B:INT0:RXD:PCINT1][PB2:SCK:ADC1:T0:PCINT2][VCC][LOW:HIGH]8SPIENSPI programming enable0EESAVEKeep EEprom contents during chip erase1WDTONWatch dog timer always on1CKDIV8Start up with system clock divided by 80SUT1Select start-up time1SUT0Select start-up time0CKSEL1Select Clock Source1CKSEL0Select Clock Source0160x800x00Serial program downloading (SPI) enabled; [SPIEN=0]0x400x00Preserve EEPROM memory through the Chip Erase cycle; [EESAVE=0]0x200x00Watch-dog Timer always on; [WDTON=0]0x100x00Divide clock by 8 internally; [CKDIV8=0]0x0F0x00Ext. Clock; Start-up time: 14 CK + 0 ms; [CKSEL=00 SUT=00]0x0F0x04Ext. Clock; Start-up time: 14 CK + 4 ms; [CKSEL=00 SUT=01]0x0F0x08Ext. Clock; Start-up time: 14 CK + 64 ms; [CKSEL=00 SUT=10]0x0F0x01Int. RC Osc. 4.8 MHz; Start-up time: 14 CK + 0 ms; [CKSEL=01 SUT=00] 0x0F0x05Int. RC Osc. 4.8 MHz; Start-up time: 14 CK + 4 ms; [CKSEL=01 SUT=01] 0x0F0x09Int. RC Osc. 4.8 MHz; Start-up time: 14 CK + 64 ms; [CKSEL=01 SUT=10]0x0F0x02Int. RC Osc. 9.6 MHz; Start-up time: 14 CK + 0 ms; [CKSEL=10 SUT=00] 0x0F0x06Int. RC Osc. 9.6 MHz; Start-up time: 14 CK + 4 ms; [CKSEL=10 SUT=01] 0x0F0x0AInt. RC Osc. 9.6 MHz; Start-up time: 14 CK + 64 ms; [CKSEL=10 SUT=10]; default value0x0F0x03Int. RC Osc. 128 kHz; Start-up time: 14 CK + 0 ms; [CKSEL=11 SUT=00] 0x0F0x07Int. RC Osc. 128 kHz; Start-up time: 14 CK + 4 ms; [CKSEL=11 SUT=01] 0x0F0x0BInt. RC Osc. 128 kHz; Start-up time: 14 CK + 64 ms; [CKSEL=11 SUT=10]5SELFPRGENSelf Programming Enable1DWENDebugWire Enable1BODLEVEL1Enable BOD and select level1BODLEVEL0Enable BOD and select level1RSTDISBLDisable external reset170x100x00Self Programming enable; [SELFPRGEN=0]0x080x00Debug Wire enable; [DWEN=0]0x060x00Brown-out detection level at VCC=4.3 V; [BODLEVEL=00]0x060x02Brown-out detection level at VCC=2.7 V; [BODLEVEL=01]0x060x04Brown-out detection level at VCC=1.8 V; [BODLEVEL=10]0x060x06Brown-out detection disabled; [BODLEVEL=11]0x010x00Reset Disabled (Enable PB5 as i/o pin); [RSTDISBL=0]V2AVRSimCoreV2.SimCoreV2[lpm rd,z+][][]32$00$1B$1A$1D$1C$1F$1E0x7f,0x1f0x7f,0x1f0,0x80,0x80,WARNING! These fuse settings will disable the ISP interface!0,0x03,0x03, WARNING! When selecting Int RC Osc 128kHz, be sure to not divide the clock using the CLKPR register with more than 16 times. Dividing the clock with 32 times or more when using the Int RC Osc 128kHz willl make the ISP interface inaccessible on STK500/AVRISP!1,0x01,0x00,WARNING! Disabling external reset will make the ISP interface inaccessible!1,0x08,0x00,WARNING! These fuse settings will disable the ISP interface!0,0x80,0x80,WARNING! These fuse settings will disable the ISP interface!0,0x03,0x03, WARNING! When selecting Int RC Osc 128kHz, be sure to not divide the clock using the CLKPR register with more than 16 times. Dividing the clock with 32 times or more when using the Int RC Osc 128kHz willl make the ISP interface inaccessible on STK500/AVRISP!1,0x01,0x00,WARNING! Disabling external reset will make the ISP interface inaccessible!1,0x08,0x00,WARNING! These fuse settings will disable the ISP interface!0x00,9.6 MHz0x01,4.8 MHz324[LB1 = 1 : LB2 = 1] No memory lock features enabled. [LB1 = 0 : LB2 = 1] Further programming of Flash and EEPROM is enabled. [LB1 = 0 : LB2 = 0] Same as previous, but verify is also disabled320x030x03Mode 1: No memory lock features enabled0x030x02Mode 2: Further programming disabled0x030x00Mode 3: Further programming and verification disabledLB1LockbitLB2Lockbit[AD_CONVERTER:ANALOG_COMPARATOR:EEPROM:CPU:PORTB:EXTERNAL_INTERRUPT:TIMER_COUNTER_0:WATCHDOG][ADMUX:ADCSRA:ADCH:ADCL:ADCSRB:DIDR0]((IF ADMUX.ADLAR = 1) LINK [ADCH(1:0):ADCL(7:0)]); (IF ADMUX.ADLAR = 0) LINK [ADCH(7:0):ADCL(7:6)]);io_analo.bmpAD Converter Feature list: 10-bit Resolution. 0.5 LSB Integral Non-Linearity. +-2 LSB Absolute Accuracy. TBD - 260 µs Conversion Time. Up to TBD kSPS at maximum resolution. 8 Multiplexed Single Ended Input Channels. 7 Differential input channels (TQFP package only). 2 Differential input channels with optional gain of 10x and 200x (TQFP package only). Optional left adjustment for ADC result readout. 0 - VCC ADC Input Voltage Range. Selectable 2.56 V ADC reference voltage. Free Running or Single Conversion Mode. Interrupt on ADC Conversion Complete. Sleep Mode NoiseADMUXThe ADC multiplexer Selection RegisterThese bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin.$07$27io_analo.bmpNREFS0Reference Selection Bit 0These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin.RW0ADLARLeft Adjust ResultThe ADLAR bit affects the presentation of the ADC conversion result in the ADC data register. If ADLAR is cleared, the result is right adjusted. If ADLAR is set, the result is left adjusted. Changing the ADLAR bit will affect the ADC data register immediately, regardless of any ongoing conversions. For a complete description of this bit, see “The ADC Data Register -ADCL and ADCH” on page 198. RW0MUX1Analog Channel and Gain Selection BitsThe value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).RW0MUX0Analog Channel and Gain Selection BitsThe value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).RW0ADCSRAThe ADC Control and Status register$06$26io_flag.bmpYADENADC EnableWriting a logical ‘1’ to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.RW0ADSCADC Start ConversionIn Single Conversion Mode, a logical ‘1’ must be written to this bit to start each conversion. In Free Running Mode, a logical ‘1’ must be written to this bit to start the first conversion. The first time ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, an extended conversion will result. This extended conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. When a dummy conversion precedes a real conversion, ADSC will stay high until the real conversion completes. Writing a 0 to this bit has no effectRW0ADATEADC Auto Trigger EnableWhen this bit is written to one,Auto Triggering of the ADC is enabled.The ADC will start a conversion on a positive edge of the selected trigger signal.The trigger source is selected by setting the ADC Trigger Select bits,ADTS in ADCSRB. RW0ADIFADC Interrupt FlagThis bit is set (one) when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set (one). ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a read-modify-write on ADCSR, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used.RW0ADIEADC Interrupt EnableWhen this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Complete Interrupt is activated.RW0ADPS2ADC Prescaler Select BitsThese bits determine the division factor between the XTAL frequency and the input clock to the ADC.RW0ADPS1ADC Prescaler Select BitsThese bits determine the division factor between the XTAL frequency and the input clock to the ADC.RW0ADPS0ADC Prescaler Select BitsThese bits determine the division factor between the XTAL frequency and the input clock to the ADC.RW0ADCHADC Data Register High ByteWhen an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. The selected channel is differential if MUX4..0 are between ‘01000’ and ‘11101’, otherwise the selected channel is single ended. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8 bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUX4..0 bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adju$05$25io_analo.bmpNADCH7ADC Data Register High Byte Bit 7RW0ADCH6ADC Data Register High Byte Bit 6RW0ADCH5ADC Data Register High Byte Bit 5RW0ADCH4ADC Data Register High Byte Bit 4RW0ADCH3ADC Data Register High Byte Bit 3RW0ADCH2ADC Data Register High Byte Bit 2RW0ADCH1ADC Data Register High Byte Bit 1RW0ADCH0ADC Data Register High Byte Bit 0RW0ADCLADC Data Register Low ByteWhen an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. The selected channel is differential if MUX4..0 are between ‘01000’ and ‘11101’, otherwise the selected channel is single ended. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8 bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUX4..0 bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right ad$04$24io_analo.bmpNADCL7ADC Data Register Low Byte Bit 7RW0ADCL6ADC Data Register Low Byte Bit 6RW0ADCL5ADC Data Register Low Byte Bit 5RW0ADCL4ADC Data Register Low Byte Bit 4RW0ADCL3ADC Data Register Low Byte Bit 3RW0ADCL2ADC Data Register Low Byte Bit 2RW0ADCL1ADC Data Register Low Byte Bit 1RW0ADCL0ADC Data Register Low Byte Bit 0RW0ADCSRBADC Control and Status Register B$03$23io_analo.bmpYADTS2ADC Auto Trigger Source 2If ADATE in ADCSRA is written to one,the value of these bits selects which source will trigger an ADC conversion.If ADATE is cleared,the ADTS2:0 settings will have no effect.A conversion will be triggered by the rising edge of the selected interrupt flag.Note that switching from a trigger source that is cleared to a trigger source that is set,will generate a positive edge on the trigger signal.If ADEN in ADCSRA is set,this will start a conversion.Switching to Free Running Mode (ADTS [2:0 ]=0)will not cause a trigger event,even if the ADC Interrupt Flag is set . RW0ADTS1ADC Auto Trigger Source 1If ADATE in ADCSRA is written to one,the value of these bits selects which source will trigger an ADC conversion.If ADATE is cleared,the ADTS2:0 settings will have no effect.A conversion will be triggered by the rising edge of the selected interrupt flag.Note that switching from a trigger source that is cleared to a trigger source that is set,will generate a positive edge on the trigger signal.If ADEN in ADCSRA is set,this will start a conversion.Switching to Free Running Mode (ADTS [2:0 ]=0)will not cause a trigger event,even if the ADC Interrupt Flag is set . RW0ADTS0ADC Auto Trigger Source 0If ADATE in ADCSRA is written to one,the value of these bits selects which source will trigger an ADC conversion.If ADATE is cleared,the ADTS2:0 settings will have no effect.A conversion will be triggered by the rising edge of the selected interrupt flag.Note that switching from a trigger source that is cleared to a trigger source that is set,will generate a positive edge on the trigger signal.If ADEN in ADCSRA is set,this will start a conversion.Switching to Free Running Mode (ADTS [2:0 ]=0)will not cause a trigger event,even if the ADC Interrupt Flag is set . RW0DIDR0Digital Input Disable Register 0$14$34io_analo.bmpNADC0DADC0 Digital input DisableWhen this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. ADC2DADC2 Digital input DisableWhen this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. ADC3DADC3 Digital input DisableWhen this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. ADC1DADC2 Digital input DisableWhen this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. [ADCSRB:ACSR:DIDR0]io_analo.bmpAlgComp_01ADCSRBADC Control and Status Register B$03$23io_flag.bmpYACMEAnalog Comparator Multiplexer EnableWhen this bit is written logic one and the ADC is switched off (ADEN in ADCSR is zero), the ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed description of this bit, see “Analog Comparator Multiplexed Input” on page 186.RW0ACSRAnalog Comparator Control And Status Register$08$28io_analo.bmpYACDAnalog Comparator DisableWhen this bit is written logic one, the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.RW0ACBGAINBGAnalog Comparator Bandgap SelectWhen this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. See “Internal Voltage Reference” on page 42.RW0ACOAnalog Compare OutputThe output of the analog comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1-2 clock cycles.RNAACIAnalog Comparator Interrupt FlagThis bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hard-ware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.RW0ACIEAnalog Comparator Interrupt EnableWhen the ACIE bit is written logic one and the I-bit in the Status Register is set, the analog comparator interrupt is acti-vated. When written logic zero, the interrupt is disabled.RW0ACIS1Analog Comparator Interrupt Mode Select bit 1These bits determine which comparator events that trigger the Analog Comparator interrupt.RW0ACIS0Analog Comparator Interrupt Mode Select bit 0These bits determine which comparator events that trigger the Analog Comparator interrupt.RW0DIDR0$14$34YAIN1DAIN1 Digital Input DisableWhen this bit is written logic one,the digital input buffer on the AIN1/0 pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. RW0AIN0DAIN0 Digital Input DisableWhen this bit is written logic one,the digital input buffer on the AIN1/0 pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. RW0[EEAR:EEDR:EECR]io_cpu.bmpEEPROM_02.xmlEEAREEARLEEPROM Read/Write AccessThe EEPROM access register is accessible in the I/O space. The write access time is in the range of 2.5 - 4ms, depending on the V CC voltages. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains code that writes the EEPROM, some pre-caution must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. CPU operation under these conditions is likely cause the program counter to perform unintentional jumps and eventually execute the EEPROM write code. To secure EEPROM integrity, the user is advised to use an external under-voltage reset circuit in this case. In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction$1E$3Eio_cpu.bmpNEEAR5EEPROM Read/Write Access bit 5RW0EEAR4EEPROM Read/Write Access bit 4RW0EEAR3EEPROM Read/Write Access bit 3RW0EEAR2EEPROM Read/Write Access bit 2RW0EEAR1EEPROM Read/Write Access bit 1RW0EEAR0EEPROM Read/Write Access bit 0RW0EEDREEPROM Data RegisterFor the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.$1D$3Dio_cpu.bmpNEEDR7EEPROM Data Register bit 7RW0EEDR6EEPROM Data Register bit 6RW0EEDR5EEPROM Data Register bit 5RW0EEDR4EEPROM Data Register bit 4RW0EEDR3EEPROM Data Register bit 3RW0EEDR2EEPROM Data Register bit 2RW0EEDR1EEPROM Data Register bit 1RW0EEDR0EEPROM Data Register bit 0RW0EECREEPROM Control Register$1C$3Cio_flag.bmpYEEPM1RW0EEPM0RW0EERIEEEProm Ready Interrupt EnableWhen the I-bit in SREG and EERIE are set (one), the EEPROM Ready Interrupt is enabled. When cleared (zero), the interrupt is disabled. The EEPROM Ready Interrupt generates a constant interrupt when EEWE is cleared (zero).RW0EEMWEEEMPEEEPROM Master Write EnableThe EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set(one) setting EEWE will write data to the EEPROM at the selected address If EEMWE is zero, setting EEWE will have no effect. When EEMWE has been set (one) by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for a EEPROM write procedure.RW0EEWEEEPEEEPROM Write EnableThe EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 2 and 3 is unessential): 1. Wait until EEWE becomes zero. 2. Write new EEPROM address to EEARL and EEARH (optional). 3. Write new EEPROM data to EEDR (optional). 4. Write a logical one to the EEMWE bit in EECR (to be able to write a logical one to the EEMWE bit, the EEWE bit mustbewritten to zero in thesamecycle). 5. Within four clock cycles after setting EEMWE, write a logical one to EEWE. When the write access time (typically 2.5 ms at V CC =5Vor 4msatV CC = 2.7V) has elapsed, the EEWE bit is cleared (zero) by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted or two cycles before the next instruction is executed. Caution: An interrupt between step 4 and step 5 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR regis-ter will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the 4 last steps to avoid these problems.RW0EEREEEPROM Read EnableThe EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be set. When the EERE bit is cleared (zero) by hardware, requested data is found in the EEDR register. The EEPROM read access takes one instruction and there is no need to poll the EERE bit. When EERE has been set, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress when new data or address is written to the EEPROM I/O registers, the write operation will be interrupted, and the result is undefined.RW0[SREG:SPL:MCUCR:MCUSR:OSCCAL:CLKPR:DWDR:SPMCSR]io_cpu.comSREGStatus Register$3F$5Fio_sreg.bmpYIGlobal Interrupt EnableThe global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable bit is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts.RW0TBit Copy StorageThe bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction.RW0HHalf Carry FlagThe half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed information.RW0SSign BitThe S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruc-tion Set Description for detailed information.RW0VTwo's Complement Overflow FlagThe two’s complement overflow flag V supports two’s complement arithmetics. See the Instruction Set Description for detailed information.RW0NNegative FlagThe negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.RW0ZZero FlagThe zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.RW0CCarry FlagThe carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software.RW0SPLStack Pointer Low Byte$3D$5Dio_sreg.bmpNSP7Stack Pointer Bit 7RW0SP6Stack Pointer Bit 6RW0SP5Stack Pointer Bit 5RW0SP4Stack Pointer Bit 4RW0SP3Stack Pointer Bit 3RW0SP2Stack Pointer Bit 2RW0SP1Stack Pointer Bit 1RW0SP0Stack Pointer Bit 0RW0MCUCRMCU Control RegisterThe MCU Control Register contains control bits for general MCU functions.$35$55io_cpu.bmpYPUDPull-up DisableRW0SESleep EnableThe SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmers purpose, it is recommended to set the Sleep Enable SE bit just before the execution of the SLEEP instruction.R0SM1Sleep Mode Select Bit 1RW0SM0Sleep Mode Select Bit 0RW0ISC01Interrupt Sense Control 0 bit 1R0ISC00Interrupt Sense Control 0 bit 0R0MCUSRMCU Status registerThe MCU Status Registerprovides information on which reset source caused a MCU reset.$34$54io_cpu.bmpYWDRFWatchdog Reset FlagRW0BORFBrown-out Reset FlagRW0EXTRFExternal Reset FlagAfter a power-on reset, this bit is undefined (X). It will be set by an external reset. A watchdog reset will leave this bit unchanged.RW0PORFPower-On Reset FlagThis bit is set by a power-on reset. A watchdog reset or an external reset will leave this bit unchangedRW0OSCCALOscillator Calibration Register$31$51io_sreg.bmpNCAL6Oscillatro Calibration Value Bit 6RW0CAL5Oscillatro Calibration Value Bit 5RW0CAL4Oscillatro Calibration Value Bit 4RW0CAL3Oscillatro Calibration Value Bit 3RW0CAL2Oscillatro Calibration Value Bit 2RW0CAL1Oscillatro Calibration Value Bit 1RW0CAL0Oscillatro Calibration Value Bit 0RW0CLKPRClock Prescale RegisterThe ATtiny63 system clock can be divided by setting the Clock Prescale Register – CLKPR. This feature can be used to decrease power consumption when the requirement for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals.$26$46io_sreg.bmpNCLKPCEClock Prescaler Change EnableThe CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only update when the other bits in CLKPR are simultaniosly written to zero. CLKPCE is cleared by hardware four cycles after it is written or when CLKPS is written. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the CLKPCE bit.RW0CLKPS3Clock Prescaler Select Bit 3RW0CLKPS2Clock Prescaler Select Bit 2These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. The division factors are given a table in the device user guide.. To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits: 1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero. 2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE. Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interruptedRW0CLKPS1Clock Prescaler Select Bit 1These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. The division factors are given a table in the device user guide.. To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits: 1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero. 2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE. Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interruptedRW0CLKPS0Clock Prescaler Select Bit 0These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. The division factors are given a table in the device user guide.. To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits: 1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero. 2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE. Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interruptedRW0DWDRDebug Wire Data Register$2E$4Eio_sreg.bmpNDWDR7Debug Wire Data Register Bit 7RW0DWDR6Debug Wire Data Register Bit 6RW0DWDR5Debug Wire Data Register Bit 5RW0DWDR4Debug Wire Data Register Bit 4RW0DWDR3Debug Wire Data Register Bit 3RW0DWDR2Debug Wire Data Register Bit 2RW0DWDR1Debug Wire Data Register Bit 1RW0DWDR0Debug Wire Data Register Bit 0RW0SPMCSRStore Program Memory Control and Status Register$37$57io_sreg.bmpYCTPBClear Temporary Page BufferIf the CTPB bit is written while filling the temporary page buffer, the temporary page buffer will be cleared and the data will be lost.RW0RFLBRead Fuse and Lock BitsAn LPM instruction within three cycles after RFLB and SPMEN are set in the SPMCSR Register, will read either the Lock bits or the Fuse bits (depending on Z0 in the Zpointer) into the destination register. See “EEPROM Write Prevents Writing to SPMCSR” on page 98 in the data sheet for details.RW0PGWRTPage WriteIf this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a Page Write, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page Write operation.RW0PGERSPage EraseIf this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Erase. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a Page Erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page Write operation.RW0SPMENStore program Memory EnableThis bit enables the SPM instruction for the next four clock cycles. If written to one together with either CTPB, RFLB, PGWRT, or PGERS, the following SPM instruction will have a special meaning, see description above. If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer. The LSB of the Z-pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During Page Erase and Page Write, the SPMEN bit remains high until the operation is completed. Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in the lower five bits will have no effectRW0[PORTB:DDRB:PINB]io_port.bmpAVRSimIOPort.SimIOPortPORTBData Register, Port B$18$38io_port.bmpNPORTB5RW0PORTB4RW0PORTB3RW0PORTB2RW0PORTB1RW0PORTB0RW0DDRBData Direction Register, Port B$17$37io_flag.bmpNDDB5RW0DDB4RW0DDB3RW0DDB2RW0DDB1RW0DDB0RW0PINBInput Pins, Port B$16$36io_port.bmpNPINB5R0PINB4R0PINB3R0PINB2R0PINB1R0PINB0R0[MCUCR:GIMSK:GIFR:PCMSK]io_ext.bmpMCUCRMCU Control Register$35$55io_cpu.bmpYISC01Interrupt Sense Control 0 Bit 1RW0ISC00Interrupt Sense Control 0 Bit 0RW0GIMSKGICRGeneral Interrupt Mask Register$3B$5Bio_flag.bmpYINT0External Interrupt Request 0 EnableWhen the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from program memory address $001. See also “External Interrupts.” • Bits 5..0 - Res: Reserved bitsRW0PCIEPin Change Interrupt EnableRW0GIFRGeneral Interrupt Flag register$3A$5Aio_flag.bmpYINTF0External Interrupt Flag 0When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the interrupt vector at address $001. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. RW0PCIFPin Change Interrupt FlagRW0PCMSKPin Change Enable Mask$15$35io_flag.bmpNPCINT5Pin Change Enable Mask Bit 5RW0PCINT4Pin Change Enable Mask Bit 4RW0PCINT3Pin Change Enable Mask Bit 3RW0PCINT2Pin Change Enable Mask Bit 2RW0PCINT1Pin Change Enable Mask Bit 1RW0PCINT0Pin Change Enable Mask Bit 0RW0[TIMSK0:TIFR0:OCR0A:TCCR0A:TCNT0:TCCR0B:OCR0B:GTCCR]io_timer.bmpAt8pwm0_01TIMSK0Timer/Counter0 Interrupt Mask Register$39$59io_flag.bmpYOCIE0BTimer/Counter0 Output Compare Match B Interrupt EnableRW0OCIE0ATimer/Counter0 Output Compare Match A Interrupt EnableRW0TOIE0Timer/Counter0 Overflow Interrupt EnableRW0TIFR0Timer/Counter0 Interrupt Flag register$38$58io_flag.bmpYOCF0BTimer/Counter0 Output Compare Flag 0BRW0OCF0ATimer/Counter0 Output Compare Flag 0ARW0TOV0Timer/Counter0 Overflow FlagRW0OCR0ATimer/Counter0 Output Compare RegisterThe Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC0 pin.$36$56io_timer.bmpNOCR0_7RW0OCR0_6RW0OCR0_5RW0OCR0_4RW0OCR0_3RW0OCR0_2RW0OCR0_1RW0OCR0_0RW0TCCR0ATimer/Counter Control Register A$2F$4Fio_flag.bmpYCOM0A1Compare Match Output A ModeRW0COM0A0Compare Match Output A ModeRW0COM0B1Compare Match Output B ModeRW0COM0B0Compare Match Output B ModeRW0WGM01Waveform Generation ModeRW0WGM00Waveform Generation ModeRW0TCNT0Timer/Counter0The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT0 register blocks (removes) the compare match on the following timer clock. Modifying the counter (TCNT0) while the counter is running, introduces a risk of missing a compare match between TCNT0 the OCR0 register.$32$52io_timer.bmpNTCNT0_7RW0TCNT0_6RW0TCNT0_5RW0TCNT0_4RW0TCNT0_3RW0TCNT0_2RW0TCNT0_1RW0TCNT0_0RW0TCCR0BTimer/Counter Control Register B$33$53io_flag.bmpYFOC0AForce Output Compare ARW0FOC0BForce Output Compare BRW0WGM02Waveform Generation ModeRW0CS02Clock SelectRW0CS01Clock SelectRW0CS00Clock SelectRW0OCR0BTimer/Counter0 Output Compare RegisterThe Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC0 pin.$29$49io_timer.bmpNOCR0_7RW0OCR0_6RW0OCR0_5RW0OCR0_4RW0OCR0_3RW0OCR0_2RW0OCR0_1RW0OCR0_0RW0GTCCRGeneral Timer Conuter Register$28$48io_timer.bmpYTSMTimer/Counter Synchronization ModeRW0PSR10Prescaler Reset Timer/Counter0RW0[WDTCR]io_watch.bmpWDTCRWatchdog Timer Control Register$21$41io_flag.bmpYWDTIFWatchdog Timeout Interrupt FlagRW0WDTIEWatchdog Timeout Interrupt EnableRW0WDP3Watchdog Timer Prescaler Bit 3RW0WDCEWatchdog Change EnableRW0WDEWatch Dog EnableWhen the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdogRW0WDP2Watch Dog Timer Prescaler bit 2RW0WDP1Watch Dog Timer Prescaler bit 1RW0WDP0Watch Dog Timer Prescaler bit 0RW0[ICE50:SIMULATOR:JTAGICEmkII:STK500:STK500_2:AVRISPmkII:AVRDragon]0x050x0F0x0F0x0F0x050x050x050x050x050x050x050x050x050x0F0x0F0x050x150x140x140x000000A00x000000000x000000000x000000000x0000003F0x000003FF0x000001FF0x000001FF0x000001FF0x000001FF0x000000A00x0000FFFF0x0000003F0x000000000x000000000x000000000x0023FFFF0x00000FFF0x000000600xEF0x6A0xff0x510x6FATtiny13.bin0x020x0010000004000000072 ; INTOSC = 1, INTRC=2;EXTCLK=41 ;NOTUSE = 1, EXTERNAL = 4, INTERNAL = 2 1 00x010x000x0180x800x000010000x00000000SELFPRGEN Fuse 0x000010000x00001000SELFPRGEN Fuse 0x0000000c0x000000006 CK, 14CK0x0000000c0x000000046 CK, 14CK+4ms0x0000000c0x000000086 CK, 14CK+64 ms0x0000000c0x000000006 CK, 14CK0x0000000c0x000000046 CK, 14CK+4ms0x0000000c0x000000086 CK, 14CK+64 ms0x0000000c0x000000006 CK, 14CK0x0000000c0x000000046 CK, 14CK+4ms0x0000000c0x000000086 CK, 14CK+64 ms0x000000030x000000030x000000030x000000019.60x000000030x000000024.80x000000030x000000000x000000200x00000000Watchdog always ON0x000000200x00000020Watchdog disabled0x000001000x00000000RSTDSBL Fuse 0x000001000x00000100RSTDSBL80x000000100x00000000CLKDIV8 Fuse0x000000100x00000010CLKDIV80x000006000x00000600BOD disabled0x000006000x00000400BOD enabled, 1.8 V0x000006000x00000200BOD enabled, 2.7 V0x000006000x00000000BOD enabled, 4.3 VAVRSimCoreV2.SimCoreV2AVRSimMemory8bit.SimMemory8bitAVRSimInterrupt.SimInterrupt0x0407AVRSimIOPort.SimIOPortYAVRSimIOExtInterrupt.SimIOExtInterrupt0x010x3B0x400x3A0x400x160x020x350x03AVRSimIOPinChangeInterrupt.SimIOPinChangeInterrupt0x020x3B0x200x3A0x200x150x160x3fAvrSimIOTim8pwmsync2.tim8pwmsync20x030x060x07PORTBPORTB01PINB2AVRSimAC.SimIOAC0x05AvrSimADC.SimADC0x09AvrMasterTimer.MasterTimer12048:4096:8192:16384:32768:65536:131072:262144:524288:10485760x00080xff0xff0xff0xff0x9007DebugWire0xF8,0x01,0xF0,0x71,0x42,0x83,0xFE,0xAF0x88,0x00,0xB0,0x71,0x00,0x83,0x7C,0xAA0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X000X00,0X00,0X00,0X00,0X00,0X00,0X00,0X000x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x000x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x000x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x000x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x000x000X000X003240x00000x00000x00000x00000x00000x000x4000x0000,320x0020,640x000x080x000x000x000x800xBB,0xFE,0xBB,0xEE,0xBB,0xCC,0xB2,0x0D,0xBC,0x0E,0xB4,0x0E,0xBA,0x0D,0xBB,0xBC,0x99,0xE1,0xBB,0xAC0xB4,0x0E,0x1E0x000x3d0x2E0x000x000x000x000x000x1c0x141010xFF0xFF0xFF012001002532030x53114510x4132100x400x4C0x000x000x000x41450xC10xC20x000x000x0025625644440x4C 0x0C 0x1C 0x2C 0x3C 0x64 0x74 0x66 0x68 0x78 0x68 0x68 0x7A 0x6A 0x68 0x78 0x78 0x7D 0x6D 0x0C 0x80 0x40 0x20 0x10 0x11 0x08 0x04 0x02 0x03 0x08 0x04 0x0010006112510100254000x0B25652560x0525652562525