[ADMIN:CORE:INTERRUPT_VECTOR:MEMORY:PACKAGE:FUSE:PROGRAMMING:LOCKBIT:IO_MODULE:ICE_SETTINGS]ATtiny151.6MHZ196RELEASED$1E$90$06V0EAVRSimCoreV0.SimCoreV0[][][]32$00$1B$1A$1D$1C$1F$1E9$000External Reset, Power-on Reset and Watchdog Reset$001External Interrupt 0$002External Interrupt Request 0$003Timer/Counter1 Compare Match$004Timer/Counter1 Overflow$005Timer/Counter0 Overflow$006EEPROM Ready$007Analog Comparator$008ADC Conversion ReadyAVRSimMemory8bit.SimMemory8bit1024640NA0NA$00$3FNANA$20$5F$3FNA0x010x020x040x080x100x200x400x80$3BNA0x200x40$3ANA0x200x40$39NA0x020x040x40$38NA0x020x040x40$35NA0x010x020x080x100x200x40$34NA0x010x020x040x08$33NA0x010x020x04$32NA0x010x020x040x080x100x200x400x80$31NA0x010x020x040x080x100x200x400x80$30NA0x010x020x040x080x100x200x400x80$2FNA0x010x020x040x080x100x200x400x80$2ENA0x010x020x040x080x100x200x400x80$2DNA0x010x020x040x080x100x200x400x80$2CNA0x010x020x04$21NA0x010x020x040x080x10$1ENA0x010x020x040x080x100x20$1DNA0x010x020x040x080x100x200x400x80$1CNA0x010x020x040x08$18NA$1f0x010x020x040x080x10$17NA$3f0x010x020x040x080x100x20$16NA$3f0x010x020x040x080x100x20$08NA0x010x020x080x100x200x400x80$07NA0x010x020x040x200x400x80$06NA0x010x020x040x080x100x200x400x80$05NA0x010x020x040x080x100x200x400x80$04NA0x010x020x040x080x100x200x400x80[DIP]8[PB5:'RESET:ADC0][PB4:ADC3][PB3:ADC2][GND][PB0:MOSI:AIN0:AREF][PB1:MISO:AIN1:OCP][PB2:SCK:ADC1:T0:INT0][VCC][LOW]960x800x80Brown-out detection level at VCC=2.7 V0x800x00Brown-out detection level at VCC=4.0 V0x400x00Brown-out detection enabled0x200x00Serial program downloading (SPI) enabled0x100x00External reset function of PB5 disabled0x030x03CKSEL=11 Very quickly rising power0x030x02CKSEL=10 Quickly rising power0x030x01CKSEL=01 Slowly rising power0x030x00CKSEL=00 Slowly rising power0,0x20,0x20,WARNING! These fuse settings will disable the ISP interface!0,0x10,0x00,WARNING! Disabling external reset will make the ISP interface inaccessible!0,0x20,0x20,WARNING! These fuse settings will disable the ISP interface!0,0x10,0x00,WARNING! Disabling external reset will make the ISP interface inaccessible!0x00,1.6 MHz02[LB1 = 1 : LB2 = 1] No memory lock features enabled. [LB1 = 0 : LB2 = 1] Further programming of Flash and EEPROM is enabled. [LB1 = 0 : LB2 = 0] Same as previous, but verify is also disabled320x060x06Mode 1: No memory lock features enabled0x060x04Mode 2: Further programming disabled0x060x00Mode 3: Further programming and verification disabledLB1LockbitLB2Lockbit[AD_CONVERTER:ANALOG_COMPARATOR:EEPROM:PORTB:TIMER_COUNTER_0:WATCHDOG:CPU:EXTERNAL_INTERRUPT:TIMER_COUNTER_1][ADMUX:ADCSR:ADCH:ADCL]((IF ADMUX.ADLAR = 1) LINK [ADCH(1:0):ADCL(7:0)]); (IF ADMUX.ADLAR = 0) LINK [ADCH(7:0):ADCL(7:6)]);io_analo.bmpAD Converter Feature list: 10-bit Resolution. 0.5 LSB Integral Non-Linearity. +-2 LSB Absolute Accuracy. TBD - 260 µs Conversion Time. Up to TBD kSPS at maximum resolution. 8 Multiplexed Single Ended Input Channels. 7 Differential input channels (TQFP package only). 2 Differential input channels with optional gain of 10x and 200x (TQFP package only). Optional left adjustment for ADC result readout. 0 - VCC ADC Input Voltage Range. Selectable 2.56 V ADC reference voltage. Free Running or Single Conversion Mode. Interrupt on ADC Conversion Complete. Sleep Mode NoiseADMUXThe ADC multiplexer Selection Register$07NAio_analo.bmpYREFS1Reference Selection Bit 1These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin.RW0REFS0Reference Selection Bit 0These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin.RW0ADLARLeft Adjust ResultThe ADLAR bit affects the presentation of the ADC conversion result in the ADC data register. If ADLAR is cleared, the result is right adjusted. If ADLAR is set, the result is left adjusted. Changing the ADLAR bit will affect the ADC data register immediately, regardless of any ongoing conversions. For a complete description of this bit, see “The ADC Data Register -ADCL and ADCH” on page 198. RW0MUX2Analog Channel and Gain Selection BitsThe value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).RW0MUX1Analog Channel and Gain Selection BitsThe value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).RW0MUX0Analog Channel and Gain Selection BitsThe value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).RW0ADCSRThe ADC Control and Status register$06NAio_flag.bmpYADENADC EnableWriting a logical ‘1’ to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.RW0ADSCADC Start ConversionIn Single Conversion Mode, a logical ‘1’ must be written to this bit to start each conversion. In Free Running Mode, a logical ‘1’ must be written to this bit to start the first conversion. The first time ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, an extended conversion will result. This extended conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. When a dummy conversion precedes a real conversion, ADSC will stay high until the real conversion completes. Writing a 0 to this bit has no effectRW0ADFRADC Free Running SelectWhen this bit is set (one) the ADC operates in Free Running Mode. In this mode, the ADC samples and updates the data registers continuously. Clearing this bit (zero) will terminate Free Running Mode.RW0ADIFADC Interrupt FlagThis bit is set (one) when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set (one). ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a read-modify-write on ADCSR, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used.RW0ADIEADC Interrupt EnableWhen this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Complete Interrupt is activated.RW0ADPS2ADC Prescaler Select BitsThese bits determine the division factor between the XTAL frequency and the input clock to the ADC.RW0ADPS1ADC Prescaler Select BitsThese bits determine the division factor between the XTAL frequency and the input clock to the ADC.RW0ADPS0ADC Prescaler Select BitsThese bits determine the division factor between the XTAL frequency and the input clock to the ADC.RW0ADCHADC Data Register High ByteWhen an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. The selected channel is differential if MUX4..0 are between ‘01000’ and ‘11101’, otherwise the selected channel is single ended. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8 bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUX4..0 bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adju$05NAio_analo.bmpNADCH7ADC Data Register High Byte Bit 7RW0ADCH6ADC Data Register High Byte Bit 6RW0ADCH5ADC Data Register High Byte Bit 5RW0ADCH4ADC Data Register High Byte Bit 4RW0ADCH3ADC Data Register High Byte Bit 3RW0ADCH2ADC Data Register High Byte Bit 2RW0ADCH1ADC Data Register High Byte Bit 1RW0ADCH0ADC Data Register High Byte Bit 0RW0ADCLADC Data Register Low ByteWhen an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. The selected channel is differential if MUX4..0 are between ‘01000’ and ‘11101’, otherwise the selected channel is single ended. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8 bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUX4..0 bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right ad$04NAio_analo.bmpNADCL7ADC Data Register Low Byte Bit 7RW0ADCL6ADC Data Register Low Byte Bit 6RW0ADCL5ADC Data Register Low Byte Bit 5RW0ADCL4ADC Data Register Low Byte Bit 4RW0ADCL3ADC Data Register Low Byte Bit 3RW0ADCL2ADC Data Register Low Byte Bit 2RW0ADCL1ADC Data Register Low Byte Bit 1RW0ADCL0ADC Data Register Low Byte Bit 0RW0[ACSR]io_analo.bmpAlgComp_06ACSRAnalog Comparator Control And Status Register$08NAio_analo.bmpYACDAnalog Comparator DisableWhen this bit is written logic one, the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.RW0ACBGAINBG6Analog Comparator Bandgap SelectWhen this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. See “Internal Voltage Reference” on page 42.RW0ACOAnalog Compare OutputThe output of the analog comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1-2 clock cycles.RNAACIAnalog Comparator Interrupt FlagThis bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hard-ware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.RW0ACIEAnalog Comparator Interrupt EnableWhen the ACIE bit is written logic one and the I-bit in the Status Register is set, the analog comparator interrupt is acti-vated. When written logic zero, the interrupt is disabled.RW0ACIS1Analog Comparator Interrupt Mode Select bit 1These bits determine which comparator events that trigger the Analog Comparator interrupt.RW0ACIS0Analog Comparator Interrupt Mode Select bit 0These bits determine which comparator events that trigger the Analog Comparator interrupt.RW0[EEAR:EEDR:EECR]io_cpu.bmpEEPROM_02.xmlEEAREEPROM Read/Write AccessThe EEPROM access register is accessible in the I/O space. The write access time is in the range of 2.5 - 4ms, depending on the V CC voltages. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains code that writes the EEPROM, some pre-caution must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. CPU operation under these conditions is likely cause the program counter to perform unintentional jumps and eventually execute the EEPROM write code. To secure EEPROM integrity, the user is advised to use an external under-voltage reset circuit in this case. In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction$1ENAio_cpu.bmpNEEAR5EEPROM Read/Write Access bit 5RW0EEAR4EEPROM Read/Write Access bit 4RW0EEAR3EEPROM Read/Write Access bit 3RW0EEAR2EEPROM Read/Write Access bit 2RW0EEAR1EEPROM Read/Write Access bit 1RW0EEAR0EEPROM Read/Write Access bit 0RW0EEDREEPROM Data RegisterFor the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.$1DNAio_cpu.bmpNEEDR7EEPROM Data Register bit 7RW0EEDR6EEPROM Data Register bit 6RW0EEDR5EEPROM Data Register bit 5RW0EEDR4EEPROM Data Register bit 4RW0EEDR3EEPROM Data Register bit 3RW0EEDR2EEPROM Data Register bit 2RW0EEDR1EEPROM Data Register bit 1RW0EEDR0EEPROM Data Register bit 0RW0EECREEPROM Control Register$1CNAio_flag.bmpYEERIEEEProm Ready Interrupt EnableWhen the I-bit in SREG and EERIE are set (one), the EEPROM Ready Interrupt is enabled. When cleared (zero), the interrupt is disabled. The EEPROM Ready Interrupt generates a constant interrupt when EEWE is cleared (zero).RW0EEMWEEEPROM Master Write EnableThe EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set(one) setting EEWE will write data to the EEPROM at the selected address If EEMWE is zero, setting EEWE will have no effect. When EEMWE has been set (one) by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for a EEPROM write procedure.RW0EEWEEEPROM Write EnableThe EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 2 and 3 is unessential): 1. Wait until EEWE becomes zero. 2. Write new EEPROM address to EEARL and EEARH (optional). 3. Write new EEPROM data to EEDR (optional). 4. Write a logical one to the EEMWE bit in EECR (to be able to write a logical one to the EEMWE bit, the EEWE bit mustbewritten to zero in thesamecycle). 5. Within four clock cycles after setting EEMWE, write a logical one to EEWE. When the write access time (typically 2.5 ms at V CC =5Vor 4msatV CC = 2.7V) has elapsed, the EEWE bit is cleared (zero) by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted or two cycles before the next instruction is executed. Caution: An interrupt between step 4 and step 5 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR regis-ter will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the 4 last steps to avoid these problems.RW0EEREEEPROM Read EnableThe EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be set. When the EERE bit is cleared (zero) by hardware, requested data is found in the EEDR register. The EEPROM read access takes one instruction and there is no need to poll the EERE bit. When EERE has been set, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress when new data or address is written to the EEPROM I/O registers, the write operation will be interrupted, and the result is undefined.RW0[PORTB:DDRB:PINB]io_port.bmpAVRSimIOPort.SimIOPortPORTBData Register, Port B$18NAio_port.bmpNPORTB4RW0PORTB3RW0PORTB2RW0PORTB1RW0PORTB0RW0DDRBData Direction Register, Port B$17NAio_flag.bmpNDDB5RW0DDB4RW0DDB3RW0DDB2RW0DDB1RW0DDB0RW0PINBInput Pins, Port B$16NAio_port.bmpNPINB5R0PINB4R0PINB3R0PINB2R0PINB1R0PINB0R0[TIMSK:TIFR:TCCR0:TCNT0]io_timer.bmpt81The 8-bit Timer/Counter0 can select clock source from CK, prescaled CK, or an external pin. In addition it can be stopped as described in “Timer/Counter0 Control Register - TCCR0” on page 35. The overflow status flag is found in “The Timer/Counter Interrupt Flag Register - TIFR” on page 29. Control signals are found in the Timer/Counter0 Control Register - TCCR0. The interrupt enable/disable settings for Timer/Counter0 are found in “The Timer/Counter Interrupt Mask Regis-ter - TIMSK” on page 28. When Timer/Counter0 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. The 8-bit Timer/Counter0 features both a high resolution and a high accuracy usage with the lower prescaling opportuni-ties. Similarly, the high prescaling opportuni ties make the Timer/Counter0 useful for lower speed functions or exact timing functions with infrequent actionsTIMSKTimer/Counter Interrupt Mask Register$39NAio_flag.bmpYTOIE0Timer/Counter0 Overflow Interrupt EnableWhen the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.RW0TIFRTimer/Counter Interrupt Flag register$38NAio_flag.bmpYTOV0Timer/Counter0 Overflow FlagThe bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, and TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed.RW0TCCR0Timer/Counter0 Control Register$33NAio_flag.bmpYCS02Clock Select0 bit 2RW0CS01Clock Select0 bit 1RW0CS00Clock Select0 bit 0RW0TCNT0Timer Counter 0The Timer/Counter0 is realized as an up-counter with read and write access. If the Timer/Counter0 is written and a clock source is present, the Timer/Counter0 continues counting in the clock cycle following the write operation.$32NAio_timer.bmpNTCNT07Timer Counter 0 bit 7RW0TCNT06Timer Counter 0 bit 6RW0TCNT05Timer Counter 0 bit 5RW0TCNT04Timer Counter 0 bit 4RW0TCNT03Timer Counter 0 bit 3RW0TCNT02Timer Counter 0 bit 2RW0TCNT01Timer Counter 0 bit 1RW0TCNT00Timer Counter 0 bit 0RW0[WDTCR]io_watch.bmpWDTCRWatchdog Timer Control Register$21NAio_flag.bmpYWDTOEWDDERWThis bit must be set (one) when the WDE bit is cleared. Otherwise, the watchdog will not be disabled. Once set, hardware will clear this bit to zero after four clock cycles. Refer to the description of the WDE bit for a watchdog disable procedure.RW0WDEWatch Dog EnableWhen the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdogRW0WDP2Watch Dog Timer Prescaler bit 2RW0WDP1Watch Dog Timer Prescaler bit 1RW0WDP0Watch Dog Timer Prescaler bit 0RW0[SREG:MCUCR:MCUSR:OSCCAL]io_cpu.comSREGStatus Register$3FNAio_sreg.bmpYIGlobal Interrupt EnableThe global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable bit is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts.RW0TBit Copy StorageThe bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction.RW0HHalf Carry FlagThe half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed information.RW0SSign BitThe S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruc-tion Set Description for detailed information.RW0VTwo's Complement Overflow FlagThe two’s complement overflow flag V supports two’s complement arithmetics. See the Instruction Set Description for detailed information.RW0NNegative FlagThe negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.RW0ZZero FlagThe zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.RW0CCarry FlagThe carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software.RW0MCUCRMCU Control RegisterThe MCU Control Register contains control bits for general MCU functions.$35NAio_cpu.bmpYPUDPull-up DisableRW0SESleep EnableThe SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmers purpose, it is recommended to set the Sleep Enable SE bit just before the execution of the SLEEP instruction.R0SM1Sleep Mode Select Bit 1RW0SM0Sleep Mode Select Bit 0RW0ISC01Interrupt Sense Control 0 bit 1R0ISC00Interrupt Sense Control 0 bit 0R0MCUSRMCU Status registerThe MCU Status Registerprovides information on which reset source caused a MCU reset.$34NAio_cpu.bmpYWDRFWatchdog Reset FlagRW0BORFBrown-out Reset FlagRW0EXTRFExternal Reset FlagAfter a power-on reset, this bit is undefined (X). It will be set by an external reset. A watchdog reset will leave this bit unchanged.RW0PORFPower-On Reset FlagThis bit is set by a power-on reset. A watchdog reset or an external reset will leave this bit unchangedRW0OSCCALStatus Register$31NAio_sreg.bmpNCAL7Oscillator Calibration Value Bit 7RW0CAL6Oscillator Calibration Value Bit 6RW0CAL5Oscillator Calibration Value Bit 5RW0CAL4Oscillator Calibration Value Bit 4RW0CAL3Oscillator Calibration Value Bit 3RW0CAL2Oscillator Calibration Value Bit 2RW0CAL1Oscillator Calibration Value Bit 1RW0CAL0Oscillator Calibration Value Bit 0RW0[GIMSK:GIFR]io_ext.bmpGIMSKGeneral Interrupt Mask Register$3BNAio_flag.bmpYINT0External Interrupt Request 0 EnableWhen the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from program memory address $001. See also “External Interrupts.” • Bits 5..0 - Res: Reserved bitsRW0PCIEPin Change Interrupt EnableRW0GIFRGeneral Interrupt Flag register$3ANAio_flag.bmpYINTF0External Interrupt Flag 0When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the interrupt vector at address $001. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. RW0PCIFPin Change Interrupt FlagRW0[TCCR1:TCNT1:OCR1A:OCR1B:TIMSK:TIFR:SFIOR]io_timer.bmpt8pwm1_00TCCR1Timer/Counter Control Register$30NAio_flag.bmpYCTC1Clear Timer/Counter on Compare MatchWhen the CTC1 control bit is set (one), Timer/Counter1 is reset to $00 in the CPU clock cycle after a compare match with OCR1A register value. If the control bit is cleared, Timer/Counter1 continues counting and is unaffected by a compare match.RW0PWM1Pulse Width Modulator EnableWhen set (one), this bit enables PWM mode for Timer/Counter1.RW0COM1A1Compare Output Mode, Bit 0The COM1A1 and COM1A0 control bits determine any output pin action following a compare match A in Timer/Counter1. Output pin actions affect pin PB1(OC1A). Since this is an alternative function to an I/O port, the corresponding direction control bit must be set (one) to control an output pin.RW0COM1A0Compare Output Mode, Bit 1The COM1A1 and COM1A0 control bits determine any output pin action following a compare match A in Timer/Counter1. Output pin actions affect pin PB1(OC1A). Since this is an alternative function to an I/O port, the corresponding direction control bit must be set (one) to control an output pin.RW0CS13Clock Select BitsThe Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1.RW0CS12Clock Select BitsThe Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1.RW0CS11Clock Select BitsThe Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1.RW0CS10Clock Select BitsThe Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1.RW0TCNT1Timer/Counter RegisterThe Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT1 register blocks (removes) the compare match on the following timer clock. Modifying the counter (TCNT1) while the counter is running, introduces a risk of missing a compare match between TCNT1 the OCR2 register. $2FNAio_timer.bmpNTCNT1_7Timer/Counter Register Bit 7RW0TCNT1_6Timer/Counter Register Bit 6RW0TCNT1_5Timer/Counter Register Bit 5RW0TCNT1_4Timer/Counter Register Bit 4RW0TCNT1_3Timer/Counter Register Bit 3RW0TCNT1_2Timer/Counter Register Bit 2RW0TCNT1_1Timer/Counter Register Bit 1RW0TCNT1_0Timer/Counter Register Bit 0RW0OCR1AOutput Compare RegisterThe Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT1). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC2 pin.$2ENAio_timer.bmpNOCR1A7Output Compare Register A Bit 7RW0OCR1A6Output Compare Register A Bit 6RW0OCR1A5Output Compare Register A Bit 5RW0OCR1A4Output Compare Register A Bit 4RW0OCR1A3Output Compare Register A Bit 3RW0OCR1A2Output Compare Register A Bit 2RW0OCR1A1Output Compare Register A Bit 1RW0OCR1A0Output Compare Register A Bit 0RW0OCR1BOutput Compare RegisterThe Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT1). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC2 pin.$2DNAio_timer.bmpNOCR1B7Output Compare Register B Bit 7RW0OCR1B6Output Compare Register B Bit 6RW0OCR1B5Output Compare Register B Bit 5RW0OCR1B4Output Compare Register B Bit 4RW0OCR1B3Output Compare Register B Bit 3RW0OCR1B2Output Compare Register B Bit 2RW0OCR1B1Output Compare Register B Bit 1RW0OCR1B0Output Compare Register B Bit 0RW0TIMSKTimer/Counter Interrupt Mask Register$39NAio_flag.bmpYOCIE1AOCIE1A: Timer/Counter1 Output Compare Interrupt EnableWhen the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Compare Match, interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a compare match A in Timer/Counter1 occurs, i.e., when the OCF1A bit is set (one) in the Timer/Counter Interrupt Flag Register (TIFR).RW0TOIE1Timer/Counter1 Overflow Interrupt EnableWhen the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $004) is executed if an overflow in Timer/Counter1 occurs (i.e., when the TOV1 bit is set in the Timer/Counter Interrupt Flag Register [TIFR]).RW0TIFRTimer/Counter Interrupt Flag Register$38NAio_flag.bmpYOCF1ATimer/Counter1 Output Compare Flag 1AThe OCF1A bit is set (one) when compare match occurs between Timer/Counter1 and the data value in OCR1A (Output Compare Register 1A). OCF1A is cleared by hard-ware when executing the corresponding interrupt handling vector. Alternatively, OCF1A is cleared by writing a logical “1” to the flag. When the I-bit in SREG, OCIE1A, and OCF1A are set (one), the Timer/Counter1 compare match A interrupt is executed.RW0TOV1Timer/Counter1 Overflow FlagThe bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logical “1” to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overf low Interrupt Enable) and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed.RW0SFIORSpecial Function IO Register$2CNAio_flag.bmpFOC1AForce Output Compare 1AWriting a logical “1” to this bit forces a change in the compare match output pin PB1 (OC1A) according to the values already set in COM1A1 and COM1A0. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in timer. The automatic action programmed in COM1A1 and COM1A0 happens as if a Compare Match had occurred, but no interrupt is generated and the Timer/Counter1 will not be cleared even if CTC1 is set. The FOC1A bit will always be read as zero. The setting of the FOC1A bit has no effect in PWM modeRW0PSR1Prescaler Reset Timer/Counter1When this bit is set (one) the Timer/Counter1 prescaler will be reset. The bit will be cleared by hardware after the operation is performed. Writing a “0” to this bit will have no effect. This bit will always be read as zero.RW0PSR0Prescaler Reset Timer/Counter0When this bit is set (one) the Timer/Counter0 prescaler will be reset. The bit will be cleared by hardware after the operation is performed. Writing a “0” to this bit will have no effect. This bit will always be read as zero.RW0[SIMULATOR:STK500:STK500_2:AVRISPmkII]AVRSimCoreV2.SimCoreV2AVRSimMemory8bit.SimMemory8bitAVRSimInterrupt.SimInterrupt0x0607AVRSimIOPort.SimIOPort0xffNAVRSimIOExtInterrupt.SimIOExtInterrupt0x010x3b0x400x3a0x400x160x040x350x03AVRSimIOPinChangeInterrupt.SimIOPinChangeInterrupt0x020x3B0x200x3A0x200x000x160x3FAVRSimIOTimert81.SimIOTimert810x050x160x04AVRSimIOtimer8t15.SimIOtimer8t15AVRSimAC.SimIOAC0x07AVRSimADC.SimADC0x080x131010xFF0xFF0xFF012001002532030x531110000x04128100x400x000x200xFF0x000x0464100xC00x000xA00xFF0xFF25625644440x4C 0x0C 0x1C 0x2C 0x3C 0x64 0x74 0x00 0x68 0x78 0x68 0x68 0x00 0x00 0x68 0x78 0x78 0x00 0x6D 0x0C 0x80 0x40 0x20 0x10 0x11 0x08 0x04 0x02 0x03 0x08 0x04 0x001005616125101002540002565256025652562525