[ADMIN:CORE:INTERRUPT_VECTOR:POWER:PROGVOLT:PACKAGE:MEMORY:FUSE:PROGRAMMING:LOCKBIT:IO_MODULE:ICE_SETTINGS]ATtiny231316MHZ201RELEASED$1E$91$0AV2AVRSimCoreV2.SimCoreV2[lpm rd,z+][][]32$00$1B$1A$1D$1C$1F$1E19$000External Reset, Power-on Reset and Watchdog Reset$001External Interrupt Request 0$002External Interrupt Request 1$003Timer/Counter1 Capture Event$004TIMER1 COMPTimer/Counter1 Compare Match A$005Timer/Counter1 Overflow$006Timer/Counter0 Overflow$007USART0, RXUSART, Rx Complete$008USART0, UDREUSART Data Register Empty$009USART0, TXUSART, Tx Complete$00AAnalog Comparator$00B$00C$00D$00E$00FUSI Start Condition$010USI Overflow$11$012Watchdog Timer Overflow4MHz25C2.8mA0.8mA<1uA2.76.04.06.0[DIP:SOIC]20['RESET][PD0:RXD][PD1:TXD][XTAL2:PA1][XTAL1:PA0][PD2:INT0:XCK:CKOUT][PD3:INT1][PD4:T0][PD5:T1:OC0B][GND][PD6:ICP][PB0:AIN0][PB1:AIN1][PB2:OC0A][PB3:OC1A][PB4:OC1B][PB5:MOSI:DI][PB6:MISO:DO][PB7:SCK:SCL]VCC20['RESET][PD0:RXD][PD1:TXD][XTAL2:PA1][XTAL1:PA0][PD2:INT0:XCK:CKOUT][PD3:INT1][PD4:T0][PD5:T1:OC0B][GND][PD6:ICP][PB0:AIN0][PB1:AIN1][PB2:OC0A][PB3:OC1A][PB4:OC1B][PB5:MOSI:DI][PB6:MISO:DO][PB7:SCK:SCL]VCCAVRSimMemory8bit.SimMemory8bit2048128128$600NA$00$3FNANA$20$5F$3F$5F0x010x020x040x080x100x200x400x80$3D$5D0x010x020x040x080x100x200x400x80$3C$5C0x010x020x040x080x100x200x400x80$3B$5B0x200x400x80$3A$5A0x200x400x80$39$590x010x020x040x080x200x400x80$38$580x010x020x040x080x200x400x80$37$570x010x020x040x080x10$36$560x010x020x040x080x100x200x400x80$35$550x010x020x040x080x100x200x400x80$34$540x010x020x040x08$33$530x010x020x040x080x400x80$32$520x010x020x040x080x100x200x400x80$31$510x010x020x040x080x100x200x40$30$500x010x020x100x200x400x80$2F$4F0x010x020x100x200x400x80$2E$4E0x010x020x040x080x100x400x80$2D$4D0x010x020x040x080x100x200x400x80$2C$4C0x010x020x040x080x100x200x400x80$2B$4B0x010x020x040x080x100x200x400x80$2A$4A0x010x020x040x080x100x200x400x80$29$490x010x020x040x080x100x200x400x80$28$480x010x020x040x080x100x200x400x80$26$460x010x020x040x080x80$25$450x010x020x040x080x100x200x400x80$24$440x010x020x040x080x100x200x400x80$23$430x01$22$420x400x80$21$410x010x020x040x080x100x200x400x80$20$400x010x020x040x080x100x200x400x80$1E$3E0x010x020x040x080x100x200x40$1D$3D0x010x020x040x080x100x200x400x80$1C$3C0x010x020x040x080x100x20$1B$3B0x010x020x04$1A$3A0x010x020x04$19$390x010x020x04$18$38$ff0x010x020x040x080x100x200x400x80$17$370x010x020x040x080x100x200x400x80$16$360x010x020x040x080x100x200x400x80$15$350x010x020x040x080x100x200x400x80$14$340x010x020x040x080x100x200x400x80$13$330x010x020x040x080x100x200x400x80$12$32$7f0x010x020x040x080x100x200x40$11$310x010x020x040x080x100x200x40$10$300x010x020x040x080x100x200x40$0F$2F0x010x020x040x080x100x200x400x80$0E$2E0x010x020x040x080x100x200x400x80$0D$2D0x010x020x040x080x100x200x400x80$0C$2C0x010x020x040x080x100x200x400x80$0B$02B0x010x020x040x080x100x200x400x80$0A$02A0x010x020x040x080x100x200x400x80$09$290x010x020x040x080x100x200x400x80$08$280x010x020x040x080x100x200x400x80$03$230x010x020x040x080x100x200x40$02$220x010x020x040x08$01$210x010x02$0$3ff$0$016[LOW:HIGH:EXTENDED]8CKDIV8Divide clock by 80CKOUTClock output1SUT1Select start-up time1SUT0Select start-up time0CKSEL3Select Clock Source0CKSEL2Select Clock Source0CKSEL1Select Clock Source1CKSEL0Select Clock Source0460x800x00Divide clock by 8 internally; [CKDIV8=0]0x400x00Clock output on PORTD2; [CKOUT=0]0x3F0x00Ext. Clock; Start-up time: 14 CK + 0 ms; [CKSEL=0000 SUT=00]0x3F0x10Ext. Clock; Start-up time: 14 CK + 4.1 ms; [CKSEL=0000 SUT=01]0x3F0x20Ext. Clock; Start-up time: 14 CK + 65 ms; [CKSEL=0000 SUT=10]0x3F0x02Int. RC Osc. 4 MHz; Start-up time: 14 CK + 0 ms; [CKSEL=0010 SUT=00]0x3F0x12Int. RC Osc. 4 MHz; Start-up time: 14 CK + 4.1 ms; [CKSEL=0010 SUT=01]0x3F0x22Int. RC Osc. 4 MHz; Start-up time: 14 CK + 65 ms; [CKSEL=0010 SUT=10]0x3F0x04Int. RC Osc. 8 MHz; Start-up time: 14 CK + 0 ms; [CKSEL=0100 SUT=00]0x3F0x14Int. RC Osc. 8 MHz; Start-up time: 14 CK + 4.1 ms; [CKSEL=0100 SUT=01]0x3F0x24Int. RC Osc. 8 MHz; Start-up time: 14 CK + 65 ms; [CKSEL=0100 SUT=10]; default value0x3F0x06Int. RC Osc. 128 kHz; Start-up time: 14 CK + 0 ms; [CKSEL=0110 SUT=00] 0x3F0x16Int. RC Osc. 128 kHz; Start-up time: 14 CK + 4 ms; [CKSEL=0110 SUT=01] 0x3F0x26Int. RC Osc. 128 kHz; Start-up time: 14 CK + 64 ms;[CKSEL=0110 SUT=10]0x3F0x08Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 14 CK + 4.1 ms; [CKSEL=1000 SUT=00]0x3F0x18Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 14 CK + 65 ms; [CKSEL=1000 SUT=01]0x3F0x28Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 14 CK + 0 ms; [CKSEL=1000 SUT=10]0x3F0x38Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 14 CK + 4.1 ms; [CKSEL=1000 SUT=11]0x3F0x09Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 14 CK + 65 ms; [CKSEL=1001 SUT=00]0x3F0x19Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 14 CK + 0 ms; [CKSEL=1001 SUT=01]0x3F0x29Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 14 CK + 4.1 ms; [CKSEL=1001 SUT=10]0x3F0x39Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 14 CK + 65 ms; [CKSEL=1001 SUT=11]0x3F0x0AExt. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 14 CK + 4.1 ms; [CKSEL=1010 SUT=00]0x3F0x1AExt. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 14 CK + 65 ms; [CKSEL=1010 SUT=01]0x3F0x2AExt. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 14 CK + 0 ms; [CKSEL=1010 SUT=10]0x3F0x3AExt. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 14 CK + 4.1 ms; [CKSEL=1010 SUT=11]0x3F0x0BExt. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 14 CK + 65 ms; [CKSEL=1011 SUT=00]0x3F0x1BExt. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 14 CK + 0 ms; [CKSEL=1011 SUT=01]0x3F0x2BExt. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 14 CK + 4.1 ms; [CKSEL=1011 SUT=10]0x3F0x3BExt. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 14 CK + 65 ms; [CKSEL=1011 SUT=11]0x3F0x0CExt. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 14 CK + 4.1 ms; [CKSEL=1100 SUT=00]0x3F0x1CExt. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 14 CK + 65 ms; [CKSEL=1100 SUT=01]0x3F0x2CExt. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 14 CK + 0 ms; [CKSEL=1100 SUT=10]0x3F0x3CExt. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 14 CK + 4.1 ms; [CKSEL=1100 SUT=11]0x3F0x0DExt. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 14 CK + 65 ms; [CKSEL=1101 SUT=00]0x3F0x1DExt. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 14 CK + 0 ms; [CKSEL=1101 SUT=01]0x3F0x2DExt. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 14 CK + 4.1 ms; [CKSEL=1101 SUT=10]0x3F0x3DExt. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 14 CK + 65 ms; [CKSEL=1101 SUT=11]0x3F0x0EExt. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 14 CK + 4.1 ms; [CKSEL=1110 SUT=00]0x3F0x1EExt. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 14 CK + 65 ms; [CKSEL=1110 SUT=01]0x3F0x2EExt. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 14 CK + 0 ms; [CKSEL=1110 SUT=10]0x3F0x3EExt. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 14 CK + 4.1 ms; [CKSEL=1110 SUT=11]0x3F0x0FExt. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 14 CK + 65 ms; [CKSEL=1111 SUT=00]0x3F0x1FExt. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 14 CK + 0 ms; [CKSEL=1111 SUT=01]0x3F0x2FExt. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 14 CK + 4.1 ms; [CKSEL=1111 SUT=10]0x3F0x3FExt. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 14 CK + 65 ms; [CKSEL=1111 SUT=11]8RSTDISBLExternal reset disable1DWENdebugWIRE Enable1SPIENEnable Serial programming and Data Downloading0WDTONWatchdog Timer Always On1EESAVEEEPROM memory is preserved through chip erase1BODLEVEL2Brown-out Detector trigger level1BODLEVEL1Brown-out Detector trigger level1BODLEVEL0Brown-out Detector trigger level190x800x00Debug Wire enable; [DWEN=0]0x400x00Preserve EEPROM memory through the Chip Erase cycle; [EESAVE=0]0x200x00Serial program downloading (SPI) enabled; [SPIEN=0]0x100x00Watch-dog Timer always on; [WDTON=0]0x0E0x08Brown-out detection level at VCC=4.3 V; [BODLEVEL=100]0x0E0x0ABrown-out detection level at VCC=2.7 V; [BODLEVEL=101]0x0E0x0CBrown-out detection level at VCC=1.8 V; [BODLEVEL=110]0x0E0x0EBrown-out detection disabled; [BODLEVEL=111]0x010x00Reset Disabled (Enable PA2 as i/o pin); [RSTDISBL=0]1SELFPRGENSelf Programming Enable110x010x00Self programming enable; [SELFPRGEN=0]0xff,0xdf0xff,0xdf1,0x20,0x20,WARNING! These fuse settings will disable the ISP interface!1,0x80,0x00,WARNING! Enabling DEBUGWIRE will make the ISP interface inaccessible!1,0x01,0x00,WARNING! Disabling external reset will make the ISP interface inaccessible!0,0x3F,0x06,WARNING! Using this clock option together with the CKDIV8 fuse will disable further programming!0,0x3F,0x16,WARNING! Using this clock option together with the CKDIV8 fuse will disable further programming!0,0x3F,0x26,WARNING! Using this clock option together with the CKDIV8 fuse will disable further programming!1,0x20,0x20,WARNING! These fuse settings will disable the ISP interface!1,0x80,0x00,WARNING! Enabling DEBUGWIRE will make the ISP interface inaccessible!1,0x01,0x00,WARNING! Disabling external reset will make the ISP interface inaccessible!0,0x3F,0x06,WARNING! Using this clock option together with the CKDIV8 fuse will disable further programming!0,0x3F,0x16,WARNING! Using this clock option together with the CKDIV8 fuse will disable further programming!0,0x3F,0x26,WARNING! Using this clock option together with the CKDIV8 fuse will disable further programming!0x00,8 MHz0x01,4 MHz324[LB1 = 1 : LB2 = 1] No memory lock features enabled. [LB1 = 0 : LB2 = 1] Further programming of Flash and EEPROM is enabled. [LB1 = 0 : LB2 = 0] Same as previous, but verify is also disabled320x030x03Mode 1: No memory lock features enabled0x030x02Mode 2: Further programming disabled0x030x00Mode 3: Further programming and verification disabledLB1LockbitLB2Lockbit[PORTB:TIMER_COUNTER_0:TIMER_COUNTER_1:WATCHDOG:EXTERNAL_INTERRUPT:USART:ANALOG_COMPARATOR:PORTD:EEPROM:PORTA:CPU:USI][PORTB:DDRB:PINB]io_port.bmpAVRSimIOPort.SimIOPortPORTBPort B Data Register$18$38io_port.bmpNPORTB7Port B Data Register bit 7RW0PORTB6Port B Data Register bit 6RW0PORTB5Port B Data Register bit 5RW0PORTB4Port B Data Register bit 4RW0PORTB3Port B Data Register bit 3RW0PORTB2Port B Data Register bit 2RW0PORTB1Port B Data Register bit 1RW0PORTB0Port B Data Register bit 0RW0DDRBPort B Data Direction Register$17$37io_flag.bmpNDDB7Port B Data Direction Register bit 7RW0DDB6Port B Data Direction Register bit 6RW0DDB5Port B Data Direction Register bit 5RW0DDB4Port B Data Direction Register bit 4RW0DDB3Port B Data Direction Register bit 3RW0DDB2Port B Data Direction Register bit 2RW0DDB1Port B Data Direction Register bit 1RW0DDB0Port B Data Direction Register bit 0RW0PINBPort B Input PinsThe Port B Input Pins address - PINB - is not a register, and this address enables access to the physical value on each Port B pin. When reading PORTB, the Port B Data Latch is read, and when reading PINB, the logical values present on the pins are read.$16$36io_port.bmpNPINB7Port B Input Pins bit 7R0PINB6Port B Input Pins bit 6R0PINB5Port B Input Pins bit 5R0PINB4Port B Input Pins bit 4R0PINB3Port B Input Pins bit 3R0PINB2Port B Input Pins bit 2R0PINB1Port B Input Pins bit 1R0PINB0Port B Input Pins bit 0R0[TIMSK:TIFR:OCR0B:OCR0A:TCCR0A:TCNT0:TCCR0B]io_timer.bmpAt8pwm0_11TIMSKTimer/Counter Interrupt Mask Register$39$59io_flag.bmpYOCIE0BTimer/Counter0 Output Compare Match B Interrupt EnableRW0TOIE0Timer/Counter0 Overflow Interrupt EnableRW0OCIE0ATimer/Counter0 Output Compare Match A Interrupt EnableRW0TIFRTimer/Counter Interrupt Flag register$38$58io_flag.bmpYOCF0BTimer/Counter0 Output Compare Flag 0BRW0TOV0Timer/Counter0 Overflow FlagRW0OCF0ATimer/Counter0 Output Compare Flag 0ARW0OCR0BTimer/Counter0 Output Compare RegisterThe Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC0 pin.$3C$5Cio_timer.bmpNOCR0_7RW0OCR0_6RW0OCR0_5RW0OCR0_4RW0OCR0_3RW0OCR0_2RW0OCR0_1RW0OCR0_0RW0OCR0ATimer/Counter0 Output Compare RegisterThe Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC0 pin.$36$56io_timer.bmpNOCR0_7RW0OCR0_6RW0OCR0_5RW0OCR0_4RW0OCR0_3RW0OCR0_2RW0OCR0_1RW0OCR0_0RW0TCCR0ATimer/Counter Control Register A$30$50io_flag.bmpYCOM0A1Compare Match Output A ModeControls Output Compare Pin A behaviour. Please refer to datasheet.RW0COM0A0Compare Match Output A ModeControls Output Compare Pin A behaviour. Please refer to datasheet.RW0COM0B1Compare Match Output B ModeControls Output Compare Pin B behaviour. Please refer to datasheet.RW0COM0B0Compare Match Output B ModeControls Output Compare Pin B behaviour. Please refer to datasheet.RW0WGM01Waveform Generation ModeControls the Waveform Generation Mode, please refer to datasheet for further details.RW0WGM00Waveform Generation ModeControls the Waveform Generation Mode, please refer to datasheet for further details.RW0TCNT0Timer/Counter0The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT0 register blocks (removes) the compare match on the following timer clock. Modifying the counter (TCNT0) while the counter is running, introduces a risk of missing a compare match between TCNT0 the OCR0 register.$32$52io_timer.bmpNTCNT0_7RW0TCNT0_6RW0TCNT0_5RW0TCNT0_4RW0TCNT0_3RW0TCNT0_2RW0TCNT0_1RW0TCNT0_0RW0TCCR0BTCCR0Timer/Counter Control Register B$33$53io_flag.bmpYFOC0AForce Output Compare BRW0FOC0BForce Output Compare BW0WGM02RW0CS02Clock SelectRW0CS01Clock SelectRW0CS00Clock SelectRW0[TIMSK:TIFR:TCCR1A:TCCR1B:TCCR1C:TCNT1H:TCNT1L:OCR1AH:OCR1AL:OCR1BH:OCR1BL:ICR1H:ICR1L]
[TCNT1H:TCNT1L];[OCR1AH:OCR1AL];[OCR1BH:OCR1BL];[ICR1H:ICR1L]
io_timer.bmpt16pwm1_13.xmlTIMSKTimer/Counter Interrupt Mask Register$39$59io_flag.bmpYTOIE1Timer/Counter1 Overflow Interrupt EnableWhen the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.RW0OCIE1ATimer/Counter1 Output CompareA Match Interrupt EnableWhen the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a CompareA match in Timer/Counter1 occurs, i.e., when the OCF1A bit is set in the Timer/Counter Interrupt Flag Register - TIFR.RW0OCIE1BTimer/Counter1 Output CompareB Match Interrupt EnableWhen the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt is executed if a CompareB match in Timer/Counter1 occurs, i.e., when the OCF1B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.RW0ICIE1TICIETimer/Counter1 Input Capture Interrupt EnableWhen the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on pin ICP, i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.RW0TIFRTimer/Counter Interrupt Flag register$38$58io_flag.bmpYTOV1Timer/Counter1 Overflow FlagThe TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the cor-responding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter1 changes counting direction at $0000.RW0OCF1AOutput Compare Flag 1AThe OCF1A bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare match InterruptA Enable), and the OCF1A are set (one), the Timer/Counter1 Compare A match Interrupt is executed. RW0OCF1BOutput Compare Flag 1BThe OCF1B bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1B - Output Compare Register 1B. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare match InterruptB Enable), and the OCF1B are set (one), the Timer/Counter1 Compare B match Interrupt is executed. RW0ICF1Input Capture Flag 1The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to the input capture register - ICR1. ICF1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF1 is cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable), and ICF1 are set (one), the Timer/Counter1 Capture Interrupt is executed. RW0TCCR1ATimer/Counter1 Control Register A$2F$4Fio_flag.bmpYCOM1A1Compare Output Mode 1A, bit 1The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA pin 1. This is an alternative function to an I/O port and the corresponding direction control bit must be set (one) to control the output pin. The control configuration is shown in the databook. RW0COM1A0Comparet Ouput Mode 1A, bit 0The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA pin 1. This is an alternative function to an I/O port and the corresponding direction control bit must be set (one) to control the output pin. The control configuration is shown in the databook. RW0COM1B1Compare Output Mode 1B, bit 1RW0COM1B0Comparet Ouput Mode 1B, bit 0RW0WGM11PWM11Pulse Width Modulator Select Bit 1RW0WGM10PWM10Pulse Width Modulator Select Bit 0RW0TCCR1BTimer/Counter1 Control Register B$2E$4Eio_flag.bmpYICNC1Input Capture 1 Noise CancelerWhen the ICNC1 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the ICP - input capture pin - as specified. When the ICNC1 bit is set (one), four successive samples are measures on the ICP - input capture pin, and all samples must be high/low according to the input capture trigger specification in the ICES1 bit. The actual sampling frequency is XTAL clock frequency.RW0ICES1Input Capture 1 Edge SelectWhile the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the falling edge of the input capture pin - ICP. While the ICES1 bit is set (one), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the rising edge of the input capture pin - ICP.RW0WGM13Waveform Generation Mode Bit 3RW0WGM12CTC1Waveform Generation Mode Bit 2RW0CS12Clock Select1 bit 2RW0CS11Clock Select 1 bit 1RW0CS10Clock Select bit 0RW0TCCR1CTimer/Counter1 Control Register C$22$42io_flag.bmpYFOC1AForce Output Compare for Channel AThe FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM mode. However, for ensuring compatibility with future devices, these bits must be set to zero when TCCR1A is written when operating in a PWM mode. When writing a logical one to the FOC1A/FOC1B bit, an immediate compare match is forced on the Waveform Generation unit. The OC1A/OC1B output is changed according to its COM1x1:0 bits setting. Note that the FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the COM1x1:0 bits that determine the effect of the forced compare. A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zeroRW0FOC1BForce Output Compare for Channel BThe FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM mode. However, for ensuring compatibility with future devices, these bits must be set to zero when TCCR1A is written when operating in a PWM mode. When writing a logical one to the FOC1A/FOC1B bit, an immediate compare match is forced on the Waveform Generation unit. The OC1A/OC1B output is changed according to its COM1x1:0 bits setting. Note that the FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the COM1x1:0 bits that determine the effect of the forced compare. A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zeroRW0TCNT1HTimer/Counter1 High ByteThis 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR1A, OCR1B and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt ro$2D$4Dio_timer.bmpNTCNT1H7Timer/Counter1 High Byte bit 7RW0TCNT1H6Timer/Counter1 High Byte bit 6RW0TCNT1H5Timer/Counter1 High Byte bit 5RW0TCNT1H4Timer/Counter1 High Byte bit 4RW0TCNT1H3Timer/Counter1 High Byte bit 3RW0TCNT1H2Timer/Counter1 High Byte bit 2RW0TCNT1H1Timer/Counter1 High Byte bit 1RW0TCNT1H0Timer/Counter1 High Byte bit 0RW0TCNT1LTimer/Counter1 Low ByteThis 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR1A, OCR1B and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrup$2C$4Cio_timer.bmpNTCNT1L7Timer/Counter1 Low Byte bit 7RW0TCNT1L6Timer/Counter1 Low Byte bit 6RW0TCNT1L5Timer/Counter1 Low Byte bit 5RW0TCNT1L4Timer/Counter1 Low Byte bit 4RW0TCNT1L3Timer/Counter1 Low Byte bit 3RW0TCNT1L2Timer/Counter1 Low Byte bit 2RW0TCNT1L1Timer/Counter1 Low Byte bit 1RW0TCNT1L0Timer/Counter1 Low Byte bit 0RW0OCR1AHTimer/Counter1 Outbut Compare Register High ByteThe output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt$2B$4Bio_timer.bmpNOCR1AH7Timer/Counter1 Outbut Compare Register High Byte bit 7RW0OCR1AH6Timer/Counter1 Outbut Compare Register High Byte bit 6RW0OCR1AH5Timer/Counter1 Outbut Compare Register High Byte bit 5RW0OCR1AH4Timer/Counter1 Outbut Compare Register High Byte bit 4RW0OCR1AH3Timer/Counter1 Outbut Compare Register High Byte bit 3RW0OCR1AH2Timer/Counter1 Outbut Compare Register High Byte bit 2RW0OCR1AH1Timer/Counter1 Outbut Compare Register High Byte bit 1RW0OCR1AH0Timer/Counter1 Outbut Compare Register High Byte bit 0RW0OCR1ALTimer/Counter1 Outbut Compare Register Low ByteThe output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interru$2A$4Aio_timer.bmpNOCR1AL7Timer/Counter1 Outbut Compare Register Low Byte Bit 7RW0OCR1AL6Timer/Counter1 Outbut Compare Register Low Byte Bit 6RW0OCR1AL5Timer/Counter1 Outbut Compare Register Low Byte Bit 5RW0OCR1AL4Timer/Counter1 Outbut Compare Register Low Byte Bit 4RW0OCR1AL3Timer/Counter1 Outbut Compare Register Low Byte Bit 3RW0OCR1AL2Timer/Counter1 Outbut Compare Register Low Byte Bit 2RW0OCR1AL1Timer/Counter1 Outbut Compare Register Low Byte Bit 1RW0OCR1AL0Timer/Counter1 Outbut Compare Register Low Byte Bit 0RW0OCR1BHTimer/Counter1 Outbut Compare Register High ByteThe output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrup$29$49io_timer.bmpNOCR1AH7Timer/Counter1 Outbut Compare Register High Byte bit 7RW0OCR1AH6Timer/Counter1 Outbut Compare Register High Byte bit 6RW0OCR1AH5Timer/Counter1 Outbut Compare Register High Byte bit 5RW0OCR1AH4Timer/Counter1 Outbut Compare Register High Byte bit 4RW0OCR1AH3Timer/Counter1 Outbut Compare Register High Byte bit 3RW0OCR1AH2Timer/Counter1 Outbut Compare Register High Byte bit 2RW0OCR1AH1Timer/Counter1 Outbut Compare Register High Byte bit 1RW0OCR1AH0Timer/Counter1 Outbut Compare Register High Byte bit 0RW0OCR1BLTimer/Counter1 Output Compare Register Low ByteThe output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interru$28$48io_timer.bmpNOCR1AL7Timer/Counter1 Outbut Compare Register Low Byte Bit 7RW0OCR1AL6Timer/Counter1 Outbut Compare Register Low Byte Bit 6RW0OCR1AL5Timer/Counter1 Outbut Compare Register Low Byte Bit 5RW0OCR1AL4Timer/Counter1 Outbut Compare Register Low Byte Bit 4RW0OCR1AL3Timer/Counter1 Outbut Compare Register Low Byte Bit 3RW0OCR1AL2Timer/Counter1 Outbut Compare Register Low Byte Bit 2RW0OCR1AL1Timer/Counter1 Outbut Compare Register Low Byte Bit 1RW0OCR1AL0Timer/Counter1 Outbut Compare Register Low Byte Bit 0RW0ICR1HTimer/Counter1 Input Capture Register High ByteThe input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES1) of the signal at the input capture pin -ICP - is detected, the current value of the Timer/Counter1 is transferred to the Input Capture Register - ICR1. At the same time, the input capture flag - ICF1 - is set (one). Since the Input Capture Register - ICR1 - is a 16-bit register, a temporary register TEMP is used when ICR1 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR1L, the data is sent to the CPU and the data of the high byte ICR1H is placed in the TEMP register. When the CPU reads the data in the high byte ICR1H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR1L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT1, OCR1A and OCR1B. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrup$25$45io_timer.bmpNICR1H7Timer/Counter1 Input Capture Register High Byte bit 7RW0ICR1H6Timer/Counter1 Input Capture Register High Byte bit 6R0ICR1H5Timer/Counter1 Input Capture Register High Byte bit 5R0ICR1H4Timer/Counter1 Input Capture Register High Byte bit 4R0ICR1H3Timer/Counter1 Input Capture Register High Byte bit 3R0ICR1H2Timer/Counter1 Input Capture Register High Byte bit 2R0ICR1H1Timer/Counter1 Input Capture Register High Byte bit 1R0ICR1H0Timer/Counter1 Input Capture Register High Byte bit 0R0ICR1LTimer/Counter1 Input Capture Register Low ByteThe input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES1) of the signal at the input capture pin -ICP - is detected, the current value of the Timer/Counter1 is transferred to the Input Capture Register - ICR1. At the same time, the input capture flag - ICF1 - is set (one). Since the Input Capture Register - ICR1 - is a 16-bit register, a temporary register TEMP is used when ICR1 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR1L, the data is sent to the CPU and the data of the high byte ICR1H is placed in the TEMP register. When the CPU reads the data in the high byte ICR1H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR1L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT1, OCR1A and OCR1B. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within inte$24$44io_timer.bmpNICR1L7Timer/Counter1 Input Capture Register Low Byte bit 7R0ICR1L6Timer/Counter1 Input Capture Register Low Byte bit 6R0ICR1L5Timer/Counter1 Input Capture Register Low Byte bit 5R0ICR1L4Timer/Counter1 Input Capture Register Low Byte bit 4R0ICR1L3Timer/Counter1 Input Capture Register Low Byte bit 3R0ICR1L2Timer/Counter1 Input Capture Register Low Byte bit 2R0ICR1L1Timer/Counter1 Input Capture Register Low Byte bit 1R0ICR1L0Timer/Counter1 Input Capture Register Low Byte bit 0R0[WDTCR]io_watch.bmpWDTCRWDTCSRWatchdog Timer Control Register$21$41io_flag.bmpYWDIFWatchdog Timeout Interrupt FlagRW0WDIEWatchdog Timeout Interrupt EnableRW0WDP3Watchdog Timer Prescaler Bit 3RW0WDCEWDTOEWatchdog Change EnableRW0WDEWatch Dog EnableWhen the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdogRW0WDP2Watch Dog Timer Prescaler bit 2RW0WDP1Watch Dog Timer Prescaler bit 1RW0WDP0Watch Dog Timer Prescaler bit 0RW0[GIMSK:EIFR]io_ext.bmpGIMSKGeneral Interrupt Mask Register$3B$5Bio_flag.bmpYINT1External Interrupt Request 1 EnableWhen the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT1 pin or level sensed. Activity on the pin will cause an interrupt request even if INT1 is configured as an output. The corresponding interrupt of External Interrupt Request 1 is executed from program memory address $002. See also “External Interrupts”.RW0INT0External Interrupt Request 0 EnableWhen the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from program memory address $001. See also “External Interrupts.” • Bits 5..0 - Res: Reserved bitsRW0PCIERW0EIFRGIFRExtended Interrupt Flag Register$3A$5Aio_flag.bmpYINTF1External Interrupt Flag 1When an event on the INT1 pin triggers an interrupt request, INTF1 becomes set (one). If the I-bit in SREG and the INT1 bit in GIMSK are set (one), the MCU will jump to the interrupt vector at address $002. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.RW0INTF0External Interrupt Flag 0When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the interrupt vector at address $001. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. RW0PCIFRW0[UDR:UCSRA:UCSRB:UCSRC:UBRRH:UBRRL]
[UBRRH:UBRRL]
io_com.bmpThe Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. The main features are: • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • High Resolution Baud Rate Generator • Supports Serial Frames with 5, 6, 7, 8 or 9 Data Bits and 1 or 2 Stop Bits • Odd or Even Parity Generation and Parity Check Supported by Hardware • Data OverRun Detection • Framing Error Detection • Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter • Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete • Multi-processor Communication Mode • Double Speed Asynchronous CommUDRUSART I/O Data RegisterThe UDR0 register is actually two physically separate registers sharing the same I/O address. When writing to the register, the USART Transmit Data register is written. When reading from UDR0, the USART Receive Data register is read.$0C$2Cio_com.bmpNUDR7USART I/O Data Register bit 7RW0UDR6USART I/O Data Register bit 6RW0UDR5USART I/O Data Register bit 5RW0UDR4USART I/O Data Register bit 4RW0UDR3USART I/O Data Register bit 3RW0UDR2USART I/O Data Register bit 2RW0UDR1USART I/O Data Register bit 1RW0UDR0USART I/O Data Register bit 0RW0UCSRAUSRUSART Control and Status Register A$0B$02Bio_flag.bmpYRXCUSART Receive CompleteThis bit is set (one) when a received character is transferred from the Receiver Shift register to UDR0. The bit is set regard-less of any detected framing errors. When the RXCIE bit in UCR is set, the USART Receive Complete interrupt will be executed when RXC is set(one). RXC is cleared by reading UDR0. When interrupt-driven data reception is used, the USART Receive Complete Interrupt routine must read UDRin order to clear RXC, otherwise a new interrupt will occur once the interrupt routine terminates.R0TXCUSART Transmitt CompleteThis bit is set (one) when the entire character (including the stop bit) in the Transmit Shift register has been shifted out and no new data has been written to UDR0. This flag is especially useful in half-duplex communications interfaces, where a transmitting application must enter receive mode and free the communications bus immediately after completing the transmission. When the TXCIE bit in UCR is set, setting of TXC causes the USART Transmit Complete interrupt to be executed. TXC is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the TXC bit is cleared (zero) by writing a logical one to the biRW0UDREUSART Data Register EmptyThis bit is set (one) when a character written to UDRis transferred to the Transmit shift register. Setting of this bit indicates that the transmitter is ready to receive a new character for transmission. When the UDR0IE bit in UCR is set, the USART Transmit Complete interrupt to be executed as long as UDR0E is set. UDR0E is cleared by writing UDR0. When interrupt-driven data transmittal is used, the USART Data Register Empty Interrupt routine must write UDRin order to clear UDR0E, otherwise a new interrupt will occur once the interrupt routine terminates. UDR0E is set (one) during reset to indicate that the transmitter is reaR1FEFraming ErrorThis bit is set if a Framing Error condition is detected, i.e. when the stop bit of an incoming character is zero. The FE bit is cleared when the stop bit of received data is one.R0DORData overRunThis bit is set if an Overrun condition is detected, i.e. when a character already present in the UDRregister is not read before the next character has been shifted into the Receiver Shift register. The OR bit is buffered, which means that it will be set once the valid data still in UDR0E is read. The OR bit is cleared (zero) when data is received and transferred to UDR0. R0UPEPEUSART Parity ErrorR0U2XDouble the USART Transmission SpeedR0MPCMMulti-processor Communication ModeRW0UCSRBUCRUSART Control and Status Register B$0A$02Aio_flag.bmpYRXCIERX Complete Interrupt EnableWriting this bit to one enables interrupt on the RXC flag. A USART Receive Complete interrupt will be generated only if the RXCIE bit is written to one, the global interrupt flag in SREG is written to one and the RXC bit in UCSR0A is set.RW0TXCIETX Complete Interrupt EnableWriting this bit to one enables interrupt on the TXC flag. A USART Transmit Complete interrupt will be generated only if the TXCIE bit is written to one, the global interrupt flag in SREG is written to one and the TXC bit in UCSR0A is set.RW0UDRIEUSART Data register Empty Interrupt EnableWriting this bit to one enables interrupt on the UDR0E flag. A Data Register Empty interrupt will be generated only if the UDR0IE bit is written to one, the global interrupt flag in SREG is written to one and the UDR0E bit in UCSR0A is set.RW1RXENReceiver EnableWriting this bit to one enables the USART receiver. The receiver will override normal port operation for the RxD pin when enabled. Disabling the receiver will flush the receive buffer invalidating the FE, DOR and PE flags.RW0TXENTransmitter EnableWriting this bit to one enables the USART transmitter. The transmitter will override normal port operation for the TxD pin when enabled. The disabling of the transmitter (writing TXEN to zero) will not become effective until ongoing and pending transmissions are completed, i.e. when the transmit shift register and transmit buffer register does not contain data to be transmitted. When disabled, the transmitter will no longer override the TxD port.RW0UCSZ2CHR9Character SizeRW0RXB8Receive Data Bit 8RXB8 is the 9th data bit of the received character when operating with serial frames with 9 data bits. Must be read before reading the low bits from UDR0.R0TXB8Transmit Data Bit 8TXB8 is the 9th data bit in the character to be transmitted when operating with serial frames with 9 data bits. Must be writ-ten before writing the low bits to UDR0.W0UCSRCUSART Control and Status Register C$03$23io_flag.bmpYUMSELUSART Mode SelectRW0UPM1Parity Mode Bit 1RW1UPM0Parity Mode Bit 0RW0USBSStop Bit SelectRW0UCSZ1Character Size Bit 1RW0UCSZ0Character Size Bit 0R0UCPOLClock PolarityW0UBRRHUSART Baud Rate Register High ByteThis is a 12-bit register which contains the USART baud rate. The UBRR0H contains the 4 most significant bits, and the UBRR0L contains the 8 least significant bits of the USART baud rate. Ongoing transmissions by the transmitter and receiver will be corrupted if the baud rate is changed. Writing UBRR0L will trigger an immediate update of the baud rate prescaler.$02$22io_com.bmpNUBRR11USART Baud Rate Register bit 11RW0UBRR10USART Baud Rate Register bit 10RW0UBRR9USART Baud Rate Register bit 9RW0UBRR8USART Baud Rate Register bit 8RW0UBRRLUBRRUSART Baud Rate Register Low ByteThis is a 12-bit register which contains the USART baud rate. The UBRR0H contains the 4 most significant bits, and the UBRR0L contains the 8 least significant bits of the USART baud rate. Ongoing transmissions by the transmitter and receiver will be corrupted if the baud rate is changed. Writing UBRR0L will trigger an immediate update of the baud rate prescaler.$09$29io_com.bmpNUBRR7USART Baud Rate Register bit 7RW0UBRR6USART Baud Rate Register bit 6RW0UBRR5USART Baud Rate Register bit 5RW0UBRR4USART Baud Rate Register bit 4RW0UBRR3USART Baud Rate Register bit 3RW0UBRR2USART Baud Rate Register bit 2RW0UBRR1USART Baud Rate Register bit 1RW0UBRR0USART Baud Rate Register bit 0RW0[ACSR:DIDR]io_analo.bmpAlgComp_06ACSRAnalog Comparator Control And Status Register$08$28io_analo.bmpYACDAnalog Comparator DisableWhen this bit is written logic one, the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.RW0ACBGAnalog Comparator Bandgap SelectWhen this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. See “Internal Voltage Reference” on page 42.RW0ACOAnalog Compare OutputThe output of the analog comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1-2 clock cycles.RNAACIAnalog Comparator Interrupt FlagThis bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hard-ware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.RW0ACIEAnalog Comparator Interrupt EnableWhen the ACIE bit is written logic one and the I-bit in the Status Register is set, the analog comparator interrupt is acti-vated. When written logic zero, the interrupt is disabled.RW0ACICRW0ACIS1Analog Comparator Interrupt Mode Select bit 1These bits determine which comparator events that trigger the Analog Comparator interrupt.RW0ACIS0Analog Comparator Interrupt Mode Select bit 0These bits determine which comparator events that trigger the Analog Comparator interrupt.RW0DIDRDigital Input Disable Register 1When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer.$01$21io_analo.bmpNAIN1DAIN1 Digital Input DisableRW0AIN0DAIN0 Digital Input DisableRW0[PORTD:DDRD:PIND]io_port.bmpAVRSimIOPort.SimIOPortPORTDData Register, Port D$12$32io_port.bmpNPORTD6RW0PORTD5RW0PORTD4RW0PORTD3RW0PORTD2RW0PORTD1RW0PORTD0RW0DDRDData Direction Register, Port D$11$31io_flag.bmpNDDD6RW0DDD5RW0DDD4RW0DDD3RW0DDD2RW0DDD1RW0DDD0RW0PINDInput Pins, Port D$10$30io_port.bmpNPIND6R0PIND5R0PIND4R0PIND3R0PIND2R0PIND1R0PIND0R0[EEAR:EEDR:EECR]io_cpu.bmpEEPROM_02.xmlEEAREEARLEEPROM Read/Write AccessThe EEPROM access register is accessible in the I/O space. The write access time is in the range of 2.5 - 4ms, depending on the V CC voltages. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains code that writes the EEPROM, some pre-caution must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. CPU operation under these conditions is likely cause the program counter to perform unintentional jumps and eventually execute the EEPROM write code. To secure EEPROM integrity, the user is advised to use an external under-voltage reset circuit in this case. In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction$1E$3Eio_cpu.bmpNEEAR6EEPROM Read/Write Access bit 6RW0EEAR5EEPROM Read/Write Access bit 5RW0EEAR4EEPROM Read/Write Access bit 4RW0EEAR3EEPROM Read/Write Access bit 3RW0EEAR2EEPROM Read/Write Access bit 2RW0EEAR1EEPROM Read/Write Access bit 1RW0EEAR0EEPROM Read/Write Access bit 0RW0EEDREEPROM Data RegisterFor the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.$1D$3Dio_cpu.bmpNEEDR7EEPROM Data Register bit 7RW0EEDR6EEPROM Data Register bit 6RW0EEDR5EEPROM Data Register bit 5RW0EEDR4EEPROM Data Register bit 4RW0EEDR3EEPROM Data Register bit 3RW0EEDR2EEPROM Data Register bit 2RW0EEDR1EEPROM Data Register bit 1RW0EEDR0EEPROM Data Register bit 0RW0EECREEPROM Control Register$1C$3Cio_flag.bmpYEEPM1RW0EEPM0RW0EERIEEEProm Ready Interrupt EnableWhen the I-bit in SREG and EERIE are set (one), the EEPROM Ready Interrupt is enabled. When cleared (zero), the interrupt is disabled. The EEPROM Ready Interrupt generates a constant interrupt when EEWE is cleared (zero).RW0EEMPEEEMWEEEPROM Master Write EnableThe EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set(one) setting EEWE will write data to the EEPROM at the selected address If EEMWE is zero, setting EEWE will have no effect. When EEMWE has been set (one) by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for a EEPROM write procedure.RW0EEPEEEWEEEPROM Write EnableThe EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 2 and 3 is unessential): 1. Wait until EEWE becomes zero. 2. Write new EEPROM address to EEARL and EEARH (optional). 3. Write new EEPROM data to EEDR (optional). 4. Write a logical one to the EEMWE bit in EECR (to be able to write a logical one to the EEMWE bit, the EEWE bit mustbewritten to zero in thesamecycle). 5. Within four clock cycles after setting EEMWE, write a logical one to EEWE. When the write access time (typically 2.5 ms at V CC =5Vor 4msatV CC = 2.7V) has elapsed, the EEWE bit is cleared (zero) by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted or two cycles before the next instruction is executed. Caution: An interrupt between step 4 and step 5 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR regis-ter will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the 4 last steps to avoid these problems.RW0EEREEEPROM Read EnableThe EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be set. When the EERE bit is cleared (zero) by hardware, requested data is found in the EEDR register. The EEPROM read access takes one instruction and there is no need to poll the EERE bit. When EERE has been set, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress when new data or address is written to the EEPROM I/O registers, the write operation will be interrupted, and the result is undefined.RW0[PORTA:DDRA:PINA]io_port.bmpAVRSimIOPort.SimIOPortPORTAPort A Data Register$1B$3Bio_port.bmpNPORTA2Port A Data Register bit 2RW0PORTA1Port A Data Register bit 1RW0PORTA0Port A Data Register bit 0RW0DDRAPort A Data Direction Register$1A$3Aio_flag.bmpNDDA2Data Direction Register, Port A, bit 2RW0DDA1Data Direction Register, Port A, bit 1RW0DDA0Data Direction Register, Port A, bit 0RW0PINAPort A Input PinsThe Port A Input Pins address - PINA - is not a register, and this address enables access to the physical value on each Port A pin. When reading PORTA the Port A Data Latch is read, and when reading PINA, the logical values present on the pins are read.$19$39io_port.bmpNPINA2Input Pins, Port A bit 2RWHi-ZPINA1Input Pins, Port A bit 1RWHi-ZPINA0Input Pins, Port A bit 0RWHi-Z[SREG:SPL:SPMCSR:MCUCR:CLKPR:MCUSR:OSCCAL:GTCCR:PCMSK:GPIOR2:GPIOR1:GPIOR0]
[SPH:SPL]
io_cpu.bmpSREGStatus Register$3F$5Fio_sreg.bmpYIGlobal Interrupt EnableThe global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable bit is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts.RW0TBit Copy StorageThe bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction.RW0HHalf Carry FlagThe half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed information.RW0SSign BitThe S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruc-tion Set Description for detailed information.RW0VTwo's Complement Overflow FlagThe two’s complement overflow flag V supports two’s complement arithmetics. See the Instruction Set Description for detailed information.RW0NNegative FlagThe negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.RW0ZZero FlagThe zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.RW0CCarry FlagThe carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software.RW0SPLStack Pointer Low Byte$3D$5Dio_sreg.bmpNSP7Stack Pointer Bit 7RW0SP6Stack Pointer Bit 6RW0SP5Stack Pointer Bit 5RW0SP4Stack Pointer Bit 4RW0SP3Stack Pointer Bit 3RW0SP2Stack Pointer Bit 2RW0SP1Stack Pointer Bit 1RW0SP0Stack Pointer Bit 0RW0SPMCSRStore Program Memory Control and Status register$37$57io_sreg.bmpYCTPBClear Temporary Page BufferIf the CTPB bit is written while filling the temporary page buffer, the temporary page buffer will be cleared and the data will be lost.RW0RFLBRead Fuse and Lock BitsAn LPM instruction within three cycles after RFLB and SPMEN are set in the SPMCSR Register, will read either the Lock bits or the Fuse bits (depending on Z0 in the Zpointer) into the destination register.RW0PGWRTPage WriteIf this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a Page Write, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page Write operation.RW0PGERSPage EraseIf this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Erase. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a Page Erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page Write operation.RW0SPMENStore Program Memory EnableThis bit enables the SPM instruction for the next four clock cycles. If written to one together with either CTPB, RFLB, PGWRT, or PGERS, the following SPM instruction will have a special meaning, see description above. If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer. The LSB of the Z-pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During Page Erase and Page Write, the SPMEN bit remains high until the operation is completed. Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in the lower five bits will have no effeRW0MCUCRMCU Control RegisterThe MCU Control Register contains control bits for general MCU functions.$35$55io_cpu.bmpYPUDPull-up DisableRW0SM1Sleep Mode Select Bit 1R0SESleep EnableThe SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmers purpose, it is recommended to set the Sleep Enable SE bit just before the execution of the SLEEP instruction.R0SM0SMSleep Mode Select Bit 0RW0ISC11Interrupt Sense Control 1 bit 1RW0ISC10Interrupt Sense Control 1 bit 0R0ISC01Interrupt Sense Control 0 bit 1R0ISC00Interrupt Sense Control 0 bit 0R0MCUSRMCU Status registerThe MCU Status Registerprovides information on which reset source caused a MCU reset.$34$54io_cpu.bmpYWDRFWatchdog Reset FlagRW0BORFBrown-out Reset FlagRW0EXTRFExternal Reset FlagAfter a power-on reset, this bit is undefined (X). It will be set by an external reset. A watchdog reset will leave this bit unchanged.RW0PORFPower-On Reset FlagThis bit is set by a power-on reset. A watchdog reset or an external reset will leave this bit unchangedRW0OSCCALOscillator Calibration Register$31$51io_sreg.bmpNCAL6Oscillatro Calibration Value Bit 6RW0CAL5Oscillatro Calibration Value Bit 5RW0CAL4Oscillatro Calibration Value Bit 4RW0CAL3Oscillatro Calibration Value Bit 3RW0CAL2Oscillatro Calibration Value Bit 2RW0CAL1Oscillatro Calibration Value Bit 1RW0CAL0Oscillatro Calibration Value Bit 0RW0CLKPRClock Prescale Register$26$46io_cpu.bmpYCLKPCEClock Prescaler Change EnableThe CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is cleared by hardware four cycles after it is written or when CLKPS bits are written. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the CLKPCE bit.RW0CLKPS3Clock Prescaler Select Bit 3RW0CLKPS2Clock Prescaler Select Bit 2RW0CLKPS1Clock Prescaler Select Bit 1RW0CLKPS0Clock Prescaler Select Bit 0RW0GTCCRSFIORGeneral Timer Counter Control Register$23$43io_sreg.bmpYPSR10RW0PCMSKPin-Change Mask register$20$40io_sreg.bmpNPCINT7Pin-Change Interrupt 7RW0PCINT6Pin-Change Interrupt 6RW0PCINT5Pin-Change Interrupt 5RW0PCINT4Pin-Change Interrupt 4RW0PCINT3Pin-Change Interrupt 3RW0PCINT2Pin-Change Interrupt 2RW0PCINT1Pin-Change Interrupt 1RW0PCINT0Pin-Change Interrupt 0RW0GPIOR2General Purpose I/O Register 2$15$35io_sreg.bmpNGPIOR27General Purpose I/O Register 2 bit 7RW0GPIOR26General Purpose I/O Register 2 bit 6RW0GPIOR25General Purpose I/O Register 2 bit 5RW0GPIOR24General Purpose I/O Register 2 bit 4RW0GPIOR23General Purpose I/O Register 2 bit 3RW0GPIOR22General Purpose I/O Register 2 bit 2RW0GPIOR21General Purpose I/O Register 2 bit 1RW0GPIOR20General Purpose I/O Register 2 bit 0RW0GPIOR1General Purpose I/O Register 1$14$34io_sreg.bmpNGPIOR17General Purpose I/O Register 1 bit 7RW0GPIOR16General Purpose I/O Register 1 bit 6RW0GPIOR15General Purpose I/O Register 1 bit 5RW0GPIOR14General Purpose I/O Register 1 bit 4RW0GPIOR13General Purpose I/O Register 1 bit 3RW0GPIOR12General Purpose I/O Register 1 bit 2RW0GPIOR11General Purpose I/O Register 1 bit 1RW0GPIOR10General Purpose I/O Register 1 bit 0RW0GPIOR0General Purpose I/O Register 0$13$33io_sreg.bmpNGPIOR07General Purpose I/O Register 0 bit 7RW0GPIOR06General Purpose I/O Register 0 bit 6RW0GPIOR05General Purpose I/O Register 0 bit 5RW0GPIOR04General Purpose I/O Register 0 bit 4RW0GPIOR03General Purpose I/O Register 0 bit 3RW0GPIOR02General Purpose I/O Register 0 bit 2RW0GPIOR01General Purpose I/O Register 0 bit 1RW0GPIOR00General Purpose I/O Register 0 bit 0RW0[USIDR:USISR:USICR]io_com.bmpUniversal Serial InterfaceUSIDRUSI Data Register$0F$2Fio_com.bmpNUSIDR7USI Data Register bit 7RW0USIDR6USI Data Register bit 6RW0USIDR5USI Data Register bit 5RW0USIDR4USI Data Register bit 4RW0USIDR3USI Data Register bit 3RW0USIDR2USI Data Register bit 2RW0USIDR1USI Data Register bit 1RW0USIDR0USI Data Register bit 0RW0USISRUSI Status Register$0E$2Eio_flag.bmpYUSISIFStart Condition Interrupt FlagRW0USIOIFCounter Overflow Interrupt FlagRW0USIPFStop Condition FlagRW1USIDCData Output CollisionRW0USICNT3USI Counter Value Bit 3RW0USICNT2USI Counter Value Bit 2RW0USICNT1USI Counter Value Bit 1RW0USICNT0USI Counter Value Bit 0RW0USICRUSI Control Register$0D$2Dio_flag.bmpYUSISIEStart Condition Interrupt EnableRW0USIOIECounter Overflow Interrupt EnableRW0USIWM1USI Wire Mode Bit 1RW1USIWM0USI Wire Mode Bit 0RW0USICS1USI Clock Source Select Bit 1RW0USICS0USI Clock Source Select Bit 0RW0USICLKClock StrobeR0USITCToggle Clock Port PinW0[ICEPRO:SIMULATOR:JTAGICEmkII:ICE50:STK500:STK500_2:AVRISPmkII:AVRDragon]0x100x0a0x080x000x780x000x81AVRSimCoreV2.SimCoreV2AVRSimMemory8bit.SimMemory8bitAVRSimInterrupt.SimInterrupt0x11012AVRSimIOPort.SimIOPort0x07YAVRSimIOPort.SimIOPort0xffYAVRSimIOPort.SimIOPort0x7FYAVRSimIOExtInterrupt.SimIOExtInterrupt0x010x3b0x400x3a0x400x100x040x350x03AVRSimIOExtInterrupt.SimIOExtInterrupt0x020x3b0x800x3a0x800x100x080x350x0cAVRSimIOPinChangeInterrupt.SimIOPinChangeInterrupt0x0B0x3B0x200x3A0x200x200x160xFFAvrSimIOTim8pwmsync2.tim8pwmsync20x060x0D0x0EPORTB2PORTD5PIND4AVRSimIOTimert16pwm1.SimIOTimert16pwm10x030x040x0C0x050x100x200x100x400x180x080x180x10AVRSimAC.SimIOAC0x0AAVRSimIOUsart.SimIOUsart0x070x090x080x100x020x100x01AvrSimUSI.SimUSI0x100x0F0x990xff0xe10xff0x910ADebugWire0x0E,0xEF,0xFF,0x7F,0x3F,0xFF,0x7F,0xBF0x0E,0xA6,0xBE,0x7D,0x39,0xFF,0x7D,0xBA0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X000X00,0X00,0X00,0X00,0X00,0X00,0X00,0X000x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x000x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x000x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x000x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x000x000X000X003240x00000x00000x00000x00000x00000x000x8000x0000,320x0020,640x000x800x000x000x200x000xBB, 0xFE, 0xBB, 0xEE, 0xBB, 0xCC, 0xB2, 0x0D, 0xBA, 0x0F, 0xB2, 0x0F, 0xBA, 0x0D, 0xBB, 0xBC, 0x99, 0xE1, 0xBB, 0xAC0xB2, 0x0F, 0x1F0x3e0x3d0x1F0x000x000x000x000x000x3c0x050x0F0x0F0x0F0x050x050x050x050x050x050x050x050x050x0F0x0F0x050x150x140x140x000000DF0x000000000x000000000x000000000x0000007F0x000007FF0x000003FF0x000003FF0x000003FF0x000003FF0x000000DF0x0000FFFF0x0000007F0x000000000x000000000x000000000x0023FFFF0x00000FFF0x0000005F0xFF0xDF0x620xff0x510x67ATtiny2313.bin0x020x0010000002000000072 ; INTOSC = 1, INTRC=2;EXTCLK=41 ;NOTUSE = 1, EXTERNAL = 4, INTERNAL = 2 1 00x000x0080x800x000000400x00000000CKOUT fuse0x000000400x00000040CKOUT fuse0x000100000x00000000SELFPRGEN Fuse 0x000100000x00010000SELFPRGEN Fuse 0x000000310x00000000258CK, 14CK +4.1ms0x000000310x00000010258CK, 14CK +65ms0x000000310x000000201kCK, 14CK0x000000310x000000301kCK, 14CK +4.1ms0x0000000c0x000000006 CK, 14CK0x000000310x000000011kCK, 14CK +65ms0x000000310x0000001116kCK, 14CK0x0000000c0x000000006 CK, 14CK0x000000310x0000002116kCK, 14CK +4.1ms0x0000000c0x000000006 CK, 14CK0x000000310x0000003116kCK, 14CK +65ms0x0000000c0x000000006 CK, 14CK0x000000300x000000006 CK, 14CK0x000000300x000000106 CK, 14CK+4ms0x000000300x000000206 CK, 14CK+64 ms0x000000300x000000006 CK, 14CK0x000000300x000000106 CK, 14CK+4ms0x000000300x000000206 CK, 14CK+64 ms0x0000000e0x0000000e0x0000000f0x0000000480x0000000f0x0000000240x0000000f0x000000000x000010000x00000000Watchdog always ON0x000010000x00001000Watchdog disabled0x000001000x00000000RSTDSBL Fuse 0x000001000x00000100RSTDSBL80x000000800x00000000CKDIV8 Fuse0x000000800x00000080CKDIV80x00000E000x00000E00BOD disabled0x00000E000x00000C00BOD enabled, 1.8 V0x00000E000x00000A00BOD enabled, 2.7 V0x00000E000x00000800BOD enabled, 4.3 V0x231110xFF0xFF0xFF010xD40xD6 2001002532030x53114510x4132100x400x4C0x000x000x000x41460xC10xC20x000x000x0025625644440x0E 0x1E 0x0E 0x1E 0x2E 0x3E 0x2E 0x3E 0x4E 0x5E 0x4E 0x5E 0x6E 0x7E 0x6E 0x7E 0x26 0x36 0x66 0x76 0x2A 0x3A 0x6A 0x7A 0x2E 0xFD 0x00 0x01 0x00 0x00 0x00 0x001000511510151501050x0B25625650x052562560505