[ADMIN:CORE:INTERRUPT_VECTOR:POWER:PROGVOLT:PACKAGE:MEMORY:FUSE:PROGRAMMING:LOCKBIT:IO_MODULE:ICE_SETTINGS] ATtiny2313 16MHZ 201 RELEASED $1E $91 $0A V2 AVRSimCoreV2.SimCoreV2 [lpm rd,z+] [] [] 32 $00 $1B $1A $1D $1C $1F $1E 19 $000 RESET External Reset, Power-on Reset and Watchdog Reset $001 INT0 External Interrupt Request 0 $002 INT1 External Interrupt Request 1 $003 TIMER1 CAPT Timer/Counter1 Capture Event $004 TIMER1 COMPA TIMER1 COMP Timer/Counter1 Compare Match A $005 TIMER1 OVF Timer/Counter1 Overflow $006 TIMER0 OVF Timer/Counter0 Overflow $007 USART, RX USART0, RX USART, Rx Complete $008 USART, UDRE USART0, UDRE USART Data Register Empty $009 USART, TX USART0, TX USART, Tx Complete $00A ANA COMP Analog Comparator $00B PCINT $00C TIMER1 COMPB $00D TIMER0 COMPA $00E TIMER0 COMPB $00F USI START USI Start Condition $010 USI OVERFLOW USI Overflow $11 EEPROM Ready $012 WDT OVERFLOW Watchdog Timer Overflow 4MHz 25C 2.8mA 0.8mA <1uA 2.7 6.0 4.0 6.0 [DIP:SOIC] 20 ['RESET] [PD0:RXD] [PD1:TXD] [XTAL2:PA1] [XTAL1:PA0] [PD2:INT0:XCK:CKOUT] [PD3:INT1] [PD4:T0] [PD5:T1:OC0B] [GND] [PD6:ICP] [PB0:AIN0] [PB1:AIN1] [PB2:OC0A] [PB3:OC1A] [PB4:OC1B] [PB5:MOSI:DI] [PB6:MISO:DO] [PB7:SCK:SCL] VCC 20 ['RESET] [PD0:RXD] [PD1:TXD] [XTAL2:PA1] [XTAL1:PA0] [PD2:INT0:XCK:CKOUT] [PD3:INT1] [PD4:T0] [PD5:T1:OC0B] [GND] [PD6:ICP] [PB0:AIN0] [PB1:AIN1] [PB2:OC0A] [PB3:OC1A] [PB4:OC1B] [PB5:MOSI:DI] [PB6:MISO:DO] [PB7:SCK:SCL] VCC AVRSimMemory8bit.SimMemory8bit 2048 128 128 $60 0 NA $00 $3F NA NA $20 $5F $3F $5F 0x010x020x040x080x100x200x400x80 $3D $5D 0x010x020x040x080x100x200x400x80 $3C $5C 0x010x020x040x080x100x200x400x80 $3B $5B 0x200x400x80 $3A $5A 0x200x400x80 $39 $59 0x010x020x040x080x200x400x80 $38 $58 0x010x020x040x080x200x400x80 $37 $57 0x010x020x040x080x10 $36 $56 0x010x020x040x080x100x200x400x80 $35 $55 0x010x020x040x080x100x200x400x80 $34 $54 0x010x020x040x08 $33 $53 0x010x020x040x080x400x80 $32 $52 0x010x020x040x080x100x200x400x80 $31 $51 0x010x020x040x080x100x200x40 $30 $50 0x010x020x100x200x400x80 $2F $4F 0x010x020x100x200x400x80 $2E $4E 0x010x020x040x080x100x400x80 $2D $4D 0x010x020x040x080x100x200x400x80 $2C $4C 0x010x020x040x080x100x200x400x80 $2B $4B 0x010x020x040x080x100x200x400x80 $2A $4A 0x010x020x040x080x100x200x400x80 $29 $49 0x010x020x040x080x100x200x400x80 $28 $48 0x010x020x040x080x100x200x400x80 $26 $46 0x010x020x040x080x80 $25 $45 0x010x020x040x080x100x200x400x80 $24 $44 0x010x020x040x080x100x200x400x80 $23 $43 0x01 $22 $42 0x400x80 $21 $41 0x010x020x040x080x100x200x400x80 $20 $40 0x010x020x040x080x100x200x400x80 $1E $3E 0x010x020x040x080x100x200x40 $1D $3D 0x010x020x040x080x100x200x400x80 $1C $3C 0x010x020x040x080x100x20 $1B $3B 0x010x020x04 $1A $3A 0x010x020x04 $19 $39 0x010x020x04 $18 $38 $ff 0x010x020x040x080x100x200x400x80 $17 $37 0x010x020x040x080x100x200x400x80 $16 $36 0x010x020x040x080x100x200x400x80 $15 $35 0x010x020x040x080x100x200x400x80 $14 $34 0x010x020x040x080x100x200x400x80 $13 $33 0x010x020x040x080x100x200x400x80 $12 $32 $7f 0x010x020x040x080x100x200x40 $11 $31 0x010x020x040x080x100x200x40 $10 $30 0x010x020x040x080x100x200x40 $0F $2F 0x010x020x040x080x100x200x400x80 $0E $2E 0x010x020x040x080x100x200x400x80 $0D $2D 0x010x020x040x080x100x200x400x80 $0C $2C 0x010x020x040x080x100x200x400x80 $0B $02B 0x010x020x040x080x100x200x400x80 $0A $02A 0x010x020x040x080x100x200x400x80 $09 $29 0x010x020x040x080x100x200x400x80 $08 $28 0x010x020x040x080x100x200x400x80 $03 $23 0x010x020x040x080x100x200x40 $02 $22 0x010x020x040x08 $01 $21 0x010x02 $0 $3ff $0 $0 16 [LOW:HIGH:EXTENDED] 8 CKDIV8 Divide clock by 8 0 CKOUT Clock output 1 SUT1 Select start-up time 1 SUT0 Select start-up time 0 CKSEL3 Select Clock Source 0 CKSEL2 Select Clock Source 0 CKSEL1 Select Clock Source 1 CKSEL0 Select Clock Source 0 46 0x80 0x00 Divide clock by 8 internally; [CKDIV8=0] 0x40 0x00 Clock output on PORTD2; [CKOUT=0] 0x3F 0x00 Ext. Clock; Start-up time: 14 CK + 0 ms; [CKSEL=0000 SUT=00] 0x3F 0x10 Ext. Clock; Start-up time: 14 CK + 4.1 ms; [CKSEL=0000 SUT=01] 0x3F 0x20 Ext. Clock; Start-up time: 14 CK + 65 ms; [CKSEL=0000 SUT=10] 0x3F 0x02 Int. RC Osc. 4 MHz; Start-up time: 14 CK + 0 ms; [CKSEL=0010 SUT=00] 0x3F 0x12 Int. RC Osc. 4 MHz; Start-up time: 14 CK + 4.1 ms; [CKSEL=0010 SUT=01] 0x3F 0x22 Int. RC Osc. 4 MHz; Start-up time: 14 CK + 65 ms; [CKSEL=0010 SUT=10] 0x3F 0x04 Int. RC Osc. 8 MHz; Start-up time: 14 CK + 0 ms; [CKSEL=0100 SUT=00] 0x3F 0x14 Int. RC Osc. 8 MHz; Start-up time: 14 CK + 4.1 ms; [CKSEL=0100 SUT=01] 0x3F 0x24 Int. RC Osc. 8 MHz; Start-up time: 14 CK + 65 ms; [CKSEL=0100 SUT=10]; default value 0x3F 0x06 Int. RC Osc. 128 kHz; Start-up time: 14 CK + 0 ms; [CKSEL=0110 SUT=00] 0x3F 0x16 Int. RC Osc. 128 kHz; Start-up time: 14 CK + 4 ms; [CKSEL=0110 SUT=01] 0x3F 0x26 Int. RC Osc. 128 kHz; Start-up time: 14 CK + 64 ms;[CKSEL=0110 SUT=10] 0x3F 0x08 Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 14 CK + 4.1 ms; [CKSEL=1000 SUT=00] 0x3F 0x18 Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 14 CK + 65 ms; [CKSEL=1000 SUT=01] 0x3F 0x28 Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 14 CK + 0 ms; [CKSEL=1000 SUT=10] 0x3F 0x38 Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 14 CK + 4.1 ms; [CKSEL=1000 SUT=11] 0x3F 0x09 Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 14 CK + 65 ms; [CKSEL=1001 SUT=00] 0x3F 0x19 Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 14 CK + 0 ms; [CKSEL=1001 SUT=01] 0x3F 0x29 Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 14 CK + 4.1 ms; [CKSEL=1001 SUT=10] 0x3F 0x39 Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 14 CK + 65 ms; [CKSEL=1001 SUT=11] 0x3F 0x0A Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 14 CK + 4.1 ms; [CKSEL=1010 SUT=00] 0x3F 0x1A Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 14 CK + 65 ms; [CKSEL=1010 SUT=01] 0x3F 0x2A Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 14 CK + 0 ms; [CKSEL=1010 SUT=10] 0x3F 0x3A Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 14 CK + 4.1 ms; [CKSEL=1010 SUT=11] 0x3F 0x0B Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 14 CK + 65 ms; [CKSEL=1011 SUT=00] 0x3F 0x1B Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 14 CK + 0 ms; [CKSEL=1011 SUT=01] 0x3F 0x2B Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 14 CK + 4.1 ms; [CKSEL=1011 SUT=10] 0x3F 0x3B Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 14 CK + 65 ms; [CKSEL=1011 SUT=11] 0x3F 0x0C Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 14 CK + 4.1 ms; [CKSEL=1100 SUT=00] 0x3F 0x1C Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 14 CK + 65 ms; [CKSEL=1100 SUT=01] 0x3F 0x2C Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 14 CK + 0 ms; [CKSEL=1100 SUT=10] 0x3F 0x3C Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 14 CK + 4.1 ms; [CKSEL=1100 SUT=11] 0x3F 0x0D Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 14 CK + 65 ms; [CKSEL=1101 SUT=00] 0x3F 0x1D Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 14 CK + 0 ms; [CKSEL=1101 SUT=01] 0x3F 0x2D Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 14 CK + 4.1 ms; [CKSEL=1101 SUT=10] 0x3F 0x3D Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 14 CK + 65 ms; [CKSEL=1101 SUT=11] 0x3F 0x0E Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 14 CK + 4.1 ms; [CKSEL=1110 SUT=00] 0x3F 0x1E Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 14 CK + 65 ms; [CKSEL=1110 SUT=01] 0x3F 0x2E Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 14 CK + 0 ms; [CKSEL=1110 SUT=10] 0x3F 0x3E Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 14 CK + 4.1 ms; [CKSEL=1110 SUT=11] 0x3F 0x0F Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 14 CK + 65 ms; [CKSEL=1111 SUT=00] 0x3F 0x1F Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 14 CK + 0 ms; [CKSEL=1111 SUT=01] 0x3F 0x2F Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 14 CK + 4.1 ms; [CKSEL=1111 SUT=10] 0x3F 0x3F Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 14 CK + 65 ms; [CKSEL=1111 SUT=11] 8 RSTDISBL External reset disable 1 DWEN debugWIRE Enable 1 SPIEN Enable Serial programming and Data Downloading 0 WDTON Watchdog Timer Always On 1 EESAVE EEPROM memory is preserved through chip erase 1 BODLEVEL2 Brown-out Detector trigger level 1 BODLEVEL1 Brown-out Detector trigger level 1 BODLEVEL0 Brown-out Detector trigger level 1 9 0x80 0x00 Debug Wire enable; [DWEN=0] 0x40 0x00 Preserve EEPROM memory through the Chip Erase cycle; [EESAVE=0] 0x20 0x00 Serial program downloading (SPI) enabled; [SPIEN=0] 0x10 0x00 Watch-dog Timer always on; [WDTON=0] 0x0E 0x08 Brown-out detection level at VCC=4.3 V; [BODLEVEL=100] 0x0E 0x0A Brown-out detection level at VCC=2.7 V; [BODLEVEL=101] 0x0E 0x0C Brown-out detection level at VCC=1.8 V; [BODLEVEL=110] 0x0E 0x0E Brown-out detection disabled; [BODLEVEL=111] 0x01 0x00 Reset Disabled (Enable PA2 as i/o pin); [RSTDISBL=0] 1 SELFPRGEN Self Programming Enable 1 1 0x01 0x00 Self programming enable; [SELFPRGEN=0] 0xff,0xdf 0xff,0xdf 1,0x20,0x20,WARNING! These fuse settings will disable the ISP interface! 1,0x80,0x00,WARNING! Enabling DEBUGWIRE will make the ISP interface inaccessible! 1,0x01,0x00,WARNING! Disabling external reset will make the ISP interface inaccessible! 0,0x3F,0x06,WARNING! Using this clock option together with the CKDIV8 fuse will disable further programming! 0,0x3F,0x16,WARNING! Using this clock option together with the CKDIV8 fuse will disable further programming! 0,0x3F,0x26,WARNING! Using this clock option together with the CKDIV8 fuse will disable further programming! 1,0x20,0x20,WARNING! These fuse settings will disable the ISP interface! 1,0x80,0x00,WARNING! Enabling DEBUGWIRE will make the ISP interface inaccessible! 1,0x01,0x00,WARNING! Disabling external reset will make the ISP interface inaccessible! 0,0x3F,0x06,WARNING! Using this clock option together with the CKDIV8 fuse will disable further programming! 0,0x3F,0x16,WARNING! Using this clock option together with the CKDIV8 fuse will disable further programming! 0,0x3F,0x26,WARNING! Using this clock option together with the CKDIV8 fuse will disable further programming! 0x00,8 MHz 0x01,4 MHz 32 4 [LB1 = 1 : LB2 = 1] No memory lock features enabled. [LB1 = 0 : LB2 = 1] Further programming of Flash and EEPROM is enabled. [LB1 = 0 : LB2 = 0] Same as previous, but verify is also disabled 3 2 0x03 0x03 Mode 1: No memory lock features enabled 0x03 0x02 Mode 2: Further programming disabled 0x03 0x00 Mode 3: Further programming and verification disabled LB1 Lockbit LB2 Lockbit [PORTB:TIMER_COUNTER_0:TIMER_COUNTER_1:WATCHDOG:EXTERNAL_INTERRUPT:USART:ANALOG_COMPARATOR:PORTD:EEPROM:PORTA:CPU:USI] [PORTB:DDRB:PINB] io_port.bmp AVRSimIOPort.SimIOPort PORTB Port B Data Register $18 $38 io_port.bmp N PORTB7 Port B Data Register bit 7 RW 0 PORTB6 Port B Data Register bit 6 RW 0 PORTB5 Port B Data Register bit 5 RW 0 PORTB4 Port B Data Register bit 4 RW 0 PORTB3 Port B Data Register bit 3 RW 0 PORTB2 Port B Data Register bit 2 RW 0 PORTB1 Port B Data Register bit 1 RW 0 PORTB0 Port B Data Register bit 0 RW 0 DDRB Port B Data Direction Register $17 $37 io_flag.bmp N DDB7 Port B Data Direction Register bit 7 RW 0 DDB6 Port B Data Direction Register bit 6 RW 0 DDB5 Port B Data Direction Register bit 5 RW 0 DDB4 Port B Data Direction Register bit 4 RW 0 DDB3 Port B Data Direction Register bit 3 RW 0 DDB2 Port B Data Direction Register bit 2 RW 0 DDB1 Port B Data Direction Register bit 1 RW 0 DDB0 Port B Data Direction Register bit 0 RW 0 PINB Port B Input Pins The Port B Input Pins address - PINB - is not a register, and this address enables access to the physical value on each Port B pin. When reading PORTB, the Port B Data Latch is read, and when reading PINB, the logical values present on the pins are read. $16 $36 io_port.bmp N PINB7 Port B Input Pins bit 7 R 0 PINB6 Port B Input Pins bit 6 R 0 PINB5 Port B Input Pins bit 5 R 0 PINB4 Port B Input Pins bit 4 R 0 PINB3 Port B Input Pins bit 3 R 0 PINB2 Port B Input Pins bit 2 R 0 PINB1 Port B Input Pins bit 1 R 0 PINB0 Port B Input Pins bit 0 R 0 [TIMSK:TIFR:OCR0B:OCR0A:TCCR0A:TCNT0:TCCR0B] io_timer.bmp At8pwm0_11 TIMSK Timer/Counter Interrupt Mask Register $39 $59 io_flag.bmp Y OCIE0B Timer/Counter0 Output Compare Match B Interrupt Enable RW 0 TOIE0 Timer/Counter0 Overflow Interrupt Enable RW 0 OCIE0A Timer/Counter0 Output Compare Match A Interrupt Enable RW 0 TIFR Timer/Counter Interrupt Flag register $38 $58 io_flag.bmp Y OCF0B Timer/Counter0 Output Compare Flag 0B RW 0 TOV0 Timer/Counter0 Overflow Flag RW 0 OCF0A Timer/Counter0 Output Compare Flag 0A RW 0 OCR0B Timer/Counter0 Output Compare Register The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC0 pin. $3C $5C io_timer.bmp N OCR0_7 RW 0 OCR0_6 RW 0 OCR0_5 RW 0 OCR0_4 RW 0 OCR0_3 RW 0 OCR0_2 RW 0 OCR0_1 RW 0 OCR0_0 RW 0 OCR0A Timer/Counter0 Output Compare Register The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC0 pin. $36 $56 io_timer.bmp N OCR0_7 RW 0 OCR0_6 RW 0 OCR0_5 RW 0 OCR0_4 RW 0 OCR0_3 RW 0 OCR0_2 RW 0 OCR0_1 RW 0 OCR0_0 RW 0 TCCR0A Timer/Counter Control Register A $30 $50 io_flag.bmp Y COM0A1 Compare Match Output A Mode Controls Output Compare Pin A behaviour. Please refer to datasheet. RW 0 COM0A0 Compare Match Output A Mode Controls Output Compare Pin A behaviour. Please refer to datasheet. RW 0 COM0B1 Compare Match Output B Mode Controls Output Compare Pin B behaviour. Please refer to datasheet. RW 0 COM0B0 Compare Match Output B Mode Controls Output Compare Pin B behaviour. Please refer to datasheet. RW 0 WGM01 Waveform Generation Mode Controls the Waveform Generation Mode, please refer to datasheet for further details. RW 0 WGM00 Waveform Generation Mode Controls the Waveform Generation Mode, please refer to datasheet for further details. RW 0 TCNT0 Timer/Counter0 The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT0 register blocks (removes) the compare match on the following timer clock. Modifying the counter (TCNT0) while the counter is running, introduces a risk of missing a compare match between TCNT0 the OCR0 register. $32 $52 io_timer.bmp N TCNT0_7 RW 0 TCNT0_6 RW 0 TCNT0_5 RW 0 TCNT0_4 RW 0 TCNT0_3 RW 0 TCNT0_2 RW 0 TCNT0_1 RW 0 TCNT0_0 RW 0 TCCR0B TCCR0 Timer/Counter Control Register B $33 $53 io_flag.bmp Y FOC0A Force Output Compare B RW 0 FOC0B Force Output Compare B W 0 WGM02 RW 0 CS02 Clock Select RW 0 CS01 Clock Select RW 0 CS00 Clock Select RW 0 [TIMSK:TIFR:TCCR1A:TCCR1B:TCCR1C:TCNT1H:TCNT1L:OCR1AH:OCR1AL:OCR1BH:OCR1BL:ICR1H:ICR1L] [TCNT1H:TCNT1L];[OCR1AH:OCR1AL];[OCR1BH:OCR1BL];[ICR1H:ICR1L] io_timer.bmp t16pwm1_13.xml TIMSK Timer/Counter Interrupt Mask Register $39 $59 io_flag.bmp Y TOIE1 Timer/Counter1 Overflow Interrupt Enable When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR. RW 0 OCIE1A Timer/Counter1 Output CompareA Match Interrupt Enable When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a CompareA match in Timer/Counter1 occurs, i.e., when the OCF1A bit is set in the Timer/Counter Interrupt Flag Register - TIFR. RW 0 OCIE1B Timer/Counter1 Output CompareB Match Interrupt Enable When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt is executed if a CompareB match in Timer/Counter1 occurs, i.e., when the OCF1B bit is set in the Timer/Counter Interrupt Flag Register - TIFR. RW 0 ICIE1 TICIE Timer/Counter1 Input Capture Interrupt Enable When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on pin ICP, i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR. RW 0 TIFR Timer/Counter Interrupt Flag register $38 $58 io_flag.bmp Y TOV1 Timer/Counter1 Overflow Flag The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the cor-responding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter1 changes counting direction at $0000. RW 0 OCF1A Output Compare Flag 1A The OCF1A bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare match InterruptA Enable), and the OCF1A are set (one), the Timer/Counter1 Compare A match Interrupt is executed. RW 0 OCF1B Output Compare Flag 1B The OCF1B bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1B - Output Compare Register 1B. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare match InterruptB Enable), and the OCF1B are set (one), the Timer/Counter1 Compare B match Interrupt is executed. RW 0 ICF1 Input Capture Flag 1 The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to the input capture register - ICR1. ICF1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF1 is cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable), and ICF1 are set (one), the Timer/Counter1 Capture Interrupt is executed. RW 0 TCCR1A Timer/Counter1 Control Register A $2F $4F io_flag.bmp Y COM1A1 Compare Output Mode 1A, bit 1 The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA pin 1. This is an alternative function to an I/O port and the corresponding direction control bit must be set (one) to control the output pin. The control configuration is shown in the databook. RW 0 COM1A0 Comparet Ouput Mode 1A, bit 0 The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA pin 1. This is an alternative function to an I/O port and the corresponding direction control bit must be set (one) to control the output pin. The control configuration is shown in the databook. RW 0 COM1B1 Compare Output Mode 1B, bit 1 RW 0 COM1B0 Comparet Ouput Mode 1B, bit 0 RW 0 WGM11 PWM11 Pulse Width Modulator Select Bit 1 RW 0 WGM10 PWM10 Pulse Width Modulator Select Bit 0 RW 0 TCCR1B Timer/Counter1 Control Register B $2E $4E io_flag.bmp Y ICNC1 Input Capture 1 Noise Canceler When the ICNC1 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the ICP - input capture pin - as specified. When the ICNC1 bit is set (one), four successive samples are measures on the ICP - input capture pin, and all samples must be high/low according to the input capture trigger specification in the ICES1 bit. The actual sampling frequency is XTAL clock frequency. RW 0 ICES1 Input Capture 1 Edge Select While the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the falling edge of the input capture pin - ICP. While the ICES1 bit is set (one), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the rising edge of the input capture pin - ICP. RW 0 WGM13 Waveform Generation Mode Bit 3 RW 0 WGM12 CTC1 Waveform Generation Mode Bit 2 RW 0 CS12 Clock Select1 bit 2 RW 0 CS11 Clock Select 1 bit 1 RW 0 CS10 Clock Select bit 0 RW 0 TCCR1C Timer/Counter1 Control Register C $22 $42 io_flag.bmp Y FOC1A Force Output Compare for Channel A The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM mode. However, for ensuring compatibility with future devices, these bits must be set to zero when TCCR1A is written when operating in a PWM mode. When writing a logical one to the FOC1A/FOC1B bit, an immediate compare match is forced on the Waveform Generation unit. The OC1A/OC1B output is changed according to its COM1x1:0 bits setting. Note that the FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the COM1x1:0 bits that determine the effect of the forced compare. A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zero RW 0 FOC1B Force Output Compare for Channel B The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM mode. However, for ensuring compatibility with future devices, these bits must be set to zero when TCCR1A is written when operating in a PWM mode. When writing a logical one to the FOC1A/FOC1B bit, an immediate compare match is forced on the Waveform Generation unit. The OC1A/OC1B output is changed according to its COM1x1:0 bits setting. Note that the FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the COM1x1:0 bits that determine the effect of the forced compare. A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zero RW 0 TCNT1H Timer/Counter1 High Byte This 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR1A, OCR1B and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt ro $2D $4D io_timer.bmp N TCNT1H7 Timer/Counter1 High Byte bit 7 RW 0 TCNT1H6 Timer/Counter1 High Byte bit 6 RW 0 TCNT1H5 Timer/Counter1 High Byte bit 5 RW 0 TCNT1H4 Timer/Counter1 High Byte bit 4 RW 0 TCNT1H3 Timer/Counter1 High Byte bit 3 RW 0 TCNT1H2 Timer/Counter1 High Byte bit 2 RW 0 TCNT1H1 Timer/Counter1 High Byte bit 1 RW 0 TCNT1H0 Timer/Counter1 High Byte bit 0 RW 0 TCNT1L Timer/Counter1 Low Byte This 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR1A, OCR1B and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrup $2C $4C io_timer.bmp N TCNT1L7 Timer/Counter1 Low Byte bit 7 RW 0 TCNT1L6 Timer/Counter1 Low Byte bit 6 RW 0 TCNT1L5 Timer/Counter1 Low Byte bit 5 RW 0 TCNT1L4 Timer/Counter1 Low Byte bit 4 RW 0 TCNT1L3 Timer/Counter1 Low Byte bit 3 RW 0 TCNT1L2 Timer/Counter1 Low Byte bit 2 RW 0 TCNT1L1 Timer/Counter1 Low Byte bit 1 RW 0 TCNT1L0 Timer/Counter1 Low Byte bit 0 RW 0 OCR1AH Timer/Counter1 Outbut Compare Register High Byte The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt $2B $4B io_timer.bmp N OCR1AH7 Timer/Counter1 Outbut Compare Register High Byte bit 7 RW 0 OCR1AH6 Timer/Counter1 Outbut Compare Register High Byte bit 6 RW 0 OCR1AH5 Timer/Counter1 Outbut Compare Register High Byte bit 5 RW 0 OCR1AH4 Timer/Counter1 Outbut Compare Register High Byte bit 4 RW 0 OCR1AH3 Timer/Counter1 Outbut Compare Register High Byte bit 3 RW 0 OCR1AH2 Timer/Counter1 Outbut Compare Register High Byte bit 2 RW 0 OCR1AH1 Timer/Counter1 Outbut Compare Register High Byte bit 1 RW 0 OCR1AH0 Timer/Counter1 Outbut Compare Register High Byte bit 0 RW 0 OCR1AL Timer/Counter1 Outbut Compare Register Low Byte The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interru $2A $4A io_timer.bmp N OCR1AL7 Timer/Counter1 Outbut Compare Register Low Byte Bit 7 RW 0 OCR1AL6 Timer/Counter1 Outbut Compare Register Low Byte Bit 6 RW 0 OCR1AL5 Timer/Counter1 Outbut Compare Register Low Byte Bit 5 RW 0 OCR1AL4 Timer/Counter1 Outbut Compare Register Low Byte Bit 4 RW 0 OCR1AL3 Timer/Counter1 Outbut Compare Register Low Byte Bit 3 RW 0 OCR1AL2 Timer/Counter1 Outbut Compare Register Low Byte Bit 2 RW 0 OCR1AL1 Timer/Counter1 Outbut Compare Register Low Byte Bit 1 RW 0 OCR1AL0 Timer/Counter1 Outbut Compare Register Low Byte Bit 0 RW 0 OCR1BH Timer/Counter1 Outbut Compare Register High Byte The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrup $29 $49 io_timer.bmp N OCR1AH7 Timer/Counter1 Outbut Compare Register High Byte bit 7 RW 0 OCR1AH6 Timer/Counter1 Outbut Compare Register High Byte bit 6 RW 0 OCR1AH5 Timer/Counter1 Outbut Compare Register High Byte bit 5 RW 0 OCR1AH4 Timer/Counter1 Outbut Compare Register High Byte bit 4 RW 0 OCR1AH3 Timer/Counter1 Outbut Compare Register High Byte bit 3 RW 0 OCR1AH2 Timer/Counter1 Outbut Compare Register High Byte bit 2 RW 0 OCR1AH1 Timer/Counter1 Outbut Compare Register High Byte bit 1 RW 0 OCR1AH0 Timer/Counter1 Outbut Compare Register High Byte bit 0 RW 0 OCR1BL Timer/Counter1 Output Compare Register Low Byte The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interru $28 $48 io_timer.bmp N OCR1AL7 Timer/Counter1 Outbut Compare Register Low Byte Bit 7 RW 0 OCR1AL6 Timer/Counter1 Outbut Compare Register Low Byte Bit 6 RW 0 OCR1AL5 Timer/Counter1 Outbut Compare Register Low Byte Bit 5 RW 0 OCR1AL4 Timer/Counter1 Outbut Compare Register Low Byte Bit 4 RW 0 OCR1AL3 Timer/Counter1 Outbut Compare Register Low Byte Bit 3 RW 0 OCR1AL2 Timer/Counter1 Outbut Compare Register Low Byte Bit 2 RW 0 OCR1AL1 Timer/Counter1 Outbut Compare Register Low Byte Bit 1 RW 0 OCR1AL0 Timer/Counter1 Outbut Compare Register Low Byte Bit 0 RW 0 ICR1H Timer/Counter1 Input Capture Register High Byte The input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES1) of the signal at the input capture pin -ICP - is detected, the current value of the Timer/Counter1 is transferred to the Input Capture Register - ICR1. At the same time, the input capture flag - ICF1 - is set (one). Since the Input Capture Register - ICR1 - is a 16-bit register, a temporary register TEMP is used when ICR1 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR1L, the data is sent to the CPU and the data of the high byte ICR1H is placed in the TEMP register. When the CPU reads the data in the high byte ICR1H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR1L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT1, OCR1A and OCR1B. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrup $25 $45 io_timer.bmp N ICR1H7 Timer/Counter1 Input Capture Register High Byte bit 7 RW 0 ICR1H6 Timer/Counter1 Input Capture Register High Byte bit 6 R 0 ICR1H5 Timer/Counter1 Input Capture Register High Byte bit 5 R 0 ICR1H4 Timer/Counter1 Input Capture Register High Byte bit 4 R 0 ICR1H3 Timer/Counter1 Input Capture Register High Byte bit 3 R 0 ICR1H2 Timer/Counter1 Input Capture Register High Byte bit 2 R 0 ICR1H1 Timer/Counter1 Input Capture Register High Byte bit 1 R 0 ICR1H0 Timer/Counter1 Input Capture Register High Byte bit 0 R 0 ICR1L Timer/Counter1 Input Capture Register Low Byte The input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES1) of the signal at the input capture pin -ICP - is detected, the current value of the Timer/Counter1 is transferred to the Input Capture Register - ICR1. At the same time, the input capture flag - ICF1 - is set (one). Since the Input Capture Register - ICR1 - is a 16-bit register, a temporary register TEMP is used when ICR1 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR1L, the data is sent to the CPU and the data of the high byte ICR1H is placed in the TEMP register. When the CPU reads the data in the high byte ICR1H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR1L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT1, OCR1A and OCR1B. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within inte $24 $44 io_timer.bmp N ICR1L7 Timer/Counter1 Input Capture Register Low Byte bit 7 R 0 ICR1L6 Timer/Counter1 Input Capture Register Low Byte bit 6 R 0 ICR1L5 Timer/Counter1 Input Capture Register Low Byte bit 5 R 0 ICR1L4 Timer/Counter1 Input Capture Register Low Byte bit 4 R 0 ICR1L3 Timer/Counter1 Input Capture Register Low Byte bit 3 R 0 ICR1L2 Timer/Counter1 Input Capture Register Low Byte bit 2 R 0 ICR1L1 Timer/Counter1 Input Capture Register Low Byte bit 1 R 0 ICR1L0 Timer/Counter1 Input Capture Register Low Byte bit 0 R 0 [WDTCR] io_watch.bmp WDTCR WDTCSR Watchdog Timer Control Register $21 $41 io_flag.bmp Y WDIF Watchdog Timeout Interrupt Flag RW 0 WDIE Watchdog Timeout Interrupt Enable RW 0 WDP3 Watchdog Timer Prescaler Bit 3 RW 0 WDCE WDTOE Watchdog Change Enable RW 0 WDE Watch Dog Enable When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog RW 0 WDP2 Watch Dog Timer Prescaler bit 2 RW 0 WDP1 Watch Dog Timer Prescaler bit 1 RW 0 WDP0 Watch Dog Timer Prescaler bit 0 RW 0 [GIMSK:EIFR] io_ext.bmp GIMSK General Interrupt Mask Register $3B $5B io_flag.bmp Y INT1 External Interrupt Request 1 Enable When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT1 pin or level sensed. Activity on the pin will cause an interrupt request even if INT1 is configured as an output. The corresponding interrupt of External Interrupt Request 1 is executed from program memory address $002. See also “External Interrupts”. RW 0 INT0 External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from program memory address $001. See also “External Interrupts.” • Bits 5..0 - Res: Reserved bits RW 0 PCIE RW 0 EIFR GIFR Extended Interrupt Flag Register $3A $5A io_flag.bmp Y INTF1 External Interrupt Flag 1 When an event on the INT1 pin triggers an interrupt request, INTF1 becomes set (one). If the I-bit in SREG and the INT1 bit in GIMSK are set (one), the MCU will jump to the interrupt vector at address $002. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. RW 0 INTF0 External Interrupt Flag 0 When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the interrupt vector at address $001. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. RW 0 PCIF RW 0 [UDR:UCSRA:UCSRB:UCSRC:UBRRH:UBRRL] [UBRRH:UBRRL] io_com.bmp The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. The main features are: • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • High Resolution Baud Rate Generator • Supports Serial Frames with 5, 6, 7, 8 or 9 Data Bits and 1 or 2 Stop Bits • Odd or Even Parity Generation and Parity Check Supported by Hardware • Data OverRun Detection • Framing Error Detection • Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter • Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete • Multi-processor Communication Mode • Double Speed Asynchronous Comm UDR USART I/O Data Register The UDR0 register is actually two physically separate registers sharing the same I/O address. When writing to the register, the USART Transmit Data register is written. When reading from UDR0, the USART Receive Data register is read. $0C $2C io_com.bmp N UDR7 USART I/O Data Register bit 7 RW 0 UDR6 USART I/O Data Register bit 6 RW 0 UDR5 USART I/O Data Register bit 5 RW 0 UDR4 USART I/O Data Register bit 4 RW 0 UDR3 USART I/O Data Register bit 3 RW 0 UDR2 USART I/O Data Register bit 2 RW 0 UDR1 USART I/O Data Register bit 1 RW 0 UDR0 USART I/O Data Register bit 0 RW 0 UCSRA USR USART Control and Status Register A $0B $02B io_flag.bmp Y RXC USART Receive Complete This bit is set (one) when a received character is transferred from the Receiver Shift register to UDR0. The bit is set regard-less of any detected framing errors. When the RXCIE bit in UCR is set, the USART Receive Complete interrupt will be executed when RXC is set(one). RXC is cleared by reading UDR0. When interrupt-driven data reception is used, the USART Receive Complete Interrupt routine must read UDRin order to clear RXC, otherwise a new interrupt will occur once the interrupt routine terminates. R 0 TXC USART Transmitt Complete This bit is set (one) when the entire character (including the stop bit) in the Transmit Shift register has been shifted out and no new data has been written to UDR0. This flag is especially useful in half-duplex communications interfaces, where a transmitting application must enter receive mode and free the communications bus immediately after completing the transmission. When the TXCIE bit in UCR is set, setting of TXC causes the USART Transmit Complete interrupt to be executed. TXC is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the TXC bit is cleared (zero) by writing a logical one to the bi RW 0 UDRE USART Data Register Empty This bit is set (one) when a character written to UDRis transferred to the Transmit shift register. Setting of this bit indicates that the transmitter is ready to receive a new character for transmission. When the UDR0IE bit in UCR is set, the USART Transmit Complete interrupt to be executed as long as UDR0E is set. UDR0E is cleared by writing UDR0. When interrupt-driven data transmittal is used, the USART Data Register Empty Interrupt routine must write UDRin order to clear UDR0E, otherwise a new interrupt will occur once the interrupt routine terminates. UDR0E is set (one) during reset to indicate that the transmitter is rea R 1 FE Framing Error This bit is set if a Framing Error condition is detected, i.e. when the stop bit of an incoming character is zero. The FE bit is cleared when the stop bit of received data is one. R 0 DOR Data overRun This bit is set if an Overrun condition is detected, i.e. when a character already present in the UDRregister is not read before the next character has been shifted into the Receiver Shift register. The OR bit is buffered, which means that it will be set once the valid data still in UDR0E is read. The OR bit is cleared (zero) when data is received and transferred to UDR0. R 0 UPE PE USART Parity Error R 0 U2X Double the USART Transmission Speed R 0 MPCM Multi-processor Communication Mode RW 0 UCSRB UCR USART Control and Status Register B $0A $02A io_flag.bmp Y RXCIE RX Complete Interrupt Enable Writing this bit to one enables interrupt on the RXC flag. A USART Receive Complete interrupt will be generated only if the RXCIE bit is written to one, the global interrupt flag in SREG is written to one and the RXC bit in UCSR0A is set. RW 0 TXCIE TX Complete Interrupt Enable Writing this bit to one enables interrupt on the TXC flag. A USART Transmit Complete interrupt will be generated only if the TXCIE bit is written to one, the global interrupt flag in SREG is written to one and the TXC bit in UCSR0A is set. RW 0 UDRIE USART Data register Empty Interrupt Enable Writing this bit to one enables interrupt on the UDR0E flag. A Data Register Empty interrupt will be generated only if the UDR0IE bit is written to one, the global interrupt flag in SREG is written to one and the UDR0E bit in UCSR0A is set. RW 1 RXEN Receiver Enable Writing this bit to one enables the USART receiver. The receiver will override normal port operation for the RxD pin when enabled. Disabling the receiver will flush the receive buffer invalidating the FE, DOR and PE flags. RW 0 TXEN Transmitter Enable Writing this bit to one enables the USART transmitter. The transmitter will override normal port operation for the TxD pin when enabled. The disabling of the transmitter (writing TXEN to zero) will not become effective until ongoing and pending transmissions are completed, i.e. when the transmit shift register and transmit buffer register does not contain data to be transmitted. When disabled, the transmitter will no longer override the TxD port. RW 0 UCSZ2 CHR9 Character Size RW 0 RXB8 Receive Data Bit 8 RXB8 is the 9th data bit of the received character when operating with serial frames with 9 data bits. Must be read before reading the low bits from UDR0. R 0 TXB8 Transmit Data Bit 8 TXB8 is the 9th data bit in the character to be transmitted when operating with serial frames with 9 data bits. Must be writ-ten before writing the low bits to UDR0. W 0 UCSRC USART Control and Status Register C $03 $23 io_flag.bmp Y UMSEL USART Mode Select RW 0 UPM1 Parity Mode Bit 1 RW 1 UPM0 Parity Mode Bit 0 RW 0 USBS Stop Bit Select RW 0 UCSZ1 Character Size Bit 1 RW 0 UCSZ0 Character Size Bit 0 R 0 UCPOL Clock Polarity W 0 UBRRH USART Baud Rate Register High Byte This is a 12-bit register which contains the USART baud rate. The UBRR0H contains the 4 most significant bits, and the UBRR0L contains the 8 least significant bits of the USART baud rate. Ongoing transmissions by the transmitter and receiver will be corrupted if the baud rate is changed. Writing UBRR0L will trigger an immediate update of the baud rate prescaler. $02 $22 io_com.bmp N UBRR11 USART Baud Rate Register bit 11 RW 0 UBRR10 USART Baud Rate Register bit 10 RW 0 UBRR9 USART Baud Rate Register bit 9 RW 0 UBRR8 USART Baud Rate Register bit 8 RW 0 UBRRL UBRR USART Baud Rate Register Low Byte This is a 12-bit register which contains the USART baud rate. The UBRR0H contains the 4 most significant bits, and the UBRR0L contains the 8 least significant bits of the USART baud rate. Ongoing transmissions by the transmitter and receiver will be corrupted if the baud rate is changed. Writing UBRR0L will trigger an immediate update of the baud rate prescaler. $09 $29 io_com.bmp N UBRR7 USART Baud Rate Register bit 7 RW 0 UBRR6 USART Baud Rate Register bit 6 RW 0 UBRR5 USART Baud Rate Register bit 5 RW 0 UBRR4 USART Baud Rate Register bit 4 RW 0 UBRR3 USART Baud Rate Register bit 3 RW 0 UBRR2 USART Baud Rate Register bit 2 RW 0 UBRR1 USART Baud Rate Register bit 1 RW 0 UBRR0 USART Baud Rate Register bit 0 RW 0 [ACSR:DIDR] io_analo.bmp AlgComp_06 ACSR Analog Comparator Control And Status Register $08 $28 io_analo.bmp Y ACD Analog Comparator Disable When this bit is written logic one, the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed. RW 0 ACBG Analog Comparator Bandgap Select When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. See “Internal Voltage Reference” on page 42. RW 0 ACO Analog Compare Output The output of the analog comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1-2 clock cycles. R NA ACI Analog Comparator Interrupt Flag This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hard-ware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag. RW 0 ACIE Analog Comparator Interrupt Enable When the ACIE bit is written logic one and the I-bit in the Status Register is set, the analog comparator interrupt is acti-vated. When written logic zero, the interrupt is disabled. RW 0 ACIC RW 0 ACIS1 Analog Comparator Interrupt Mode Select bit 1 These bits determine which comparator events that trigger the Analog Comparator interrupt. RW 0 ACIS0 Analog Comparator Interrupt Mode Select bit 0 These bits determine which comparator events that trigger the Analog Comparator interrupt. RW 0 DIDR Digital Input Disable Register 1 When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. $01 $21 io_analo.bmp N AIN1D AIN1 Digital Input Disable RW 0 AIN0D AIN0 Digital Input Disable RW 0 [PORTD:DDRD:PIND] io_port.bmp AVRSimIOPort.SimIOPort PORTD Data Register, Port D $12 $32 io_port.bmp N PORTD6 RW 0 PORTD5 RW 0 PORTD4 RW 0 PORTD3 RW 0 PORTD2 RW 0 PORTD1 RW 0 PORTD0 RW 0 DDRD Data Direction Register, Port D $11 $31 io_flag.bmp N DDD6 RW 0 DDD5 RW 0 DDD4 RW 0 DDD3 RW 0 DDD2 RW 0 DDD1 RW 0 DDD0 RW 0 PIND Input Pins, Port D $10 $30 io_port.bmp N PIND6 R 0 PIND5 R 0 PIND4 R 0 PIND3 R 0 PIND2 R 0 PIND1 R 0 PIND0 R 0 [EEAR:EEDR:EECR] io_cpu.bmp EEPROM_02.xml EEAR EEARL EEPROM Read/Write Access The EEPROM access register is accessible in the I/O space. The write access time is in the range of 2.5 - 4ms, depending on the V CC voltages. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains code that writes the EEPROM, some pre-caution must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. CPU operation under these conditions is likely cause the program counter to perform unintentional jumps and eventually execute the EEPROM write code. To secure EEPROM integrity, the user is advised to use an external under-voltage reset circuit in this case. In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction $1E $3E io_cpu.bmp N EEAR6 EEPROM Read/Write Access bit 6 RW 0 EEAR5 EEPROM Read/Write Access bit 5 RW 0 EEAR4 EEPROM Read/Write Access bit 4 RW 0 EEAR3 EEPROM Read/Write Access bit 3 RW 0 EEAR2 EEPROM Read/Write Access bit 2 RW 0 EEAR1 EEPROM Read/Write Access bit 1 RW 0 EEAR0 EEPROM Read/Write Access bit 0 RW 0 EEDR EEPROM Data Register For the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR. $1D $3D io_cpu.bmp N EEDR7 EEPROM Data Register bit 7 RW 0 EEDR6 EEPROM Data Register bit 6 RW 0 EEDR5 EEPROM Data Register bit 5 RW 0 EEDR4 EEPROM Data Register bit 4 RW 0 EEDR3 EEPROM Data Register bit 3 RW 0 EEDR2 EEPROM Data Register bit 2 RW 0 EEDR1 EEPROM Data Register bit 1 RW 0 EEDR0 EEPROM Data Register bit 0 RW 0 EECR EEPROM Control Register $1C $3C io_flag.bmp Y EEPM1 RW 0 EEPM0 RW 0 EERIE EEProm Ready Interrupt Enable When the I-bit in SREG and EERIE are set (one), the EEPROM Ready Interrupt is enabled. When cleared (zero), the interrupt is disabled. The EEPROM Ready Interrupt generates a constant interrupt when EEWE is cleared (zero). RW 0 EEMPE EEMWE EEPROM Master Write Enable The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set(one) setting EEWE will write data to the EEPROM at the selected address If EEMWE is zero, setting EEWE will have no effect. When EEMWE has been set (one) by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for a EEPROM write procedure. RW 0 EEPE EEWE EEPROM Write Enable The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 2 and 3 is unessential): 1. Wait until EEWE becomes zero. 2. Write new EEPROM address to EEARL and EEARH (optional). 3. Write new EEPROM data to EEDR (optional). 4. Write a logical one to the EEMWE bit in EECR (to be able to write a logical one to the EEMWE bit, the EEWE bit mustbewritten to zero in thesamecycle). 5. Within four clock cycles after setting EEMWE, write a logical one to EEWE. When the write access time (typically 2.5 ms at V CC =5Vor 4msatV CC = 2.7V) has elapsed, the EEWE bit is cleared (zero) by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted or two cycles before the next instruction is executed. Caution: An interrupt between step 4 and step 5 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR regis-ter will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the 4 last steps to avoid these problems. RW 0 EERE EEPROM Read Enable The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be set. When the EERE bit is cleared (zero) by hardware, requested data is found in the EEDR register. The EEPROM read access takes one instruction and there is no need to poll the EERE bit. When EERE has been set, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress when new data or address is written to the EEPROM I/O registers, the write operation will be interrupted, and the result is undefined. RW 0 [PORTA:DDRA:PINA] io_port.bmp AVRSimIOPort.SimIOPort PORTA Port A Data Register $1B $3B io_port.bmp N PORTA2 Port A Data Register bit 2 RW 0 PORTA1 Port A Data Register bit 1 RW 0 PORTA0 Port A Data Register bit 0 RW 0 DDRA Port A Data Direction Register $1A $3A io_flag.bmp N DDA2 Data Direction Register, Port A, bit 2 RW 0 DDA1 Data Direction Register, Port A, bit 1 RW 0 DDA0 Data Direction Register, Port A, bit 0 RW 0 PINA Port A Input Pins The Port A Input Pins address - PINA - is not a register, and this address enables access to the physical value on each Port A pin. When reading PORTA the Port A Data Latch is read, and when reading PINA, the logical values present on the pins are read. $19 $39 io_port.bmp N PINA2 Input Pins, Port A bit 2 RW Hi-Z PINA1 Input Pins, Port A bit 1 RW Hi-Z PINA0 Input Pins, Port A bit 0 RW Hi-Z [SREG:SPL:SPMCSR:MCUCR:CLKPR:MCUSR:OSCCAL:GTCCR:PCMSK:GPIOR2:GPIOR1:GPIOR0] [SPH:SPL] io_cpu.bmp SREG Status Register $3F $5F io_sreg.bmp Y I Global Interrupt Enable The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable bit is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. RW 0 T Bit Copy Storage The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction. RW 0 H Half Carry Flag The half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed information. RW 0 S Sign Bit The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruc-tion Set Description for detailed information. RW 0 V Two's Complement Overflow Flag The two’s complement overflow flag V supports two’s complement arithmetics. See the Instruction Set Description for detailed information. RW 0 N Negative Flag The negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information. RW 0 Z Zero Flag The zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information. RW 0 C Carry Flag The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software. RW 0 SPL Stack Pointer Low Byte $3D $5D io_sreg.bmp N SP7 Stack Pointer Bit 7 RW 0 SP6 Stack Pointer Bit 6 RW 0 SP5 Stack Pointer Bit 5 RW 0 SP4 Stack Pointer Bit 4 RW 0 SP3 Stack Pointer Bit 3 RW 0 SP2 Stack Pointer Bit 2 RW 0 SP1 Stack Pointer Bit 1 RW 0 SP0 Stack Pointer Bit 0 RW 0 SPMCSR Store Program Memory Control and Status register $37 $57 io_sreg.bmp Y CTPB Clear Temporary Page Buffer If the CTPB bit is written while filling the temporary page buffer, the temporary page buffer will be cleared and the data will be lost. RW 0 RFLB Read Fuse and Lock Bits An LPM instruction within three cycles after RFLB and SPMEN are set in the SPMCSR Register, will read either the Lock bits or the Fuse bits (depending on Z0 in the Zpointer) into the destination register. RW 0 PGWRT Page Write If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a Page Write, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page Write operation. RW 0 PGERS Page Erase If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Erase. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a Page Erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page Write operation. RW 0 SPMEN Store Program Memory Enable This bit enables the SPM instruction for the next four clock cycles. If written to one together with either CTPB, RFLB, PGWRT, or PGERS, the following SPM instruction will have a special meaning, see description above. If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer. The LSB of the Z-pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During Page Erase and Page Write, the SPMEN bit remains high until the operation is completed. Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in the lower five bits will have no effe RW 0 MCUCR MCU Control Register The MCU Control Register contains control bits for general MCU functions. $35 $55 io_cpu.bmp Y PUD Pull-up Disable RW 0 SM1 Sleep Mode Select Bit 1 R 0 SE Sleep Enable The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmers purpose, it is recommended to set the Sleep Enable SE bit just before the execution of the SLEEP instruction. R 0 SM0 SM Sleep Mode Select Bit 0 RW 0 ISC11 Interrupt Sense Control 1 bit 1 RW 0 ISC10 Interrupt Sense Control 1 bit 0 R 0 ISC01 Interrupt Sense Control 0 bit 1 R 0 ISC00 Interrupt Sense Control 0 bit 0 R 0 MCUSR MCU Status register The MCU Status Registerprovides information on which reset source caused a MCU reset. $34 $54 io_cpu.bmp Y WDRF Watchdog Reset Flag RW 0 BORF Brown-out Reset Flag RW 0 EXTRF External Reset Flag After a power-on reset, this bit is undefined (X). It will be set by an external reset. A watchdog reset will leave this bit unchanged. RW 0 PORF Power-On Reset Flag This bit is set by a power-on reset. A watchdog reset or an external reset will leave this bit unchanged RW 0 OSCCAL Oscillator Calibration Register $31 $51 io_sreg.bmp N CAL6 Oscillatro Calibration Value Bit 6 RW 0 CAL5 Oscillatro Calibration Value Bit 5 RW 0 CAL4 Oscillatro Calibration Value Bit 4 RW 0 CAL3 Oscillatro Calibration Value Bit 3 RW 0 CAL2 Oscillatro Calibration Value Bit 2 RW 0 CAL1 Oscillatro Calibration Value Bit 1 RW 0 CAL0 Oscillatro Calibration Value Bit 0 RW 0 CLKPR Clock Prescale Register $26 $46 io_cpu.bmp Y CLKPCE Clock Prescaler Change Enable The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is cleared by hardware four cycles after it is written or when CLKPS bits are written. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the CLKPCE bit. RW 0 CLKPS3 Clock Prescaler Select Bit 3 RW 0 CLKPS2 Clock Prescaler Select Bit 2 RW 0 CLKPS1 Clock Prescaler Select Bit 1 RW 0 CLKPS0 Clock Prescaler Select Bit 0 RW 0 GTCCR SFIOR General Timer Counter Control Register $23 $43 io_sreg.bmp Y PSR10 RW 0 PCMSK Pin-Change Mask register $20 $40 io_sreg.bmp N PCINT7 Pin-Change Interrupt 7 RW 0 PCINT6 Pin-Change Interrupt 6 RW 0 PCINT5 Pin-Change Interrupt 5 RW 0 PCINT4 Pin-Change Interrupt 4 RW 0 PCINT3 Pin-Change Interrupt 3 RW 0 PCINT2 Pin-Change Interrupt 2 RW 0 PCINT1 Pin-Change Interrupt 1 RW 0 PCINT0 Pin-Change Interrupt 0 RW 0 GPIOR2 General Purpose I/O Register 2 $15 $35 io_sreg.bmp N GPIOR27 General Purpose I/O Register 2 bit 7 RW 0 GPIOR26 General Purpose I/O Register 2 bit 6 RW 0 GPIOR25 General Purpose I/O Register 2 bit 5 RW 0 GPIOR24 General Purpose I/O Register 2 bit 4 RW 0 GPIOR23 General Purpose I/O Register 2 bit 3 RW 0 GPIOR22 General Purpose I/O Register 2 bit 2 RW 0 GPIOR21 General Purpose I/O Register 2 bit 1 RW 0 GPIOR20 General Purpose I/O Register 2 bit 0 RW 0 GPIOR1 General Purpose I/O Register 1 $14 $34 io_sreg.bmp N GPIOR17 General Purpose I/O Register 1 bit 7 RW 0 GPIOR16 General Purpose I/O Register 1 bit 6 RW 0 GPIOR15 General Purpose I/O Register 1 bit 5 RW 0 GPIOR14 General Purpose I/O Register 1 bit 4 RW 0 GPIOR13 General Purpose I/O Register 1 bit 3 RW 0 GPIOR12 General Purpose I/O Register 1 bit 2 RW 0 GPIOR11 General Purpose I/O Register 1 bit 1 RW 0 GPIOR10 General Purpose I/O Register 1 bit 0 RW 0 GPIOR0 General Purpose I/O Register 0 $13 $33 io_sreg.bmp N GPIOR07 General Purpose I/O Register 0 bit 7 RW 0 GPIOR06 General Purpose I/O Register 0 bit 6 RW 0 GPIOR05 General Purpose I/O Register 0 bit 5 RW 0 GPIOR04 General Purpose I/O Register 0 bit 4 RW 0 GPIOR03 General Purpose I/O Register 0 bit 3 RW 0 GPIOR02 General Purpose I/O Register 0 bit 2 RW 0 GPIOR01 General Purpose I/O Register 0 bit 1 RW 0 GPIOR00 General Purpose I/O Register 0 bit 0 RW 0 [USIDR:USISR:USICR] io_com.bmp Universal Serial Interface USIDR USI Data Register $0F $2F io_com.bmp N USIDR7 USI Data Register bit 7 RW 0 USIDR6 USI Data Register bit 6 RW 0 USIDR5 USI Data Register bit 5 RW 0 USIDR4 USI Data Register bit 4 RW 0 USIDR3 USI Data Register bit 3 RW 0 USIDR2 USI Data Register bit 2 RW 0 USIDR1 USI Data Register bit 1 RW 0 USIDR0 USI Data Register bit 0 RW 0 USISR USI Status Register $0E $2E io_flag.bmp Y USISIF Start Condition Interrupt Flag RW 0 USIOIF Counter Overflow Interrupt Flag RW 0 USIPF Stop Condition Flag RW 1 USIDC Data Output Collision RW 0 USICNT3 USI Counter Value Bit 3 RW 0 USICNT2 USI Counter Value Bit 2 RW 0 USICNT1 USI Counter Value Bit 1 RW 0 USICNT0 USI Counter Value Bit 0 RW 0 USICR USI Control Register $0D $2D io_flag.bmp Y USISIE Start Condition Interrupt Enable RW 0 USIOIE Counter Overflow Interrupt Enable RW 0 USIWM1 USI Wire Mode Bit 1 RW 1 USIWM0 USI Wire Mode Bit 0 RW 0 USICS1 USI Clock Source Select Bit 1 RW 0 USICS0 USI Clock Source Select Bit 0 RW 0 USICLK Clock Strobe R 0 USITC Toggle Clock Port Pin W 0 [ICEPRO:SIMULATOR:JTAGICEmkII:ICE50:STK500:STK500_2:AVRISPmkII:AVRDragon] 0x10 0x0a 0x08 0x00 0x78 0x00 0x81 AVRSimCoreV2.SimCoreV2 AVRSimMemory8bit.SimMemory8bit AVRSimInterrupt.SimInterrupt 0x11 0 12 AVRSimIOPort.SimIOPort 0x07 Y AVRSimIOPort.SimIOPort 0xff Y AVRSimIOPort.SimIOPort 0x7F Y AVRSimIOExtInterrupt.SimIOExtInterrupt 0x01 0x3b 0x40 0x3a 0x40 0x10 0x04 0x35 0x03 AVRSimIOExtInterrupt.SimIOExtInterrupt 0x02 0x3b 0x80 0x3a 0x80 0x10 0x08 0x35 0x0c AVRSimIOPinChangeInterrupt.SimIOPinChangeInterrupt 0x0B 0x3B 0x20 0x3A 0x20 0x20 0x16 0xFF AvrSimIOTim8pwmsync2.tim8pwmsync2 0x06 0x0D 0x0E PORTB 2 PORTD 5 PIND 4 AVRSimIOTimert16pwm1.SimIOTimert16pwm1 0x03 0x04 0x0C 0x05 0x10 0x20 0x10 0x40 0x18 0x08 0x18 0x10 AVRSimAC.SimIOAC 0x0A AVRSimIOUsart.SimIOUsart 0x07 0x09 0x08 0x10 0x02 0x10 0x01 AvrSimUSI.SimUSI 0x10 0x0F 0x99 0xff 0xe1 0xff 0x910A DebugWire 0x0E,0xEF,0xFF,0x7F,0x3F,0xFF,0x7F,0xBF 0x0E,0xA6,0xBE,0x7D,0x39,0xFF,0x7D,0xBA 0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00 0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 0x00 0X00 0X00 32 4 0x0000 0x0000 0x0000 0x0000 0x0000 0x00 0x800 0x0000,32 0x0020,64 0x00 0x80 0x00 0x00 0x20 0x00 0xBB, 0xFE, 0xBB, 0xEE, 0xBB, 0xCC, 0xB2, 0x0D, 0xBA, 0x0F, 0xB2, 0x0F, 0xBA, 0x0D, 0xBB, 0xBC, 0x99, 0xE1, 0xBB, 0xAC 0xB2, 0x0F, 0x1F 0x3e 0x3d 0x1F 0x00 0x00 0x00 0x00 0x00 0x3c 0x05 0x0F 0x0F 0x0F 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x0F 0x0F 0x05 0x15 0x14 0x14 0x000000DF 0x00000000 0x00000000 0x00000000 0x0000007F 0x000007FF 0x000003FF 0x000003FF 0x000003FF 0x000003FF 0x000000DF 0x0000FFFF 0x0000007F 0x00000000 0x00000000 0x00000000 0x0023FFFF 0x00000FFF 0x0000005F 0xFF 0xDF 0x62 0xff 0x51 0x67 ATtiny2313.bin 0x02 0x00 1000000 20000000 7 2 ; INTOSC = 1, INTRC=2;EXTCLK=4 1 ;NOTUSE = 1, EXTERNAL = 4, INTERNAL = 2 1 0 0x00 0x00 8 0x80 0x00000040 0x00000000 CKOUT fuse 0x00000040 0x00000040 CKOUT fuse 0x00010000 0x00000000 SELFPRGEN Fuse 0x00010000 0x00010000 SELFPRGEN Fuse 0x00000031 0x00000000 258CK, 14CK +4.1ms 0x00000031 0x00000010 258CK, 14CK +65ms 0x00000031 0x00000020 1kCK, 14CK 0x00000031 0x00000030 1kCK, 14CK +4.1ms 0x0000000c 0x00000000 6 CK, 14CK 0x00000031 0x00000001 1kCK, 14CK +65ms 0x00000031 0x00000011 16kCK, 14CK 0x0000000c 0x00000000 6 CK, 14CK 0x00000031 0x00000021 16kCK, 14CK +4.1ms 0x0000000c 0x00000000 6 CK, 14CK 0x00000031 0x00000031 16kCK, 14CK +65ms 0x0000000c 0x00000000 6 CK, 14CK 0x00000030 0x00000000 6 CK, 14CK 0x00000030 0x00000010 6 CK, 14CK+4ms 0x00000030 0x00000020 6 CK, 14CK+64 ms 0x00000030 0x00000000 6 CK, 14CK 0x00000030 0x00000010 6 CK, 14CK+4ms 0x00000030 0x00000020 6 CK, 14CK+64 ms 0x0000000e 0x0000000e 0x0000000f 0x00000004 8 0x0000000f 0x00000002 4 0x0000000f 0x00000000 0x00001000 0x00000000 Watchdog always ON 0x00001000 0x00001000 Watchdog disabled 0x00000100 0x00000000 RSTDSBL Fuse 0x00000100 0x00000100 RSTDSBL 8 0x00000080 0x00000000 CKDIV8 Fuse 0x00000080 0x00000080 CKDIV8 0x00000E00 0x00000E00 BOD disabled 0x00000E00 0x00000C00 BOD enabled, 1.8 V 0x00000E00 0x00000A00 BOD enabled, 2.7 V 0x00000E00 0x00000800 BOD enabled, 4.3 V 0x23 1 1 1 0xFF 0xFF 0xFF 0 1 0xD4 0xD6 2001002532030x53114510x4132100x400x4C0x000x000x000x41460xC10xC20x000x000x0025625644440x0E 0x1E 0x0E 0x1E 0x2E 0x3E 0x2E 0x3E 0x4E 0x5E 0x4E 0x5E 0x6E 0x7E 0x6E 0x7E 0x26 0x36 0x66 0x76 0x2A 0x3A 0x6A 0x7A 0x2E 0xFD 0x00 0x01 0x00 0x00 0x00 0x001000511510151501050x0B25625650x052562560505