[ADMIN:CORE:PACKAGE:INTERRUPT_VECTOR:LOCKBIT:FUSE:MEMORY:PROGRAMMING:IO_MODULE:ICE_SETTINGS]ATtiny2420MHZ82RELEASED$1E$91$0BV2AVRSimCoreV2.SimCoreV2[lpm rd,z+][][]32$00$1B$1A$1D$1C$1F$1E[SOIC:MLF]14[VCC][PB0:PCINT8:XTAL1][PB1:PCINT9:XTAL2][PB3:PCINT11:'RESET:dW][PB2:PCINT10:INT0:OC0A:CKOUT][PA7:PCINT7:ICP1:OC0B:ADC7][PA6:PCINT6:OC1A:DI:SDA:MOSI:ADC6][PA5:ADC5:DO:MISO:OC1B:PCINT5][PA4:ADC4:USCK:SCL:T1:PCINT4][PA3:ADC3:T0:PCINT3][PA2:ADC2:AIN1:PCINT2][PA1:ADC1:AIN0:PCINT1][PA0:ADC0:AREF:PCINT0][GND]20[PA4:ADC4:USCK:SCL:T1:PCINT4][PA3:ADC3:T0:PCINT3][PA2:ADC2:AIN1:PCINT2][PA1:ADC1:AIN0:PCINT1][PA0:ADC0:AREF:PCINT0]NCNC[GND][VCC]NC[PB0:PCINT8:XTAL1][PB1:PCINT9:XTAL2][PB3:PCINT11:'RESET:dW][PB2:PCINT10:INT0:OC0A:CKOUT][PA7:PCINT7:ICP1:OC0B:ADC7][PA6:PCINT6:OC1A:DI:SDA:MOSI:ADC6]NCNCNC[PA5:ADC5:DO:MISO:OC1B:PCINT5]17$000External Pin, Power-on Reset, Brown-out Reset,Watchdog Reset$001External Interrupt Request 0$002Pin Change Interrupt Request 0$003Pin Change Interrupt Request 1$004Watchdog Time-out$005Timer/Counter1 Capture Event$006Timer/Counter1 Compare Match A$007Timer/Counter1 Compare Match B$008Timer/Counter1 Overflow$009Timer/Counter0 Compare Match A$00ATimer/Counter0 Compare Match B$00BTimer/Counter0 Overflow$00CAnalog Comparator$00DADC Conversion Complete$00EEEPROM Ready$00FUSI START$010USI Overflow[LB1 = 1 : LB2 = 1] No memory lock features enabled. [LB1 = 0 : LB2 = 1] Further programming of Flash and EEPROM is enabled. [LB1 = 0 : LB2 = 0] Same as previous, but verify is also disabled320x030x03Mode 1: No memory lock features enabled0x030x02Mode 2: Further programming disabled0x030x00Mode 3: Further programming and verification disabledLB1LockbitLB2Lockbit[LOW:HIGH:EXTENDED]4680x800x00Divide clock by 8 internally; [CKDIV8=0]0x400x00Clock output on PORTB2; [CKOUT=0]0x3F0x00Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms; [CKSEL=0000 SUT=00]0x3F0x10Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms; [CKSEL=0000 SUT=01]0x3F0x20Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms; [CKSEL=0000 SUT=10]0x3F0x02Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms; [CKSEL=0010 SUT=00]0x3F0x12Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4 ms; [CKSEL=0010 SUT=01]0x3F0x22Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 64 ms; [CKSEL=0010 SUT=10]; default value0x3F0x04WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms; [CKSEL=0100 SUT=00]0x3F0x14WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4 ms; [CKSEL=0100 SUT=01]0x3F0x24WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 64 ms; [CKSEL=0100 SUT=10]0x3F0x06Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 0 ms; [CKSEL=0110 SUT=00] 0x3F0x16Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4 ms; [CKSEL=0110 SUT=01] 0x3F0x26Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 64 ms; [CKSEL=0110 SUT=10] 0x3F0x08Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms; [CKSEL=1000 SUT=00] 0x3F0x18Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms; [CKSEL=1000 SUT=01] 0x3F0x28Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms; [CKSEL=1000 SUT=10] 0x3F0x38Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms; [CKSEL=1000 SUT=11] 0x3F0x09Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms; [CKSEL=1001 SUT=00] 0x3F0x19Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms; [CKSEL=1001 SUT=01] 0x3F0x29Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms; [CKSEL=1001 SUT=10] 0x3F0x39Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms; [CKSEL=1001 SUT=11] 0x3F0x0AExt. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms; [CKSEL=1010 SUT=00] 0x3F0x1AExt. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms; [CKSEL=1010 SUT=01] 0x3F0x2AExt. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms; [CKSEL=1010 SUT=10] 0x3F0x3AExt. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms; [CKSEL=1010 SUT=11] 0x3F0x0BExt. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms; [CKSEL=1011 SUT=00] 0x3F0x1BExt. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms; [CKSEL=1011 SUT=01] 0x3F0x2BExt. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms; [CKSEL=1011 SUT=10] 0x3F0x3BExt. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms; [CKSEL=1011 SUT=11] 0x3F0x0CExt. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms; [CKSEL=1100 SUT=00] 0x3F0x1CExt. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms; [CKSEL=1100 SUT=01] 0x3F0x2CExt. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms; [CKSEL=1100 SUT=10] 0x3F0x3CExt. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms; [CKSEL=1100 SUT=11] 0x3F0x0DExt. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms; [CKSEL=1101 SUT=00] 0x3F0x1DExt. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms; [CKSEL=1101 SUT=01] 0x3F0x2DExt. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms; [CKSEL=1101 SUT=10] 0x3F0x3DExt. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms; [CKSEL=1101 SUT=11] 0x3F0x0EExt. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms; [CKSEL=1110 SUT=00] 0x3F0x1EExt. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms; [CKSEL=1110 SUT=01] 0x3F0x2EExt. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms; [CKSEL=1110 SUT=10] 0x3F0x3EExt. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms; [CKSEL=1110 SUT=11] 0x3F0x0FExt. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms; [CKSEL=1111 SUT=00] 0x3F0x1FExt. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms; [CKSEL=1111 SUT=01] 0x3F0x2FExt. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms; [CKSEL=1111 SUT=10] 0x3F0x3FExt. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms; [CKSEL=1111 SUT=11] CKSEL0Select Clock source0CKSEL1Select Clock source1CKSEL2Select Clock source0CKSEL3Select Clock source1SUT0Select start-up time0SUT1Select start-up time1CKOUTClock Output Enable1CKDIV8Divide clock by 801380x800x00Reset Disabled (Enable PB3 as i/o pin); [RSTDISBL=0]0x400x00Debug Wire enable; [DWEN=0]0x200x00Serial program downloading (SPI) enabled; [SPIEN=0]0x100x00Watch-dog Timer always on; [WDTON=0]0x080x00Preserve EEPROM memory through the Chip Erase cycle; [EESAVE=0]0x070x07Brown-out detection disabled; [BODLEVEL=111] 0x070x06Brown-out detection level at VCC=1.8 V; [BODLEVEL=110] 0x070x05Brown-out detection level at VCC=2.7 V; [BODLEVEL=101] 0x070x04Brown-out detection level at VCC=4.3 V; [BODLEVEL=100] 0x070x03Brown-out detection level at VCC=2.3 V; [BODLEVEL=011] 0x070x02Brown-out detection level at VCC=2.2 V; [BODLEVEL=010] 0x070x01Brown-out detection level at VCC=1.9 V; [BODLEVEL=001] 0x070x00Brown-out detection level at VCC=2.0 V; [BODLEVEL=000] BODLEVEL0Brown-out Detector trigger level1BODLEVEL1Brown-out Detector trigger level1BODLEVEL2Brown-out Detector trigger level1EESAVEEEPROM memory is preserved through the Chip Erase1WDTONWatchdog Timer always on1SPIENEnable Serial Program and Data Downloading0DWENDebugWIRE Enable1RSTDISBLExternal Reset disable1SELFPRGENSelf-Programming Enable1110x010x00Self Programming enable; [SELFPRGEN=0]AVRSimMemory8bit.SimMemory8bit2048128128$600NA$00$3FNANA$20$5F$3F$5F0x010x020x040x080x100x200x400x80$3D$5D0xDF0x010x020x040x080x100x200x400x80$3C$5C0x010x020x040x080x100x200x400x80$3B$5B0x100x200x40$3A$5A0x100x200x40$39$590x010x020x04$38$580x010x020x04$37$570x010x020x040x080x10$36$560x010x020x040x080x100x200x400x80$35$550x010x020x080x100x200x40$34$540x010x020x040x08$33$530x010x020x040x080x400x80$32$520x010x020x040x080x100x200x400x80$31$510x010x020x040x080x100x200x400x80$30$500x010x020x100x200x400x80$2F$4F0x010x020x100x200x400x80$2E$4E0x010x020x040x080x100x400x80$2D$4D0x010x020x040x080x100x200x400x80$2C$4C0x010x020x040x080x100x200x400x80$2B$4B0x010x020x040x080x100x200x400x80$2A$4A0x010x020x040x080x100x200x400x80$29$490x010x020x040x080x100x200x400x80$28$480x010x020x040x080x100x200x400x80$27$47$26$460x010x020x040x080x80$25$450x010x020x040x080x100x200x400x80$24$440x010x020x040x080x100x200x400x80$23$430x010x80$22$420x400x80$21$410x010x020x040x080x100x200x400x80$20$400x010x020x040x08$1F$3F0x01$1E$3E0x010x020x040x080x100x200x400x80$1D$3D0x010x020x040x080x100x200x400x80$1C$3C0x010x020x040x080x100x20$1B$3B0x010x020x040x080x100x200x400x80$1A$3A0x010x020x040x080x100x200x400x80$19$390x010x020x040x080x100x200x400x80$18$380x010x020x040x08$17$370x010x020x040x08$16$360x010x020x040x08$15$350x010x020x040x080x100x200x400x80$14$340x010x020x040x080x100x200x400x80$13$330x010x020x040x080x100x200x400x80$12$320x010x020x040x080x100x200x400x80$10$300x010x020x040x080x100x200x400x80$0F$2F0x010x020x040x080x100x200x400x80$0E$2E0x010x020x040x080x100x200x400x80$0D$2D0x010x020x040x080x100x200x400x80$0C$2C0x010x020x040x20$0B$2B0x010x020x040x20$08$280x010x020x040x080x100x200x400x80$07$270x010x020x040x080x100x200x400x80$06$260x010x020x040x080x100x200x400x80$05$250x010x020x040x080x100x200x400x80$04$240x010x020x040x080x100x200x400x80$03$230x400x010x020x040x100x80$01$210x010x020x040x080x100x200x400x80$00$200x010x020x040x08$0$3FF$0$0160xff,0xdf, 0x010xff,0xdf, 0x011,0x20,0x20,WARNING! These fuse settings will disable the ISP interface!1,0x40,0x00,WARNING! Enabling DEBUGWIRE will make the ISP interface inaccessible!1,0x80,0x00,WARNING! Disabling external reset will make the ISP interface inaccessible!1,0x20,0x20,WARNING! These fuse settings will disable the ISP interface!1,0x40,0x00,WARNING! Enabling DEBUGWIRE will make the ISP interface inaccessible!1,0x80,0x00,WARNING! Disabling external reset will make the ISP interface inaccessible!0x00,8.0 MHz324[PORTA:PORTB:ANALOG_COMPARATOR:AD_CONVERTER:USI:EXTERNAL_INTERRUPT:EEPROM:WATCHDOG:TIMER_COUNTER_0:TIMER_COUNTER_1:CPU:BOOT_LOAD][PORTA:DDRA:PINA]io_port.bmpAVRSimIOPort.SimIOPortPORTAPort A Data Register$1B$3Bio_port.bmpNPORTA7Port A Data Register bit 7RW0PORTA6Port A Data Register bit 6RW0PORTA5Port A Data Register bit 5RW0PORTA4Port A Data Register bit 4RW0PORTA3Port A Data Register bit 3RW0PORTA2Port A Data Register bit 2RW0PORTA1Port A Data Register bit 1RW0PORTA0Port A Data Register bit 0RW0DDRAPort A Data Direction Register$1A$3Aio_flag.bmpNDDA7Data Direction Register, Port A, bit 7RW0DDA6Data Direction Register, Port A, bit 6RW0DDA5Data Direction Register, Port A, bit 5RW0DDA4Data Direction Register, Port A, bit 4RW0DDA3Data Direction Register, Port A, bit 3RW0DDA2Data Direction Register, Port A, bit 2RW0DDA1Data Direction Register, Port A, bit 1RW0DDA0Data Direction Register, Port A, bit 0RW0PINAPort A Input PinsThe Port A Input Pins address - PINA - is not a register, and this address enables access to the physical value on each Port A pin. When reading PORTA the Port A Data Latch is read, and when reading PINA, the logical values present on the pins are read.$19$39io_port.bmpNPINA7Input Pins, Port A bit 7RWHi-ZPINA6Input Pins, Port A bit 6RWHi-ZPINA5Input Pins, Port A bit 5RWHi-ZPINA4Input Pins, Port A bit 4RWHi-ZPINA3Input Pins, Port A bit 3RWHi-ZPINA2Input Pins, Port A bit 2RWHi-ZPINA1Input Pins, Port A bit 1RWHi-ZPINA0Input Pins, Port A bit 0RWHi-Z[PORTB:DDRB:PINB]io_port.bmpAVRSimIOPort.SimIOPortPORTBData Register, Port B$18$38io_port.bmpNPORTB3RW0PORTB2RW0PORTB1RW0PORTB0RW0DDRBData Direction Register, Port B$17$37io_flag.bmpNDDB3RW0DDB2RW0DDB1RW0DDB0RW0PINBInput Pins, Port B$16$36io_port.bmpNPINB3R0PINB2R0PINB1R0PINB0R0[ADCSRB:ACSR:DIDR0]io_analo.bmpAlgComp_01ADCSRBADC Control and Status Register B$03$23io_flag.bmpYACMEAnalog Comparator Multiplexer EnableWhen this bit is written logic one and the ADC is switched off (ADEN in ADCSR is zero), the ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed description of this bit, see “Analog Comparator Multiplexed Input” on page 186.RW0ACSRAnalog Comparator Control And Status Register$08$28io_analo.bmpYACDAnalog Comparator DisableWhen this bit is written logic one, the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.RW0ACBGAINBGAnalog Comparator Bandgap SelectWhen this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. See “Internal Voltage Reference” on page 42.RW0ACOAnalog Compare OutputThe output of the analog comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1-2 clock cycles.RNAACIAnalog Comparator Interrupt FlagThis bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hard-ware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.RW0ACIEAnalog Comparator Interrupt EnableWhen the ACIE bit is written logic one and the I-bit in the Status Register is set, the analog comparator interrupt is acti-vated. When written logic zero, the interrupt is disabled.RW0ACICAnalog Comparator Input Capture EnableWhen written logic one, this bit enables the input capture function in Timer/Counter1 to be triggered by the Analog Comparator.R0ACIS1Analog Comparator Interrupt Mode Select bit 1These bits determine which comparator events that trigger the Analog Comparator interrupt.RW0ACIS0Analog Comparator Interrupt Mode Select bit 0These bits determine which comparator events that trigger the Analog Comparator interrupt.RW0DIDR0$01$21YADC1DADC 1 Digital input buffer disableWhen this bit is written logic one,the digital input buffer on the AIN1 pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer.RW0ADC0DADC 0 Digital input buffer disableWhen this bit is written logic one,the digital input buffer on the AIN0 pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer.RW0[ADMUX:ADCSRA:ADCH:ADCL:ADCSRB:DIDR0]io_analo.bmpADMUXADC Multiplexer Selection Register$07$27io_analo.bmpNREFS1Reference Selection Bit 1RW0REFS0Reference Selection Bit 0RW0MUX5Analog Channel and Gain Selection Bit 5RW0MUX4Analog Channel and Gain Selection Bit 4RW0MUX3Analog Channel and Gain Selection Bit 3RW0MUX2Analog Channel and Gain Selection Bit 2RW0MUX1Analog Channel and Gain Selection Bit 1RW0MUX0Analog Channel and Gain Selection Bit 0RW0ADCSRAADC Control and Status Register A$06$26io_flag.bmpYADENADC EnableWriting a logical ‘1’ to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.RW0ADSCADC Start ConversionIn Single Conversion Mode, a logical ‘1’ must be written to this bit to start each conversion. In Free Running Mode, a logical ‘1’ must be written to this bit to start the first conversion. The first time ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, an extended conversion will result. This extended conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. When a dummy conversion precedes a real conversion, ADSC will stay high until the real conversion completes. Writing a 0 to this bit has no effecRW0ADATEADC Auto Trigger EnableWhen this bit is written to one,Auto Triggering of the ADC is enabled.The ADC will start a conversion on a positive edge of the selected trigger signal.The trigger source is selected by setting the ADC Trigger Select bits,ADTS in ADCSRB. RW0ADIFADC Interrupt FlagThis bit is set (one) when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set (one). ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a read-modify-write on ADCSR, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used.RW0ADIEADC Interrupt EnableWhen this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Complete Interrupt is activated.RW0ADPS2ADC Prescaler Select Bit 2These bits determine the division factor between the XTAL frequency and the input clock to the ADC.RW0ADPS1ADC Prescaler Select Bit 1These bits determine the division factor between the XTAL frequency and the input clock to the ADC.RW0ADPS0ADC Prescaler Select Bit 0These bits determine the division factor between the XTAL frequency and the input clock to the ADC.RW0ADCHADC Data Register High ByteWhen an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. The selected channel is differential if MUX4..0 are between ‘01000’ and ‘11101’, otherwise the selected channel is single ended. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8 bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUX4..0 bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right $05$25io_analo.bmpNADCH7ADC Data Register High Byte Bit 7RW0ADCH6ADC Data Register High Byte Bit 6RW0ADCH5ADC Data Register High Byte Bit 5RW0ADCH4ADC Data Register High Byte Bit 4RW0ADCH3ADC Data Register High Byte Bit 3RW0ADCH2ADC Data Register High Byte Bit 2RW0ADCH1ADC Data Register High Byte Bit 1RW0ADCH0ADC Data Register High Byte Bit 0RW0ADCLADC Data Register Low ByteWhen an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. The selected channel is differential if MUX4..0 are between ‘01000’ and ‘11101’, otherwise the selected channel is single ended. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8 bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUX4..0 bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right$04$24io_analo.bmpNADCL7ADC Data Register Low Byte Bit 7RW0ADCL6ADC Data Register Low Byte Bit 6RW0ADCL5ADC Data Register Low Byte Bit 5RW0ADCL4ADC Data Register Low Byte Bit 4RW0ADCL3ADC Data Register Low Byte Bit 3RW0ADCL2ADC Data Register Low Byte Bit 2RW0ADCL1ADC Data Register Low Byte Bit 1RW0ADCL0ADC Data Register Low Byte Bit 0RW0ADCSRBADC Control and Status Register B$03$23io_analo.bmpYBINBipolar Input ModeThe gain stage is working in the unipolar mode as default, but the bipolar mode can be selected by writing the BIN bit in the ADCSRB register.R0ADLARADC Left Adjust ResultRW0ADTS2ADC Auto Trigger Source bit 2If ADATE in ADCSRA is written to one,the value of these bits selects which source will trigger an ADC conversion.If ADATE is cleared,the ADTS2:0 settings will have no effect.A conversion will be triggered by the rising edge of the selected interrupt flag.Note that switching from a trigger source that is cleared to a trigger source that is set,will generate a positive edge on the trigger signal.If ADEN in ADCSRA is set,this will start a conversion.Switching to Free Running Mode (ADTS [2:0 ]=0)will not cause a trigger event,even if the ADC Interrupt Flag is set . RW0ADTS1ADC Auto Trigger Source bit 1If ADATE in ADCSRA is written to one,the value of these bits selects which source will trigger an ADC conversion.If ADATE is cleared,the ADTS2:0 settings will have no effect.A conversion will be triggered by the rising edge of the selected interrupt flag.Note that switching from a trigger source that is cleared to a trigger source that is set,will generate a positive edge on the trigger signal.If ADEN in ADCSRA is set,this will start a conversion.Switching to Free Running Mode (ADTS [2:0 ]=0)will not cause a trigger event,even if the ADC Interrupt Flag is set . RW0ADTS0ADC Auto Trigger Source bit 0If ADATE in ADCSRA is written to one,the value of these bits selects which source will trigger an ADC conversion.If ADATE is cleared,the ADTS2:0 settings will have no effect.A conversion will be triggered by the rising edge of the selected interrupt flag.Note that switching from a trigger source that is cleared to a trigger source that is set,will generate a positive edge on the trigger signal.If ADEN in ADCSRA is set,this will start a conversion.Switching to Free Running Mode (ADTS [2:0 ]=0)will not cause a trigger event,even if the ADC Interrupt Flag is set . RW0DIDR0Digital Input Disable Register 0$01$21io_analo.bmpNADC7DADC7 Digital Input DisableRW0ADC6DADC6 Digital Input DisableRW0ADC5DADC5 Digital Input DisableRW0ADC4DADC4 Digital Input DisableRW0ADC3DADC3 Digital Input DisableRW0ADC2DADC2 Digital Input DisableRW0ADC1DADC1 Digital Input DisableRW0ADC0DADC0 Digital Input DisableRW0[USIBR:USIDR:USISR:USICR]io_com.bmpUniversal Serial InterfaceUSIBRUSI Buffer Register$10$30io_com.bmpNUSIBR7USI Buffer Register bit 7R0USIBR6USI Buffer Register bit 6R0USIBR5USI Buffer Register bit 5R0USIBR4USI Buffer Register bit 4R0USIBR3USI Buffer Register bit 3R0USIBR2USI Buffer Register bit 2R0USIBR1USI Buffer Register bit 1R0USIBR0USI Buffer Register bit 0R0USIDRUSI Data Register$0F$2Fio_com.bmpNUSIDR7USI Data Register bit 7RW0USIDR6USI Data Register bit 6RW0USIDR5USI Data Register bit 5RW0USIDR4USI Data Register bit 4RW0USIDR3USI Data Register bit 3RW0USIDR2USI Data Register bit 2RW0USIDR1USI Data Register bit 1RW0USIDR0USI Data Register bit 0RW0USISRUSI Status Register$0E$2Eio_flag.bmpYUSISIFStart Condition Interrupt FlagRW0USIOIFCounter Overflow Interrupt FlagRW0USIPFStop Condition FlagRW1USIDCData Output CollisionRW0USICNT3USI Counter Value Bit 3RW0USICNT2USI Counter Value Bit 2RW0USICNT1USI Counter Value Bit 1RW0USICNT0USI Counter Value Bit 0RW0USICRUSI Control Register$0D$2Dio_flag.bmpYUSISIEStart Condition Interrupt EnableRW0USIOIECounter Overflow Interrupt EnableRW0USIWM1USI Wire Mode Bit 1RW1USIWM0USI Wire Mode Bit 0RW0USICS1USI Clock Source Select Bit 1RW0USICS0USI Clock Source Select Bit 0RW0USICLKClock StrobeR0USITCToggle Clock Port PinW0[MCUCR:GIMSK:GIFR:PCMSK1:PCMSK0]io_ext.bmpMCUCRMCU Control Register$35$55io_cpu.bmpYISC01Interrupt Sense Control 0 Bit 1RW0ISC00Interrupt Sense Control 0 Bit 0RW0GIMSKGICRGeneral Interrupt Mask Register$3B$5Bio_flag.bmpYINT0External Interrupt Request 0 EnableWhen the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from program memory address $001. See also “External Interrupts.” • Bits 5..0 - Res: Reserved bitsRW0PCIE1Pin Change Interrupt Enable 1RW0PCIE0Pin Change Interrupt Enable 0RW0GIFRGeneral Interrupt Flag register$3A$5Aio_flag.bmpYINTF0External Interrupt Flag 0When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the interrupt vector at address $001. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. RW0PCIF1Pin Change Interrupt Flag 1RW0PCIF0Pin Change Interrupt Flag 0RW0PCMSK1Pin Change Enable Mask 1$20$40io_flag.bmpNPCINT11Pin Change Enable Mask Bit 11RW1PCINT10Pin Change Enable Mask Bit 10RW1PCINT9Pin Change Enable Mask Bit 9RW1PCINT8Pin Change Enable Mask Bit 8RW1PCMSK0Pin Change Enable Mask 0$12$32io_flag.bmpNPCINT7Pin Change Enable Mask Bit 7RW1PCINT6Pin Change Enable Mask Bit 6RW1PCINT5Pin Change Enable Mask Bit 5RW1PCINT4Pin Change Enable Mask Bit 4RW1PCINT3Pin Change Enable Mask Bit 3RW1PCINT2Pin Change Enable Mask Bit 2RW1PCINT1Pin Change Enable Mask Bit 1RW1PCINT0Pin Change Enable Mask Bit 0RW1[EEARL:EEARH:EEDR:EECR]io_cpu.bmpEEPROM Read/Write Access. The EEPROM access registers are accessible in the I/O space. The write access time for the EEPROM is given in Table 1. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page 19. for details on how to avoid problems in these situations.In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When theEEPROM is written, the CPU is halted for two clock cycles before the next instruction is executEEARHEEPROM Address Register High Byte$1F$3Fio_cpu.bmpNEEAR8EEPROM Read/Write Access Bit 0RW0EEARLEEPROM Address Register Low Byte$1E$3Eio_cpu.bmpNEEAR7EEPROM Read/Write Access Bit 7RW0EEAR6EEPROM Read/Write Access Bit 6RW0EEAR5EEPROM Read/Write Access Bit 5RW0EEAR4EEPROM Read/Write Access Bit 4RW0EEAR3EEPROM Read/Write Access Bit 3RW0EEAR2EEPROM Read/Write Access Bit 2RW0EEAR1EEPROM Read/Write Access Bit 1RW0EEAR0EEPROM Read/Write Access Bit 0RW0EEDREEPROM Data RegisterFor the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.$1D$3Dio_cpu.bmpNEEDR7EEPROM Data Register bit 7RW0EEDR6EEPROM Data Register bit 6RW0EEDR5EEPROM Data Register bit 5RW0EEDR4EEPROM Data Register bit 4RW0EEDR3EEPROM Data Register bit 3RW0EEDR2EEPROM Data Register bit 2RW0EEDR1EEPROM Data Register bit 1RW0EEDR0EEPROM Data Register bit 0RW0EECREEPROM Control Register$1C$3Cio_flag.bmpYEEPM1EEPROM Programming Mode Bit 1The EEPROM Programming mode bit setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in Table 2. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.RWXEEPM0EEPROM Programming Mode Bit 0The EEPROM Programming mode bit setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in Table 2. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.RWXEERIEEEPROM Ready Interrupt EnableEEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared.RW0EEMPEEEPROM Master Write EnableThe EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is written to one, writing EEWE to one within 4 clock cycles will write data to the EEPROM at the selected address. If EEMWE is zero, writing EEWE to one will have no effect. When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure.RW0EEPEEEPROM Write EnableThe EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential): 1. Wait until EEWE becomes zero. 2. Wait until SPMEN in SPMCR becomes zero. 3. Write new EEPROM address to EEAR (optional). 4. Write new EEPROM data to EEDR (optional). 5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR. 6. Within four clock cycles after setting EEMWE, write a logical one to EEWE. The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a boot loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See “Boot Loader Support - Read While Write self-programming” on page 228 for details about boot programming. Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR regis-ter will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the 4 last steps to avoid these problems. When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruc-tion is executedRWXEEREEEPROM Read EnableThe EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR register. The calibrated oscillator is used to time the EEPROM accesses. Table 1 lists the typical programming time for EEPROM access from the CPURW0[WDTCSR]io_watch.bmpWDTCSRWatchdog Timer Control Register$21$41io_flag.bmpYWDIFWatchdog Timeout Interrupt FlagRW0WDIEWatchdog Timeout Interrupt EnableRW0WDP3Watchdog Timer Prescaler Bit 3RW0WDCEWatchdog Change EnableRW0WDEWatch Dog EnableWhen the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdogRW0WDP2Watch Dog Timer Prescaler bit 2RW0WDP1Watch Dog Timer Prescaler bit 1RW0WDP0Watch Dog Timer Prescaler bit 0RW0[TIMSK0:TIFR0:TCCR0A:TCCR0B:TCNT0:OCR0A:OCR0B:GTCCR]io_timer.bmpTIMSK0Timer/Counter Interrupt Mask Register$39$59io_flag.bmpYOCIE0BTimer/Counter0 Output Compare Match B Interrupt EnableRW0OCIE0ATimer/Counter0 Output Compare Match A Interrupt EnableRW0TOIE0Timer/Counter0 Overflow Interrupt EnableRW0TIFR0Timer/Counter0 Interrupt Flag Register$38$58io_flag.bmpYOCF0BTimer/Counter0 Output Compare Flag BRW0OCF0ATimer/Counter0 Output Compare Flag ARW0TOV0Timer/Counter0 Overflow FlagRW0TCCR0ATimer/Counter Control Register A$30$50io_flag.bmpYCOM0A1Compare Match Output A Mode bit 1RW0COM0A0Compare Match Output A Mode bit 0RW0COM0B1Compare Match Output B Mode bit 1W0COM0B0Compare Match Output B Mode bit 0RW0WGM01Waveform Generation Mode bit 1RW0WGM00Waveform Generation Mode bit 0RW0TCCR0BTimer/Counter Control Register B$33$53io_flag.bmpYFOC0AForce Output Compare AW0FOC0BForce Output Compare BW0WGM02Waveform Generation Mode bit 2RW0CS02Clock Select bit 2RW0CS01Clock Select bit 1RW0CS00Clock Select bit 0RW0TCNT0Timer/Counter0The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT0 register blocks (removes) the compare match on the following timer clock. Modifying the counter (TCNT0) while the counter is running, introduces a risk of missing a compare match between TCNT0 the OCR0 register.$32$52io_timer.bmpNTCNT0_7RW0TCNT0_6RW0TCNT0_5RW0TCNT0_4RW0TCNT0_3RW0TCNT0_2RW0TCNT0_1RW0TCNT0_0RW0OCR0ATimer/Counter0 Output Compare Register A$36$56io_timer.bmpNOCR0_7RW0OCR0_6RW0OCR0_5RW0OCR0_4RW0OCR0_3RW0OCR0_2RW0OCR0_1RW0OCR0_0RW0OCR0BTimer/Counter0 Output Compare Register B$3C$5Cio_timer.bmpNOCR0_7RW0OCR0_6RW0OCR0_5RW0OCR0_4RW0OCR0_3RW0OCR0_2RW0OCR0_1RW0OCR0_0RW0GTCCRGeneral Timer/Counter Control Register$23$43io_flag.bmpYTSMTimer/Counter Synchronization ModeWriting the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSR2 and PSR10 bits is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSR2 and PSR10 bits are cleared by hardware, and the Timer/Counters start counting simultaneouslRW0PSR10Prescaler Reset Timer/CounterNWhen this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers.RW0[TIMSK1:TIFR1:TCCR1A:TCCR1B:TCCR1C:TCNT1H:TCNT1L:OCR1AH:OCR1AL:OCR1BH:OCR1BL:ICR1H:ICR1L]
[TCNT1H:TCNT1L];[OCR1AH:OCR1AL];[OCR1BH:OCR1BL];[ICR1H:ICR1L]
io_timer.bmpt16pwm1_13.xmlTIMSK1Timer/Counter1 Interrupt Mask Register$0C$2Cio_flag.bmpYICIE1Timer/Counter1 Input Capture Interrupt EnableWhen the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on pin ICP, i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.RW0OCIE1BTimer/Counter1 Output Compare B Match Interrupt EnableWhen the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt is executed if a CompareB match in Timer/Counter1 occurs, i.e., when the OCF1B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.RW0OCIE1ATimer/Counter1 Output Compare A Match Interrupt EnableWhen the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a CompareA match in Timer/Counter1 occurs, i.e., when the OCF1A bit is set in the Timer/Counter Interrupt Flag Register - TIFR.RW0TOIE1Timer/Counter1 Overflow Interrupt EnableWhen the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.RW0TIFR1Timer/Counter Interrupt Flag register$0B$2Bio_flag.bmpYICF1Timer/Counter1 Input Capture FlagThe ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to the input capture register - ICR1. ICF1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF1 is cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable), and ICF1 are set (one), the Timer/Counter1 Capture Interrupt is executed. RW0OCF1BTimer/Counter1 Output Compare B Match FlagThe OCF1B bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1B - Output Compare Register 1B. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare match InterruptB Enable), and the OCF1B are set (one), the Timer/Counter1 Compare B match Interrupt is executed. RW0OCF1ATimer/Counter1 Output Compare A Match FlagThe OCF1A bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare match InterruptA Enable), and the OCF1A are set (one), the Timer/Counter1 Compare A match Interrupt is executed. RW0TOV1Timer/Counter1 Overflow FlagThe TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the cor-responding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter1 changes counting direction at $0000.RW0TCCR1ATimer/Counter1 Control Register A$2F$4Fio_flag.bmpYCOM1A1Compare Output Mode 1A, bit 1The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA pin 1. This is an alternative function to an I/O port and the corresponding direction control bit must be set (one) to control the output pin. The control configuration is shown in the databook. RW0COM1A0Comparet Ouput Mode 1A, bit 0The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA pin 1. This is an alternative function to an I/O port and the corresponding direction control bit must be set (one) to control the output pin. The control configuration is shown in the databook. RW0COM1B1Compare Output Mode 1B, bit 1RW0COM1B0Comparet Ouput Mode 1B, bit 0RW0WGM11PWM11Pulse Width Modulator Select Bit 1RW0WGM10PWM10Pulse Width Modulator Select Bit 0RW0TCCR1BTimer/Counter1 Control Register B$2E$4Eio_flag.bmpYICNC1Input Capture 1 Noise CancelerWhen the ICNC1 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the ICP - input capture pin - as specified. When the ICNC1 bit is set (one), four successive samples are measures on the ICP - input capture pin, and all samples must be high/low according to the input capture trigger specification in the ICES1 bit. The actual sampling frequency is XTAL clock frequency.RW0ICES1Input Capture 1 Edge SelectWhile the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the falling edge of the input capture pin - ICP. While the ICES1 bit is set (one), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the rising edge of the input capture pin - ICP.RW0WGM13Waveform Generation Mode Bit 3RW0WGM12CTC1Waveform Generation Mode Bit 2RW0CS12Clock Select1 bit 2RW0CS11Clock Select 1 bit 1RW0CS10Clock Select bit 0RW0TCCR1CTimer/Counter1 Control Register C$22$42io_flag.bmpYFOC1AForce Output Compare for Channel AThe FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM mode. However, for ensuring compatibility with future devices, these bits must be set to zero when TCCR1A is written when operating in a PWM mode. When writing a logical one to the FOC1A/FOC1B bit, an immediate compare match is forced on the Waveform Generation unit. The OC1A/OC1B output is changed according to its COM1x1:0 bits setting. Note that the FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the COM1x1:0 bits that determine the effect of the forced compare. A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zeroRW0FOC1BForce Output Compare for Channel BThe FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM mode. However, for ensuring compatibility with future devices, these bits must be set to zero when TCCR1A is written when operating in a PWM mode. When writing a logical one to the FOC1A/FOC1B bit, an immediate compare match is forced on the Waveform Generation unit. The OC1A/OC1B output is changed according to its COM1x1:0 bits setting. Note that the FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the COM1x1:0 bits that determine the effect of the forced compare. A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zeroRW0TCNT1HTimer/Counter1 High ByteThis 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR1A, OCR1B and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt ro$2D$4Dio_timer.bmpNTCNT1H7Timer/Counter1 High Byte bit 7RW0TCNT1H6Timer/Counter1 High Byte bit 6RW0TCNT1H5Timer/Counter1 High Byte bit 5RW0TCNT1H4Timer/Counter1 High Byte bit 4RW0TCNT1H3Timer/Counter1 High Byte bit 3RW0TCNT1H2Timer/Counter1 High Byte bit 2RW0TCNT1H1Timer/Counter1 High Byte bit 1RW0TCNT1H0Timer/Counter1 High Byte bit 0RW0TCNT1LTimer/Counter1 Low ByteThis 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR1A, OCR1B and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrup$2C$4Cio_timer.bmpNTCNT1L7Timer/Counter1 Low Byte bit 7RW0TCNT1L6Timer/Counter1 Low Byte bit 6RW0TCNT1L5Timer/Counter1 Low Byte bit 5RW0TCNT1L4Timer/Counter1 Low Byte bit 4RW0TCNT1L3Timer/Counter1 Low Byte bit 3RW0TCNT1L2Timer/Counter1 Low Byte bit 2RW0TCNT1L1Timer/Counter1 Low Byte bit 1RW0TCNT1L0Timer/Counter1 Low Byte bit 0RW0OCR1AHTimer/Counter1 Output Compare Register A High ByteThe output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrup$2B$4Bio_timer.bmpNOCR1AH7Timer/Counter1 Output Compare Register High Byte bit 7RW0OCR1AH6Timer/Counter1 Output Compare Register High Byte bit 6RW0OCR1AH5Timer/Counter1 Output Compare Register High Byte bit 5RW0OCR1AH4Timer/Counter1 Output Compare Register High Byte bit 4RW0OCR1AH3Timer/Counter1 Output Compare Register High Byte bit 3RW0OCR1AH2Timer/Counter1 Output Compare Register High Byte bit 2RW0OCR1AH1Timer/Counter1 Output Compare Register High Byte bit 1RW0OCR1AH0Timer/Counter1 Output Compare Register High Byte bit 0RW0OCR1ALTimer/Counter1 Output Compare Register A Low ByteThe output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interru$2A$4Aio_timer.bmpNOCR1AL7Timer/Counter1 Output Compare Register Low Byte Bit 7RW0OCR1AL6Timer/Counter1 Output Compare Register Low Byte Bit 6RW0OCR1AL5Timer/Counter1 Output Compare Register Low Byte Bit 5RW0OCR1AL4Timer/Counter1 Output Compare Register Low Byte Bit 4RW0OCR1AL3Timer/Counter1 Output Compare Register Low Byte Bit 3RW0OCR1AL2Timer/Counter1 Output Compare Register Low Byte Bit 2RW0OCR1AL1Timer/Counter1 Output Compare Register Low Byte Bit 1RW0OCR1AL0Timer/Counter1 Output Compare Register Low Byte Bit 0RW0OCR1BHTimer/Counter1 Output Compare Register B High ByteThe output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrup$29$49io_timer.bmpNOCR1AH7Timer/Counter1 Output Compare Register High Byte bit 7RW0OCR1AH6Timer/Counter1 Output Compare Register High Byte bit 6RW0OCR1AH5Timer/Counter1 Output Compare Register High Byte bit 5RW0OCR1AH4Timer/Counter1 Output Compare Register High Byte bit 4RW0OCR1AH3Timer/Counter1 Output Compare Register High Byte bit 3RW0OCR1AH2Timer/Counter1 Output Compare Register High Byte bit 2RW0OCR1AH1Timer/Counter1 Output Compare Register High Byte bit 1RW0OCR1AH0Timer/Counter1 Output Compare Register High Byte bit 0RW0OCR1BLTimer/Counter1 Output Compare Register B Low ByteThe output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interru$28$48io_timer.bmpNOCR1AL7Timer/Counter1 Output Compare Register Low Byte Bit 7RW0OCR1AL6Timer/Counter1 Output Compare Register Low Byte Bit 6RW0OCR1AL5Timer/Counter1 Output Compare Register Low Byte Bit 5RW0OCR1AL4Timer/Counter1 Output Compare Register Low Byte Bit 4RW0OCR1AL3Timer/Counter1 Output Compare Register Low Byte Bit 3RW0OCR1AL2Timer/Counter1 Output Compare Register Low Byte Bit 2RW0OCR1AL1Timer/Counter1 Output Compare Register Low Byte Bit 1RW0OCR1AL0Timer/Counter1 Output Compare Register Low Byte Bit 0RW0ICR1HTimer/Counter1 Input Capture Register High ByteThe input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES1) of the signal at the input capture pin -ICP - is detected, the current value of the Timer/Counter1 is transferred to the Input Capture Register - ICR1. At the same time, the input capture flag - ICF1 - is set (one). Since the Input Capture Register - ICR1 - is a 16-bit register, a temporary register TEMP is used when ICR1 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR1L, the data is sent to the CPU and the data of the high byte ICR1H is placed in the TEMP register. When the CPU reads the data in the high byte ICR1H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR1L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT1, OCR1A and OCR1B. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrup$25$45io_timer.bmpNICR1H7Timer/Counter1 Input Capture Register High Byte bit 7RW0ICR1H6Timer/Counter1 Input Capture Register High Byte bit 6R0ICR1H5Timer/Counter1 Input Capture Register High Byte bit 5R0ICR1H4Timer/Counter1 Input Capture Register High Byte bit 4R0ICR1H3Timer/Counter1 Input Capture Register High Byte bit 3R0ICR1H2Timer/Counter1 Input Capture Register High Byte bit 2R0ICR1H1Timer/Counter1 Input Capture Register High Byte bit 1R0ICR1H0Timer/Counter1 Input Capture Register High Byte bit 0R0ICR1LTimer/Counter1 Input Capture Register Low ByteThe input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES1) of the signal at the input capture pin -ICP - is detected, the current value of the Timer/Counter1 is transferred to the Input Capture Register - ICR1. At the same time, the input capture flag - ICF1 - is set (one). Since the Input Capture Register - ICR1 - is a 16-bit register, a temporary register TEMP is used when ICR1 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR1L, the data is sent to the CPU and the data of the high byte ICR1H is placed in the TEMP register. When the CPU reads the data in the high byte ICR1H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR1L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT1, OCR1A and OCR1B. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within inte$24$44io_timer.bmpNICR1L7Timer/Counter1 Input Capture Register Low Byte bit 7R0ICR1L6Timer/Counter1 Input Capture Register Low Byte bit 6R0ICR1L5Timer/Counter1 Input Capture Register Low Byte bit 5R0ICR1L4Timer/Counter1 Input Capture Register Low Byte bit 4R0ICR1L3Timer/Counter1 Input Capture Register Low Byte bit 3R0ICR1L2Timer/Counter1 Input Capture Register Low Byte bit 2R0ICR1L1Timer/Counter1 Input Capture Register Low Byte bit 1R0ICR1L0Timer/Counter1 Input Capture Register Low Byte bit 0R0[SREG:SPL:MCUCR:MCUSR:OSCCAL:GPIOR2:GPIOR1:GPIOR0:PRR:CLKPR]io_cpu.bmpPRRPower Reduction Register$00$20io_cpu.bmpYPRTIM1Power Reduction Timer/Counter1R/W0PRTIM0Power Reduction Timer/Counter0R/W0PRUSIPower Reduction USIR/W0PRADCPower Reduction ADCR/W0OSCCALOscillator Calibration ValueWriting the calibration byte to this address will trim the internal oscillator to remove process variations from the oscillator frequency. This is done automatically during chip reset. When OSCCAL is zero, the lowest available frequency is chosen. Writing non-zero values to this register will increase the frequency of the internal oscillator. Writing $FF to the register gives the highest available frequency. The calibrated oscillator is used to time EEPROM and Flash access. If EEPROM or Flash is written, do not calibrate to more than 10% above the nominal frequency. Otherwise, the EEPROM or Flash write may fail. Note that the Oscillator is intended for calibration to 1.0 MHz, 2.0 MHz, 4.0 MHz, or 8.0MHz. Tuning to other values is not guaranteed, as indicated in Table 14$31$51io_cpu.bmpNCAL7Oscillator Calibration Value Bit7R/W0CAL6Oscillator Calibration Value Bit6R/W0CAL5Oscillator Calibration Value Bit5R/W0CAL4Oscillator Calibration Value Bit4R/W0CAL3Oscillator Calibration Value Bit3R/W0CAL2Oscillator Calibration Value Bit2R/W0CAL1Oscillator Calibration Value Bit1R/W0CAL0Oscillator Calibration Value Bit0R/W0CLKPRClock Prescale Register$26$46io_flag.bmpYCLKPCEClock Prescaler Change EnableThe CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is cleared by hardware four cycles after it is written or when CLKPS bits are written. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the CLKPCE bit.RW0CLKPS3Clock Prescaler Select Bit 3These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used.RW0CLKPS2Clock Prescaler Select Bit 2These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used.RW0CLKPS1Clock Prescaler Select Bit 1These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used.RW0CLKPS0Clock Prescaler Select Bit 0These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used.RW0SREGStatus Register$3F$5Fio_sreg.bmpYIGlobal Interrupt EnableThe global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable bit is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts.RW0TBit Copy StorageThe bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction.RW0HHalf Carry FlagThe half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed information.RW0SSign BitThe S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruc-tion Set Description for detailed information.RW0VTwo's Complement Overflow FlagThe two’s complement overflow flag V supports two’s complement arithmetics. See the Instruction Set Description for detailed information.RW0NNegative FlagThe negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.RW0ZZero FlagThe zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.RW0CCarry FlagThe carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software.RW0SPLStack Pointer LowThe general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the AT90S4414/8515 supports up to 64 kB external SRAM, all 16-bits are used. The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or return from interrupt $3D$5Dio_sph.bmpNSP7Stack pointer bit 7RW0SP6Stack pointer bit 6RW0SP5Stack pointer bit 5RW0SP4Stack pointer bit 4RW0SP3Stack pointer bit 3RW0SP2Stack pointer bit 2RW0SP1Stack pointer bit 1RW0SP0Stack pointer bit 0RW0MCUCRMCU Control RegisterThe MCU Control Register contains control bits for general MCU functions.$35$55io_flag.bmpYPUDRW0SESleep EnableRW0SM1Sleep Mode Select Bit 1RW0SM0Sleep Mode Select Bit 0RW0MCUSRMCU Status RegisterThe MCU Status Register provides information on which reset source caused an MCU reset.$34$54io_flag.bmpYWDRFWatchdog Reset FlagThis bit is set if a watchdog reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.RW0BORFBrown-out Reset FlagThis bit is set if a brown-out reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.R/W0EXTRFExternal Reset FlagThis bit is set if an external reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag.R/W0PORFPower-on reset flagThis bit is set if a power-on reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the reset flags to identify a reset condition, the user should read and then reset the MCUCSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags.R/W0GPIOR2General Purpose I/O Register 2$15$35io_flag.bmpNGPIOR27RW0GPIOR26RW0GPIOR25RW0GPIOR24RW0GPIOR23GPIOR22RW0GPIOR21RW0GPIOR20RW0GPIOR1General Purpose I/O Register 1$14$34io_flag.bmpNGPIOR17RW0GPIOR16RW0GPIOR15RW0GPIOR14RW0GPIOR13GPIOR12RW0GPIOR11RW0GPIOR10RW0GPIOR0General Purpose I/O Register 0$13$33io_flag.bmpNGPIOR07RW0GPIOR06RW0GPIOR05RW0GPIOR04RW0GPIOR03GPIOR02RW0GPIOR01RW0GPIOR00RW0[SPMCSR]io_cpu.bmpThe Boot Loader Support provides a real Read While Write self-programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program. The Boot Loader program can use any available data interface and associated proto-col to read code and write (program) that code into the Flash memory, or read the code from the program memory. The program code within the Boot Loader section has the capability to write into the entire Flash, including the Boot Loader Memory. The Boot Loader can thus even modify itself, and it can also erase itself from the code if the feature is not needed anymore. The size of the Boot Loader Memory is configurable with fuses and the Boot Loader has two separate sets of Boot Lock Bits which can be set independently. This gives the user a unique flexibility to select different levels of protection. Boot Loader Features: Read While Write self-programming. Flexibl Boot Memory size. High security (separate Boot Lock bits for a flexible protection). Separate fuse to select reset vector Optimized page (1) size. Code efficient algorithm Efficient read-modify-write suppoSPMCSRStore Program Memory Control RegisterThe Store Program Memory Control Register contains the control bits needed to control the Boot Loader operations.$37$57io_flag.bmpYCTPBClear temporary page bufferRW0RFLBRead fuse and lock bitsRW0PGWRTPage WriteIf this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPM instruction is exe-cuted within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.RW0PGERSPage EraseIf this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page erase. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a page erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed.RW0SPMENStore Program Memory EnableThis bit enables the SPM instruction for the next four clock cycles. If written to one together with either RWWSRE, BLB-SET, PGWRT or PGERS, the following SPM instruction will have a special meaning, see description above. If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z pointer. The LSB of the Z pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During page erase and page write, the SPMEN bit remain high until the operation is completed. Writing any other combination than “10001”, "01001", "00101", "00011" or "00001" in the lower five bits will have no effRW0[SIMULATOR:STK500_2:JTAGICEmkII:ICE50:AVRISPmkII]AVRSimCoreV2.SimCoreV2AVRSimMemory8bit.SimMemory8bitAVRSimInterrupt.SimInterrupt0x0e110AVRSimIOPort.SimIOPortYAVRSimIOPort.SimIOPortYAVRSimIOExtInterrupt.SimIOExtInterrupt0x010x3b0x400x3a0x400x160x040x350x03AVRSimIOPinChangeInterrupt.SimIOPinChangeInterrupt0x020x3B0x100x3A0x100x120x190xFFAVRSimIOPinChangeInterrupt.SimIOPinChangeInterrupt0x030x3B0x200x3A0x200x200x160x0FAVRSimAC.SimIOAC0x0CAVRSimADC.SimADC0x0DAvrSimIOTim8pwmsync2.tim8pwmsync20x0B0x090x0APORTB2PORTA7PORTB2AvrMasterTimer.MasterTimer0x050x060x070x080x190x100x190x800x190x400x190x20TIFR1/OCF1ATIFR1/OCF1B1:8:64:256:10242001002532030x53114510x4132100x400x4C0x000x000x000x414100xC10xC20x000x000x0025625644440x4C 0x0C 0x1C 0x2C 0x3C 0x64 0x74 0x66 0x68 0x78 0x68 0x68 0x7A 0x6A 0x68 0x78 0x78 0x7D 0x6D 0x0C 0x80 0x40 0x20 0x10 0x11 0x08 0x04 0x02 0x03 0x08 0x04 0x0F10006112510100254000x0B25652560x05256525625250x910BDebugWire0xFB,0xF9,0xFD,0xFF,0x7F,0xFF,0xFF,0xFF0x8B,0xB0,0xFC,0xFF,0x7D,0xFF,0xFD,0xFA0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X000X00,0X00,0X00,0X00,0X00,0X00,0X00,0X000x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x000x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x000x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x000x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x000x000X000X003240x00000x00000x00000x00000x00000x000x8000x0000,320x0020,640x000x400x000x000x200x000xBB,0xFF,0xBB,0xEE,0xBB,0xCC,0xB2,0x0D,0xBC,0x07,0xB4,0x07,0xBA,0x0D,0xBB,0xBC,0x99,0xE1,0xBB,0xAC 0xB4,0x07,0x170x3e0x3d0x270x000x000x000x000x000x1c0x050x0F0x0F0x0F0x050x050x050x050x050x050x050x050x050x0F0x0F0x050x150x140x140x000000DF0x000000000x000000000x000000000x0000007F0x000007FF0x000003FF0x000003FF0x000003FF0x000003FF0x000000DF0x0000FFFF0x0000007F0x000000000x000000000x000000000x0023FFFF0x00000FFF0x0000005F0xFE0xDF0x620xff0x510xC7ATtiny24.bin0x020x0010000002000000072 ; INTOSC = 1, INTRC=2;EXTCLK=41 ;NOTUSE = 1, EXTERNAL = 4, INTERNAL = 2 1 00x010x800x8080x800x000000400x00000000CKOUT fuse0x000000400x00000040CKOUT fuse0x000100000x00000000SELFPRGEN Fuse 0x000100000x00010000SELFPRGEN Fuse 0x000000310x00000000258CK, 14CK +4.1ms0x000000310x00000010258CK, 14CK +65ms0x000000310x000000201kCK, 14CK0x000000310x000000301kCK, 14CK +4.1ms0x000000310x000000011kCK, 14CK +65ms0x000000310x0000001116kCK, 14CK0x000000310x0000002116kCK, 14CK +4.1ms0x000000310x0000003116kCK, 14CK +65ms0x000000300x000000006 CK, 14CK0x000000300x000000106 CK, 14CK+4ms0x000000300x000000206 CK, 14CK+64 ms0x000000300x000000006 CK, 14CK0x000000300x000000106 CK, 14CK+4ms0x000000300x000000206 CK, 14CK+64 ms0x0000000e0x0000000e0x0000000f0x0000000280x0000000f0x000000000x000010000x00000000Watchdog always ON0x000010000x00001000Watchdog disabled0x000080000x00000000RSTDSBL Fuse 0x000080000x00008000RSTDSBL80x000000800x00000000CKDIV8 Fuse0x000000800x00000080CKDIV80x000007000x00000700BOD disabled0x000007000x00000600BOD enabled, 1.8 V0x000007000x00000500BOD enabled, 2.7 V0x000007000x00000400BOD enabled, 4.3 V