[ADMIN:CORE:MEMORY:PACKAGE:INTERRUPT_VECTOR:LOCKBIT:FUSE:PROGRAMMING:IO_MODULE:ICE_SETTINGS] ATtiny25 20MHZ 150 RELEASED $1E $91 $08 V2 AVRSimCoreV2.SimCoreV2 [lpm rd,z+] [] [] 32 $00 $1B $1A $1D $1C $1F $1E AVRSimMemory8bit.SimMemory8bit 2048 128 128 $60 0 NA $00 $3F NA NA $20 $5F $3F $5F 0x010x020x040x080x100x200x400x80 $3D $5D 0xDF 0x010x020x040x080x100x200x400x80 $3B $5B 0x200x40 $3A $5A 0x200x40 $39 $59 0x020x080x100x040x200x40 $38 $58 0x020x080x100x040x200x40 $37 $57 0x010x020x040x080x10 $35 $55 0x010x020x080x100x200x40 $34 $54 0x010x020x040x08 $33 $53 0x010x020x040x080x400x80 $32 $52 0x010x020x040x080x100x200x400x80 $31 $51 0x010x020x040x080x100x200x400x80 $30 $50 0x010x020x040x080x100x200x400x80 $2F $4F 0x010x020x040x080x100x200x400x80 $2E $4E 0x010x020x040x080x100x200x400x80 $2D $4D 0x010x020x040x080x100x200x400x80 $2C $4C 0x010x800x020x040x080x100x200x40 $2B $4B 0x010x020x040x080x100x200x400x80 $2A $4A 0x010x020x100x200x400x80 $29 $49 0x010x020x040x080x100x200x400x80 $28 $48 0x010x020x040x080x100x200x400x80 $27 $47 0x010x020x040x80 $26 $46 0x010x020x040x080x80 $25 $45 0x010x020x040x080x100x200x400x80 $24 $44 0x010x020x040x080x100x200x400x80 $23 $43 0x010x02 $22 $42 0x010x020x040x080x100x200x400x80 $21 $41 0x010x020x040x080x100x200x400x80 $20 $40 0x010x020x040x08 $1F $3F 0x01 $1E $3E 0x010x020x040x080x100x200x400x80 $1D $3D 0x010x020x040x080x100x200x400x80 $1C $3C 0x010x020x040x080x100x20 $18 $38 0x010x020x040x080x100x20 $17 $37 0x010x020x040x080x100x20 $16 $36 0x010x020x040x080x100x20 $15 $35 0x010x020x040x080x100x20 $14 $34 0x010x020x040x080x100x20 $13 $33 0x010x020x040x080x100x200x400x80 $12 $32 0x010x020x040x080x100x200x400x80 $11 $31 0x010x020x040x080x100x200x400x80 $10 $30 0x010x020x040x080x100x200x400x80 $0F $2F 0x010x020x040x080x100x200x400x80 $0E $2E 0x010x020x040x080x100x200x400x80 $0D $2D 0x010x020x040x080x100x200x400x80 $08 $28 0x010x020x080x100x200x400x80 $07 $27 0x010x020x040x080x100x200x400x80 $06 $26 0x010x020x040x080x100x200x400x80 $05 $25 0x010x020x040x080x100x200x400x80 $04 $24 0x010x020x040x080x100x200x400x80 $03 $23 0x400x010x020x040x200x80 $0 $3FF $0 $0 16 [PDIP:SOIC:MLF] 8 [PB5:'RESET:ADC0:PCINT5:dW] [PB3:ADC3:'OC1B:XTAL1:PCINT4] [PB4:ADC2:OC1B:XTAL2:PCINT3] [GND] [PB0:MOSI:DI:SDA:AIN0:OC0A:'OC1A:AREF:PCINT0] [PB1:MISO:DO:AIN1:OC0B:OC1A:PCINT1] [PB2:SCK:USCK:SCL:ADC1:T0:INT0:PCINT2] [VCC] 15 $000 RESET External Pin, Power-on Reset, Brown-out Reset,Watchdog Reset $001 INT0 External Interrupt 0 $002 PCINT0 Pin change Interrupt Request 0 $003 TIM1_COMPA Timer/Counter1 Compare Match 1A $004 TIM1_OVF Timer/Counter1 Overflow $005 TIM0_OVF Timer/Counter0 Overflow $006 EE_RDY EEPROM Ready $007 ANA_COMP Analog comparator $008 ADC ADC Conversion ready $009 TIM1_COMPB Timer/Counter1 Compare Match B $00A TIM0_COMPA Timer/Counter0 Compare Match A $00B TIM0_COMPB Timer/Counter0 Compare Match B $00C WDT Watchdog Time-out $00D USI_START USI START $00E USI_OVF USI Overflow [LB1 = 1 : LB2 = 1] No memory lock features enabled. [LB1 = 0 : LB2 = 1] Further programming of Flash and EEPROM is enabled. [LB1 = 0 : LB2 = 0] Same as previous, but verify is also disabled 3 2 0x03 0x03 Mode 1: No memory lock features enabled 0x03 0x02 Mode 2: Further programming disabled 0x03 0x00 Mode 3: Further programming and verification disabled LB1 Lockbit LB2 Lockbit [LOW:HIGH:EXTENDED] 54 8 0x80 0x00 Divide clock by 8 internally; [CKDIV8=0] 0x40 0x00 Clock output on PORTB4; [CKOUT=0] 0x3F 0x00 Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms; [CKSEL=0000 SUT=00] 0x3F 0x10 Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms; [CKSEL=0000 SUT=01] 0x3F 0x20 Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms; [CKSEL=0000 SUT=10] 0x3F 0x01 PLL Clock; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4 ms; [CKSEL=0001 SUT=00] 0x3F 0x11 PLL Clock; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4 ms; [CKSEL=0001 SUT=01] 0x3F 0x21 PLL Clock; Start-up time PWRDWN/RESET: 1K CK/14 CK + 64 ms; [CKSEL=0001 SUT=10] 0x3F 0x31 PLL Clock; Start-up time PWRDWN/RESET: 16K CK/14 CK + 64 ms; [CKSEL=0001 SUT=11] 0x3F 0x02 Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms; [CKSEL=0010 SUT=00] 0x3F 0x12 Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4 ms; [CKSEL=0010 SUT=01] 0x3F 0x22 Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 64 ms; [CKSEL=0010 SUT=10]; default value 0x3F 0x03 ATtiny15 Comp: Int. RC Osc. 6.4 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 64 ms; [CKSEL=0011 SUT=00] 0x3F 0x13 ATtiny15 Comp: Int. RC Osc. 6.4 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 64 ms; [CKSEL=0011 SUT=01] 0x3F 0x23 ATtiny15 Comp: Int. RC Osc. 6.4 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4 ms; [CKSEL=0011 SUT=10] 0x3F 0x33 ATtiny15 Comp: Int. RC Osc. 6.4 MHz; Start-up time PWRDWN/RESET: 1 CK/14 CK + 0 ms; [CKSEL=0011 SUT=11] 0x3F 0x04 WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms; [CKSEL=0100 SUT=00] 0x3F 0x14 WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4 ms; [CKSEL=0100 SUT=01] 0x3F 0x24 WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 64 ms; [CKSEL=0100 SUT=10] 0x3F 0x06 Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 0 ms; [CKSEL=0110 SUT=00] 0x3F 0x16 Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4 ms; [CKSEL=0110 SUT=01] 0x3F 0x26 Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 64 ms; [CKSEL=0110 SUT=10] 0x3F 0x08 Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms; [CKSEL=1000 SUT=00] 0x3F 0x18 Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms; [CKSEL=1000 SUT=01] 0x3F 0x28 Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms; [CKSEL=1000 SUT=10] 0x3F 0x38 Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms; [CKSEL=1000 SUT=11] 0x3F 0x09 Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms; [CKSEL=1001 SUT=00] 0x3F 0x19 Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms; [CKSEL=1001 SUT=01] 0x3F 0x29 Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms; [CKSEL=1001 SUT=10] 0x3F 0x39 Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms; [CKSEL=1001 SUT=11] 0x3F 0x0A Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms; [CKSEL=1010 SUT=00] 0x3F 0x1A Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms; [CKSEL=1010 SUT=01] 0x3F 0x2A Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms; [CKSEL=1010 SUT=10] 0x3F 0x3A Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms; [CKSEL=1010 SUT=11] 0x3F 0x0B Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms; [CKSEL=1011 SUT=00] 0x3F 0x1B Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms; [CKSEL=1011 SUT=01] 0x3F 0x2B Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms; [CKSEL=1011 SUT=10] 0x3F 0x3B Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms; [CKSEL=1011 SUT=11] 0x3F 0x0C Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms; [CKSEL=1100 SUT=00] 0x3F 0x1C Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms; [CKSEL=1100 SUT=01] 0x3F 0x2C Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms; [CKSEL=1100 SUT=10] 0x3F 0x3C Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms; [CKSEL=1100 SUT=11] 0x3F 0x0D Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms; [CKSEL=1101 SUT=00] 0x3F 0x1D Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms; [CKSEL=1101 SUT=01] 0x3F 0x2D Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms; [CKSEL=1101 SUT=10] 0x3F 0x3D Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms; [CKSEL=1101 SUT=11] 0x3F 0x0E Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms; [CKSEL=1110 SUT=00] 0x3F 0x1E Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms; [CKSEL=1110 SUT=01] 0x3F 0x2E Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms; [CKSEL=1110 SUT=10] 0x3F 0x3E Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms; [CKSEL=1110 SUT=11] 0x3F 0x0F Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms; [CKSEL=1111 SUT=00] 0x3F 0x1F Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms; [CKSEL=1111 SUT=01] 0x3F 0x2F Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms; [CKSEL=1111 SUT=10] 0x3F 0x3F Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms; [CKSEL=1111 SUT=11] CKSEL0 Select Clock source 0 CKSEL1 Select Clock source 1 CKSEL2 Select Clock source 0 CKSEL3 Select Clock source 1 SUT0 Select start-up time 0 SUT1 Select start-up time 1 CKOUT Clock Output Enable 1 CKDIV8 Divide clock by 8 0 9 8 0x80 0x00 Reset Disabled (Enable PB5 as i/o pin); [RSTDISBL=0] 0x40 0x00 Debug Wire enable; [DWEN=0] 0x20 0x00 Serial program downloading (SPI) enabled; [SPIEN=0] 0x10 0x00 Watch-dog Timer always on; [WDTON=0] 0x08 0x00 Preserve EEPROM memory through the Chip Erase cycle; [EESAVE=0] 0x07 0x04 Brown-out detection level at VCC=4.3 V; [BODLEVEL=100] 0x07 0x05 Brown-out detection level at VCC=2.7 V; [BODLEVEL=101] 0x07 0x06 Brown-out detection level at VCC=1.8 V; [BODLEVEL=110] 0x07 0x07 Brown-out detection disabled; [BODLEVEL=111] BODLEVEL0 Brown-out Detector trigger level 1 BODLEVEL1 Brown-out Detector trigger level 1 BODLEVEL2 Brown-out Detector trigger level 1 EESAVE EEPROM memory is preserved through the Chip Erase 1 WDTON Watchdog Timer always on 1 SPIEN Enable Serial Program and Data Downloading 0 DWEN DebugWIRE Enable 1 RSTDISBL External Reset disable 1 SELFPRGEN Self-Programming Enable 1 1 1 0x01 0x00 Self Programming enable; [SELFPRGEN=0] 0xff,0xdf, 0x01 0xff,0xdf, 0x01 1,0x20,0x20,WARNING! These fuse settings will disable the ISP interface! 1,0x40,0x00,WARNING! Enabling DEBUGWIRE will make the ISP interface inaccessible! 1,0x80,0x00,WARNING! Disabling external reset will make the ISP interface inaccessible! 1,0x20,0x20,WARNING! These fuse settings will disable the ISP interface! 1,0x40,0x00,WARNING! Enabling DEBUGWIRE will make the ISP interface inaccessible! 1,0x80,0x00,WARNING! Disabling external reset will make the ISP interface inaccessible! 0x00,8.0 MHz 0x01,6.4 MHz 32 4 [PORTB:ANALOG_COMPARATOR:AD_CONVERTER:USI:EXTERNAL_INTERRUPT:EEPROM:WATCHDOG:TIMER_COUNTER_0:TIMER_COUNTER_1:BOOT_LOAD:CPU] [PORTB:DDRB:PINB] io_port.bmp AVRSimIOPort.SimIOPort PORTB Data Register, Port B $18 $38 io_port.bmp N PORTB5 RW 0 PORTB4 RW 0 PORTB3 RW 0 PORTB2 RW 0 PORTB1 RW 0 PORTB0 RW 0 DDRB Data Direction Register, Port B $17 $37 io_flag.bmp N DDB5 RW 0 DDB4 RW 0 DDB3 RW 0 DDB2 RW 0 DDB1 RW 0 DDB0 RW 0 PINB Input Pins, Port B $16 $36 io_port.bmp N PINB5 R 0 PINB4 R 0 PINB3 R 0 PINB2 R 0 PINB1 R 0 PINB0 R 0 [ADCSRB:ACSR:DIDR0] io_analo.bmp AlgComp_01 ADCSRB ADC Control and Status Register B $03 $23 io_flag.bmp Y ACME Analog Comparator Multiplexer Enable When this bit is written logic one and the ADC is switched off (ADEN in ADCSR is zero), the ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed description of this bit, see “Analog Comparator Multiplexed Input” on page 186. RW 0 ACSR Analog Comparator Control And Status Register $08 $28 io_analo.bmp Y ACD Analog Comparator Disable When this bit is written logic one, the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed. RW 0 ACBG AINBG Analog Comparator Bandgap Select When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. See “Internal Voltage Reference” on page 42. RW 0 ACO Analog Compare Output The output of the analog comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1-2 clock cycles. R NA ACI Analog Comparator Interrupt Flag This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hard-ware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag. RW 0 ACIE Analog Comparator Interrupt Enable When the ACIE bit is written logic one and the I-bit in the Status Register is set, the analog comparator interrupt is acti-vated. When written logic zero, the interrupt is disabled. RW 0 ACIS1 Analog Comparator Interrupt Mode Select bit 1 These bits determine which comparator events that trigger the Analog Comparator interrupt. RW 0 ACIS0 Analog Comparator Interrupt Mode Select bit 0 These bits determine which comparator events that trigger the Analog Comparator interrupt. RW 0 DIDR0 $14 $34 Y AIN1D AIN1 Digital Input Disable When this bit is written logic one,the digital input buffer on the AIN1/0 pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. RW 0 AIN0D AIN0 Digital Input Disable When this bit is written logic one,the digital input buffer on the AIN1/0 pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. RW 0 [ADMUX:ADCSRA:ADCH:ADCL:ADCSRB:DIDR0] ((IF ADMUX.ADLAR = 1) LINK [ADCH(1:0):ADCL(7:0)]); (IF ADMUX.ADLAR = 0) LINK [ADCH(7:0):ADCL(7:6)]); io_analo.bmp AD Converter Feature list: 10-bit Resolution. 0.5 LSB Integral Non-Linearity. +-2 LSB Absolute Accuracy. TBD - 260 µs Conversion Time. Up to TBD kSPS at maximum resolution. 8 Multiplexed Single Ended Input Channels. 7 Differential input channels (TQFP package only). 2 Differential input channels with optional gain of 10x and 200x (TQFP package only). Optional left adjustment for ADC result readout. 0 - VCC ADC Input Voltage Range. Selectable 2.56 V ADC reference voltage. Free Running or Single Conversion Mode. Interrupt on ADC Conversion Complete. Sleep Mode N ADMUX The ADC multiplexer Selection Register These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin. $07 $27 io_analo.bmp Y REFS1 Reference Selection Bit 1 These bits select the voltage reference for the ADC. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin. RW 0 REFS0 Reference Selection Bit 0 These bits select the voltage reference for the ADC. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin. RW 0 ADLAR Left Adjust Result The ADLAR bit affects the presentation of the ADC conversion result in the ADC data register. If ADLAR is cleared, the result is right adjusted. If ADLAR is set, the result is left adjusted. Changing the ADLAR bit will affect the ADC data register immediately, regardless of any ongoing conversions. For a complete description of this bit, see “The ADC Data Register -ADCL and ADCH” on page 198. RW 0 REFS2 Reference Selection Bit 2 These bits select the voltage reference for the ADC. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin. RW 0 MUX3 Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). RW 0 MUX2 Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). RW 0 MUX1 Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). RW 0 MUX0 Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). RW 0 ADCSRA The ADC Control and Status register $06 $26 io_flag.bmp Y ADEN ADC Enable Writing a logical ‘1’ to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion. RW 0 ADSC ADC Start Conversion In Single Conversion Mode, a logical ‘1’ must be written to this bit to start each conversion. In Free Running Mode, a logical ‘1’ must be written to this bit to start the first conversion. The first time ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, an extended conversion will result. This extended conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. When a dummy conversion precedes a real conversion, ADSC will stay high until the real conversion completes. Writing a 0 to this bit has no effect RW 0 ADATE ADC Auto Trigger Enable When this bit is written to one,Auto Triggering of the ADC is enabled.The ADC will start a conversion on a positive edge of the selected trigger signal.The trigger source is selected by setting the ADC Trigger Select bits,ADTS in ADCSRB. RW 0 ADIF ADC Interrupt Flag This bit is set (one) when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set (one). ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a read-modify-write on ADCSR, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used. RW 0 ADIE ADC Interrupt Enable When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Complete Interrupt is activated. RW 0 ADPS2 ADC Prescaler Select Bits These bits determine the division factor between the XTAL frequency and the input clock to the ADC. RW 0 ADPS1 ADC Prescaler Select Bits These bits determine the division factor between the XTAL frequency and the input clock to the ADC. RW 0 ADPS0 ADC Prescaler Select Bits These bits determine the division factor between the XTAL frequency and the input clock to the ADC. RW 0 ADCH ADC Data Register High Byte When an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. The selected channel is differential if MUX4..0 are between ‘01000’ and ‘11101’, otherwise the selected channel is single ended. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8 bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUX4..0 bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right $05 $25 io_analo.bmp N ADCH7 ADC Data Register High Byte Bit 7 RW 0 ADCH6 ADC Data Register High Byte Bit 6 RW 0 ADCH5 ADC Data Register High Byte Bit 5 RW 0 ADCH4 ADC Data Register High Byte Bit 4 RW 0 ADCH3 ADC Data Register High Byte Bit 3 RW 0 ADCH2 ADC Data Register High Byte Bit 2 RW 0 ADCH1 ADC Data Register High Byte Bit 1 RW 0 ADCH0 ADC Data Register High Byte Bit 0 RW 0 ADCL ADC Data Register Low Byte When an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. The selected channel is differential if MUX4..0 are between ‘01000’ and ‘11101’, otherwise the selected channel is single ended. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8 bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUX4..0 bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right $04 $24 io_analo.bmp N ADCL7 ADC Data Register Low Byte Bit 7 RW 0 ADCL6 ADC Data Register Low Byte Bit 6 RW 0 ADCL5 ADC Data Register Low Byte Bit 5 RW 0 ADCL4 ADC Data Register Low Byte Bit 4 RW 0 ADCL3 ADC Data Register Low Byte Bit 3 RW 0 ADCL2 ADC Data Register Low Byte Bit 2 RW 0 ADCL1 ADC Data Register Low Byte Bit 1 RW 0 ADCL0 ADC Data Register Low Byte Bit 0 RW 0 ADCSRB ADC Control and Status Register B $03 $23 io_analo.bmp Y BIN Bipolar Input Mode The gain stage is working in the unipolar mode as default, but the bipolar mode can be selected by writing the BIN bit in the ADCSRB register. R 0 IPR Input Polarity Mode R 0 ADTS2 ADC Auto Trigger Source 2 If ADATE in ADCSRA is written to one,the value of these bits selects which source will trigger an ADC conversion.If ADATE is cleared,the ADTS2:0 settings will have no effect.A conversion will be triggered by the rising edge of the selected interrupt flag.Note that switching from a trigger source that is cleared to a trigger source that is set,will generate a positive edge on the trigger signal.If ADEN in ADCSRA is set,this will start a conversion.Switching to Free Running Mode (ADTS [2:0 ]=0)will not cause a trigger event,even if the ADC Interrupt Flag is set . RW 0 ADTS1 ADC Auto Trigger Source 1 If ADATE in ADCSRA is written to one,the value of these bits selects which source will trigger an ADC conversion.If ADATE is cleared,the ADTS2:0 settings will have no effect.A conversion will be triggered by the rising edge of the selected interrupt flag.Note that switching from a trigger source that is cleared to a trigger source that is set,will generate a positive edge on the trigger signal.If ADEN in ADCSRA is set,this will start a conversion.Switching to Free Running Mode (ADTS [2:0 ]=0)will not cause a trigger event,even if the ADC Interrupt Flag is set . RW 0 ADTS0 ADC Auto Trigger Source 0 If ADATE in ADCSRA is written to one,the value of these bits selects which source will trigger an ADC conversion.If ADATE is cleared,the ADTS2:0 settings will have no effect.A conversion will be triggered by the rising edge of the selected interrupt flag.Note that switching from a trigger source that is cleared to a trigger source that is set,will generate a positive edge on the trigger signal.If ADEN in ADCSRA is set,this will start a conversion.Switching to Free Running Mode (ADTS [2:0 ]=0)will not cause a trigger event,even if the ADC Interrupt Flag is set . RW 0 DIDR0 Digital Input Disable Register 0 $14 $34 io_analo.bmp Y ADC0D ADC0 Digital input Disable When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. ADC2D ADC2 Digital input Disable When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. ADC3D ADC3 Digital input Disable When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. ADC1D ADC1 Digital input Disable When this bit is written logic one,the digital input buffer on the corresponding ADC pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. [USIBR:USIDR:USISR:USICR] io_com.bmp Universal Serial Interface USIBR USI Buffer Register $10 $30 io_com.bmp N USIBR7 USI Buffer Register bit 7 R 0 USIBR6 USI Buffer Register bit 6 R 0 USIBR5 USI Buffer Register bit 5 R 0 USIBR4 USI Buffer Register bit 4 R 0 USIBR3 USI Buffer Register bit 3 R 0 USIBR2 USI Buffer Register bit 2 R 0 USIBR1 USI Buffer Register bit 1 R 0 USIBR0 USI Buffer Register bit 0 R 0 USIDR USI Data Register $0F $2F io_com.bmp N USIDR7 USI Data Register bit 7 RW 0 USIDR6 USI Data Register bit 6 RW 0 USIDR5 USI Data Register bit 5 RW 0 USIDR4 USI Data Register bit 4 RW 0 USIDR3 USI Data Register bit 3 RW 0 USIDR2 USI Data Register bit 2 RW 0 USIDR1 USI Data Register bit 1 RW 0 USIDR0 USI Data Register bit 0 RW 0 USISR USI Status Register $0E $2E io_flag.bmp Y USISIF Start Condition Interrupt Flag RW 0 USIOIF Counter Overflow Interrupt Flag RW 0 USIPF Stop Condition Flag RW 1 USIDC Data Output Collision RW 0 USICNT3 USI Counter Value Bit 3 RW 0 USICNT2 USI Counter Value Bit 2 RW 0 USICNT1 USI Counter Value Bit 1 RW 0 USICNT0 USI Counter Value Bit 0 RW 0 USICR USI Control Register $0D $2D io_flag.bmp Y USISIE Start Condition Interrupt Enable RW 0 USIOIE Counter Overflow Interrupt Enable RW 0 USIWM1 USI Wire Mode Bit 1 RW 1 USIWM0 USI Wire Mode Bit 0 RW 0 USICS1 USI Clock Source Select Bit 1 RW 0 USICS0 USI Clock Source Select Bit 0 RW 0 USICLK Clock Strobe R 0 USITC Toggle Clock Port Pin W 0 [MCUCR:GIMSK:GIFR:PCMSK] io_ext.bmp MCUCR MCU Control Register $35 $55 io_cpu.bmp Y ISC01 Interrupt Sense Control 0 Bit 1 RW 0 ISC00 Interrupt Sense Control 0 Bit 0 RW 0 GIMSK GICR General Interrupt Mask Register $3B $5B io_flag.bmp Y INT0 External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from program memory address $001. See also “External Interrupts.” • Bits 5..0 - Res: Reserved bits RW 0 PCIE Pin Change Interrupt Enable RW 0 GIFR General Interrupt Flag register $3A $5A io_flag.bmp Y INTF0 External Interrupt Flag 0 When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the interrupt vector at address $001. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. RW 0 PCIF Pin Change Interrupt Flag RW 0 PCMSK Pin Change Enable Mask $15 $35 io_flag.bmp N PCINT5 Pin Change Enable Mask Bit 5 RW 0 PCINT4 Pin Change Enable Mask Bit 4 RW 0 PCINT3 Pin Change Enable Mask Bit 3 RW 0 PCINT2 Pin Change Enable Mask Bit 2 RW 0 PCINT1 Pin Change Enable Mask Bit 1 RW 0 PCINT0 Pin Change Enable Mask Bit 0 RW 0 [EEARL:EEARH:EEDR:EECR] io_cpu.bmp EEPROM Read/Write Access. The EEPROM access registers are accessible in the I/O space. The write access time for the EEPROM is given in Table 1. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page 19. for details on how to avoid problems in these situations.In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When theEEPROM is written, the CPU is halted for two clock cycles before the next instruction is execut EEARH EEPROM Address Register High Byte $1F $3F io_cpu.bmp N EEAR8 EEPROM Read/Write Access Bit 0 RW 0 EEARL EEPROM Address Register Low Byte $1E $3E io_cpu.bmp N EEAR7 EEPROM Read/Write Access Bit 7 RW 0 EEAR6 EEPROM Read/Write Access Bit 6 RW 0 EEAR5 EEPROM Read/Write Access Bit 5 RW 0 EEAR4 EEPROM Read/Write Access Bit 4 RW 0 EEAR3 EEPROM Read/Write Access Bit 3 RW 0 EEAR2 EEPROM Read/Write Access Bit 2 RW 0 EEAR1 EEPROM Read/Write Access Bit 1 RW 0 EEAR0 EEPROM Read/Write Access Bit 0 RW 0 EEDR EEPROM Data Register For the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR. $1D $3D io_cpu.bmp N EEDR7 EEPROM Data Register bit 7 RW 0 EEDR6 EEPROM Data Register bit 6 RW 0 EEDR5 EEPROM Data Register bit 5 RW 0 EEDR4 EEPROM Data Register bit 4 RW 0 EEDR3 EEPROM Data Register bit 3 RW 0 EEDR2 EEPROM Data Register bit 2 RW 0 EEDR1 EEPROM Data Register bit 1 RW 0 EEDR0 EEPROM Data Register bit 0 RW 0 EECR EEPROM Control Register $1C $3C io_flag.bmp Y EEPM1 EEPROM Programming Mode Bit 1 The EEPROM Programming mode bit setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in Table 2. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming. RW X EEPM0 EEPROM Programming Mode Bit 0 The EEPROM Programming mode bit setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in Table 2. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming. RW X EERIE EEPROM Ready Interrupt Enable EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared. RW 0 EEMPE EEPROM Master Write Enable The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is written to one, writing EEWE to one within 4 clock cycles will write data to the EEPROM at the selected address. If EEMWE is zero, writing EEWE to one will have no effect. When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure. RW 0 EEPE EEPROM Write Enable The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential): 1. Wait until EEWE becomes zero. 2. Wait until SPMEN in SPMCR becomes zero. 3. Write new EEPROM address to EEAR (optional). 4. Write new EEPROM data to EEDR (optional). 5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR. 6. Within four clock cycles after setting EEMWE, write a logical one to EEWE. The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a boot loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See “Boot Loader Support - Read While Write self-programming” on page 228 for details about boot programming. Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR regis-ter will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the 4 last steps to avoid these problems. When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruc-tion is executed RW X EERE EEPROM Read Enable The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR register. The calibrated oscillator is used to time the EEPROM accesses. Table 1 lists the typical programming time for EEPROM access from the CPU RW 0 [WDTCR] io_watch.bmp WDTCR WDTCSR Watchdog Timer Control Register $21 $41 io_flag.bmp Y WDIF Watchdog Timeout Interrupt Flag RW 0 WDIE Watchdog Timeout Interrupt Enable RW 0 WDP3 Watchdog Timer Prescaler Bit 3 RW 0 WDCE WDTOE Watchdog Change Enable RW 0 WDE Watch Dog Enable When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog RW 0 WDP2 Watch Dog Timer Prescaler bit 2 RW 0 WDP1 Watch Dog Timer Prescaler bit 1 RW 0 WDP0 Watch Dog Timer Prescaler bit 0 RW 0 [TIMSK:TIFR:TCCR0A:TCCR0B:TCNT0:OCR0A:OCR0B:GTCCR] io_timer.bmp TIMSK Timer/Counter Interrupt Mask Register $39 $59 io_flag.bmp Y OCIE0A Timer/Counter0 Output Compare Match A Interrupt Enable RW 0 OCIE0B Timer/Counter0 Output Compare Match B Interrupt Enable RW 0 TOIE0 Timer/Counter0 Overflow Interrupt Enable RW 0 TIFR Timer/Counter0 Interrupt Flag register $38 $58 io_flag.bmp Y OCF0A Timer/Counter0 Output Compare Flag 0A RW 0 OCF0B Timer/Counter0 Output Compare Flag 0B RW 0 TOV0 Timer/Counter0 Overflow Flag RW 0 TCCR0A Timer/Counter Control Register A $2A $4A io_flag.bmp Y COM0A1 Compare Output Mode, Phase Correct PWM Mode RW 0 COM0A0 Compare Output Mode, Phase Correct PWM Mode RW 0 COM0B1 Compare Output Mode, Fast PWm W 0 COM0B0 Compare Output Mode, Fast PWm RW 0 WGM01 Waveform Generation Mode RW 0 WGM00 Waveform Generation Mode RW 0 TCCR0B Timer/Counter Control Register B $33 $53 io_flag.bmp Y FOC0A Force Output Compare A W 0 FOC0B Force Output Compare B W 0 WGM02 RW 0 CS02 Clock Select RW 0 CS01 Clock Select RW 0 CS00 Clock Select RW 0 TCNT0 Timer/Counter0 The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT0 register blocks (removes) the compare match on the following timer clock. Modifying the counter (TCNT0) while the counter is running, introduces a risk of missing a compare match between TCNT0 the OCR0 register. $32 $52 io_timer.bmp N TCNT0_7 RW 0 TCNT0_6 RW 0 TCNT0_5 RW 0 TCNT0_4 RW 0 TCNT0_3 RW 0 TCNT0_2 RW 0 TCNT0_1 RW 0 TCNT0_0 RW 0 OCR0A Timer/Counter0 Output Compare Register The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC0 pin. $29 $49 io_timer.bmp N OCR0_7 RW 0 OCR0_6 RW 0 OCR0_5 RW 0 OCR0_4 RW 0 OCR0_3 RW 0 OCR0_2 RW 0 OCR0_1 RW 0 OCR0_0 RW 0 OCR0B Timer/Counter0 Output Compare Register The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC0 pin. $28 $48 io_timer.bmp N OCR0_7 RW 0 OCR0_6 RW 0 OCR0_5 RW 0 OCR0_4 RW 0 OCR0_3 RW 0 OCR0_2 RW 0 OCR0_1 RW 0 OCR0_0 RW 0 GTCCR General Timer/Counter Control Register $2C $4C io_flag.bmp Y TSM Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSR2 and PSR10 bits is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSR2 and PSR10 bits are cleared by hardware, and the Timer/Counters start counting simultaneousl RW 0 PSR0 Prescaler Reset Timer/Counter1 and Timer/Counter0 When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. RW 0 [TCCR1:TCNT1:OCR1A:OCR1B:OCR1C:TIMSK:TIFR:GTCCR:DTPS:DTVALA:DTVALB] io_timer.bmp t8pwm1_02 TCCR1 Timer/Counter Control Register $30 $50 io_flag.bmp Y CTC1 Clear Timer/Counter on Compare Match When the CTC1 control bit is set (one), Timer/Counter1 is reset to $00 in the CPU clock cycle after a compare match with OCR1A register value. If the control bit is cleared, Timer/Counter1 continues counting and is unaffected by a compare match. RW 0 PWM1A Pulse Width Modulator Enable When set (one), this bit enables PWM mode for Timer/Counter1. RW 0 COM1A1 Compare Output Mode, Bit 0 The COM1A1 and COM1A0 control bits determine any output pin action following a compare match A in Timer/Counter1. Output pin actions affect pin PB1(OC1A). Since this is an alternative function to an I/O port, the corresponding direction control bit must be set (one) to control an output pin. RW 0 COM1A0 Compare Output Mode, Bit 1 The COM1A1 and COM1A0 control bits determine any output pin action following a compare match A in Timer/Counter1. Output pin actions affect pin PB1(OC1A). Since this is an alternative function to an I/O port, the corresponding direction control bit must be set (one) to control an output pin. RW 0 CS13 Clock Select Bits The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1. RW 0 CS12 Clock Select Bits The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1. RW 0 CS11 Clock Select Bits The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1. RW 0 CS10 Clock Select Bits The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1. RW 0 TCNT1 Timer/Counter Register The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT1 register blocks (removes) the compare match on the following timer clock. Modifying the counter (TCNT1) while the counter is running, introduces a risk of missing a compare match between TCNT1 the OCR2 register. $2F $4F io_timer.bmp N TCNT1_7 Timer/Counter Register Bit 7 RW 0 TCNT1_6 Timer/Counter Register Bit 6 RW 0 TCNT1_5 Timer/Counter Register Bit 5 RW 0 TCNT1_4 Timer/Counter Register Bit 4 RW 0 TCNT1_3 Timer/Counter Register Bit 3 RW 0 TCNT1_2 Timer/Counter Register Bit 2 RW 0 TCNT1_1 Timer/Counter Register Bit 1 RW 0 TCNT1_0 Timer/Counter Register Bit 0 RW 0 OCR1A Output Compare Register The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT1). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC2 pin. $2E $4E io_timer.bmp N OCR1A7 Output Compare Register A Bit 7 RW 0 OCR1A6 Output Compare Register A Bit 6 RW 0 OCR1A5 Output Compare Register A Bit 5 RW 0 OCR1A4 Output Compare Register A Bit 4 RW 0 OCR1A3 Output Compare Register A Bit 3 RW 0 OCR1A2 Output Compare Register A Bit 2 RW 0 OCR1A1 Output Compare Register A Bit 1 RW 0 OCR1A0 Output Compare Register A Bit 0 RW 0 OCR1B Output Compare Register The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT1). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC2 pin. $2B $4B io_timer.bmp N OCR1B7 Output Compare Register B Bit 7 RW 0 OCR1B6 Output Compare Register B Bit 6 RW 0 OCR1B5 Output Compare Register B Bit 5 RW 0 OCR1B4 Output Compare Register B Bit 4 RW 0 OCR1B3 Output Compare Register B Bit 3 RW 0 OCR1B2 Output Compare Register B Bit 2 RW 0 OCR1B1 Output Compare Register B Bit 1 RW 0 OCR1B0 Output Compare Register B Bit 0 RW 0 OCR1C Output compare register $2D $4D io_timer.bmp N OCR1C7 OCR1C6 OCR1C5 OCR1C4 OCR1C3 OCR1C2 OCR1C1 OCR1C0 TIMSK Timer/Counter Interrupt Mask Register $39 $59 io_flag.bmp Y OCIE1A OCIE1A: Timer/Counter1 Output Compare Interrupt Enable When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Compare Match, interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a compare match A in Timer/Counter1 occurs, i.e., when the OCF1A bit is set (one) in the Timer/Counter Interrupt Flag Register (TIFR). RW 0 OCIE1B OCIE1A: Timer/Counter1 Output Compare B Interrupt Enable RW 0 TOIE1 Timer/Counter1 Overflow Interrupt Enable When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $004) is executed if an overflow in Timer/Counter1 occurs (i.e., when the TOV1 bit is set in the Timer/Counter Interrupt Flag Register [TIFR]). RW 0 TIFR Timer/Counter Interrupt Flag Register $38 $58 io_flag.bmp Y OCF1A Timer/Counter1 Output Compare Flag 1A The OCF1A bit is set (one) when compare match occurs between Timer/Counter1 and the data value in OCR1A (Output Compare Register 1A). OCF1A is cleared by hard-ware when executing the corresponding interrupt handling vector. Alternatively, OCF1A is cleared by writing a logical “1” to the flag. When the I-bit in SREG, OCIE1A, and OCF1A are set (one), the Timer/Counter1 compare match A interrupt is executed. RW 0 OCF1B Timer/Counter1 Output Compare Flag 1B RW 0 TOV1 Timer/Counter1 Overflow Flag The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logical “1” to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overf low Interrupt Enable) and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. RW 0 GTCCR Timer counter control register $2C $4C io_flag.bmp PWM1B Pulse Width Modulator B Enable RW 0 COM1B1 Comparator B Output Mode RW 0 COM1B0 Comparator B Output Mode RW 0 FOC1B Force Output Compare Match 1B RW 0 FOC1A Force Output Compare 1A Writing a logical “1” to this bit forces a change in the compare match output pin PB1 (OC1A) according to the values already set in COM1A1 and COM1A0. The Force Output Compare bit can be used to change the output pin without waiting for a compare match in timer. The automatic action programmed in COM1A1 and COM1A0 happens as if a Compare Match had occurred, but no interrupt is generated and the Timer/Counter1 will not be cleared even if CTC1 is set. The FOC1A bit will always be read as zero. The setting of the FOC1A bit has no effect i RW 0 PSR1 Prescaler Reset Timer/Counter1 When this bit is set (one) the Timer/Counter1 prescaler will be reset. The bit will be cleared by hardware after the operation is performed. Writing a “0” to this bit will have no effect. This bit will always be read as zero. RW 0 DTPS Dead time prescaler register $23 $43 io_flag.bmp DTPS1 RW 0 DTPS0 RW 0 DTVALA Dead time value register $25 $45 io_flag.bmp DTVH3 RW 0 DTVH2 RW 0 DTVH1 RW 0 DTVH0 RW 0 DTVL3 RW 0 DTVL2 RW 0 DTVL1 RW 0 DTVL0 RW 0 DTVALB Dead time value B $24 $44 io_flag.bmp DTVH3 RW 0 DTVH2 RW 0 DTVH1 RW 0 DTVH0 RW 0 DTVL3 RW 0 DTVL2 RW 0 DTVL1 RW 0 DTVL0 RW 0 [SPMCSR] io_cpu.bmp The Boot Loader Support provides a real Read While Write self-programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program. The Boot Loader program can use any available data interface and associated proto-col to read code and write (program) that code into the Flash memory, or read the code from the program memory. The program code within the Boot Loader section has the capability to write into the entire Flash, including the Boot Loader Memory. The Boot Loader can thus even modify itself, and it can also erase itself from the code if the feature is not needed anymore. The size of the Boot Loader Memory is configurable with fuses and the Boot Loader has two separate sets of Boot Lock Bits which can be set independently. This gives the user a unique flexibility to select different levels of protection. Boot Loader Features: Read While Write self-programming. Flexibl Boot Memory size. High security (separate Boot Lock bits for a flexible protection). Separate fuse to select reset vector Optimized page (1) size. Code efficient algorithm Efficient read-modify-write suppo SPMCSR Store Program Memory Control Register The Store Program Memory Control Register contains the control bits needed to control the Boot Loader operations. $37 $57 io_flag.bmp Y CTPB Clear temporary page buffer RW 0 RFLB Read fuse and lock bits RW 0 PGWRT Page Write If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPM instruction is exe-cuted within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed. RW 0 PGERS Page Erase If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page erase. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a page erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed. RW 0 SPMEN Store Program Memory Enable This bit enables the SPM instruction for the next four clock cycles. If written to one together with either RWWSRE, BLB-SET, PGWRT or PGERS, the following SPM instruction will have a special meaning, see description above. If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z pointer. The LSB of the Z pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During page erase and page write, the SPMEN bit remain high until the operation is completed. Writing any other combination than “10001”, "01001", "00101", "00011" or "00001" in the lower five bits will have no eff RW 0 [SREG:SPL:MCUCR:MCUSR:PRR:OSCCAL:PLLCSR:CLKPR:DWDR:GPIOR2:GPIOR1:GPIOR0] io_cpu.bmp SREG Status Register $3F $5F io_sreg.bmp Y I Global Interrupt Enable The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable bit is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. RW 0 T Bit Copy Storage The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction. RW 0 H Half Carry Flag The half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed information. RW 0 S Sign Bit The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruc-tion Set Description for detailed information. RW 0 V Two's Complement Overflow Flag The two’s complement overflow flag V supports two’s complement arithmetics. See the Instruction Set Description for detailed information. RW 0 N Negative Flag The negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information. RW 0 Z Zero Flag The zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information. RW 0 C Carry Flag The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software. RW 0 PRR Power Reduction Register $20 $40 io_sreg.bmp Y PRTIM1 Power Reduction Timer/Counter1 Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1 is enabled, operation will continue like before the shutdown. RW 0 PRTIM0 Power Reduction Timer/Counter0 Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, operation will continue like before the shutdown. RW 0 PRUSI Power Reduction USI Writing a logic one to this bit shuts down the USI by stopping the clock to the module. When waking up the USI again, the USI should be re initialized to ensure proper operation. RW 0 PRADC Power Reduction ADC Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. The analog comparator cannot use the ADC input MUX when the ADC is shut down. RW 0 SPL Stack Pointer Low Byte $3D $5D io_sreg.bmp N SP7 Stack Pointer Bit 7 RW 0 SP6 Stack Pointer Bit 6 RW 0 SP5 Stack Pointer Bit 5 RW 0 SP4 Stack Pointer Bit 4 RW 0 SP3 Stack Pointer Bit 3 RW 0 SP2 Stack Pointer Bit 2 RW 0 SP1 Stack Pointer Bit 1 RW 0 SP0 Stack Pointer Bit 0 RW 0 MCUCR MCU Control Register The MCU Control Register contains control bits for general MCU functions. $35 $55 io_cpu.bmp Y PUD Pull-up Disable RW 0 SE Sleep Enable The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmers purpose, it is recommended to set the Sleep Enable SE bit just before the execution of the SLEEP instruction. R 0 SM1 Sleep Mode Select Bit 1 RW 0 SM0 Sleep Mode Select Bit 0 RW 0 ISC01 Interrupt Sense Control 0 bit 1 R 0 ISC00 Interrupt Sense Control 0 bit 0 R 0 MCUSR MCU Status register The MCU Status Registerprovides information on which reset source caused a MCU reset. $34 $54 io_cpu.bmp Y WDRF Watchdog Reset Flag RW 0 BORF Brown-out Reset Flag RW 0 EXTRF External Reset Flag After a power-on reset, this bit is undefined (X). It will be set by an external reset. A watchdog reset will leave this bit unchanged. RW 0 PORF Power-On Reset Flag This bit is set by a power-on reset. A watchdog reset or an external reset will leave this bit unchanged RW 0 OSCCAL Oscillator Calibration Register $31 $51 io_sreg.bmp N CAL7 Oscillatro Calibration Value Bit 7 RW 0 CAL6 Oscillatro Calibration Value Bit 6 RW 0 CAL5 Oscillatro Calibration Value Bit 5 RW 0 CAL4 Oscillatro Calibration Value Bit 4 RW 0 CAL3 Oscillatro Calibration Value Bit 3 RW 0 CAL2 Oscillatro Calibration Value Bit 2 RW 0 CAL1 Oscillatro Calibration Value Bit 1 RW 0 CAL0 Oscillatro Calibration Value Bit 0 RW 0 CLKPR Clock Prescale Register The system clock can be divided by setting the Clock Prescale Register – CLKPR. This feature can be used to decrease power consumption when the requirement for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals. $26 $46 io_sreg.bmp Y CLKPCE Clock Prescaler Change Enable The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only update when the other bits in CLKPR are simultaniosly written to zero. CLKPCE is cleared by hardware four cycles after it is written or when CLKPS is written. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the CLKPCE bit. RW 0 CLKPS3 Clock Prescaler Select Bit 3 RW 0 CLKPS2 Clock Prescaler Select Bit 2 These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. The division factors are given a table in the device user guide.. To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits: 1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero. 2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE. Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted RW 0 CLKPS1 Clock Prescaler Select Bit 1 These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. The division factors are given a table in the device user guide.. To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits: 1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero. 2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE. Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted RW 0 CLKPS0 Clock Prescaler Select Bit 0 These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. The division factors are given a table in the device user guide.. To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits: 1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero. 2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE. Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted RW 0 PLLCSR PLL Control and status register $27 $47 io_sreg.bmp Y LSM Low speed mode R 0 PCKE PCK Enable RW 0 PLLE PLL Enable RW 0 PLOCK PLL Lock detector R 0 DWDR debugWire data register $22 $42 io_cpu.bmp N DWDR7 RW 0 DWDR6 RW 0 DWDR5 RW 0 DWDR4 RW 0 DWDR3 RW 0 DWDR2 RW 0 DWDR1 RW 0 DWDR0 RW 0 GPIOR2 General Purpose IO register 2 $13 $33 io_sreg.bmp N GPIOR27 RW 0 GPIOR26 RW 0 GPIOR25 RW 0 GPIOR24 RW 0 GPIOR23 RW 0 GPIOR22 RW 0 GPIOR21 RW 0 GPIOR20 GPIOR27 0 GPIOR1 General Purpose register 1 $12 $32 io_sreg.bmp N GPIOR17 RW 0 GPIOR16 RW 0 GPIOR15 RW 0 GPIOR14 RW 0 GPIOR13 RW 0 GPIOR12 RW 0 GPIOR11 RW 0 GPIOR10 RW 0 GPIOR0 General purpose register 0 $11 $31 io_sreg.bmp N GPIOR07 RW 0 GPIOR06 RW 0 GPIOR05 RW 0 GPIOR04 RW 9 GPIOR03 RW 0 GPIOR02 RW 0 GPIOR01 RW 0 GPIOR00 RW 0 [SIMULATOR:ICE50:STK500_2:AVRISPmkII:JTAGICEmkII:AVRDragon] AVRSimCoreV2.SimCoreV2 AVRSimMemory8bit.SimMemory8bit AVRSimInterrupt.SimInterrupt 0x06 0 6 AVRSimIOPort.SimIOPort Y AVRSimIOExtInterrupt.SimIOExtInterrupt 0x01 0x3b 0x40 0x3a 0x40 0x16 0x04 0x35 0x03 AVRSimIOPinChangeInterrupt.SimIOPinChangeInterrupt 0x02 0x3B 0x20 0x3A 0x20 0x15 0x16 0x3F AVRSimAC.SimIOAC 0x07 AVRSimADC.SimADC 0x08 AvrSimIOTim8pwmsync2.tim8pwmsync2 0x05 0x0a 0x0b PORTB 0 PORTB 1 PINB 2 0x05 0x0F 0x0F 0x0F 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x0F 0x0F 0x05 0x15 0x14 0x14 0x000000DF 0x00000000 0x00000000 0x00000000 0x0000007F 0x000007FF 0x000003FF 0x000003FF 0x000003FF 0x000003FF 0x000000DF 0x0000FFFF 0x0000007F 0x00000000 0x00000000 0x00000000 0x0023FFFF 0x00000FFF 0x0000005F 0xFE 0xDF 0x62 0xff 0x51 0xC7 ATtiny25.bin 0x02 0x00 1000000 20000000 7 2 ; INTOSC = 1, INTRC=2;EXTCLK=4 1 ;NOTUSE = 1, EXTERNAL = 4, INTERNAL = 2 1 0 0x80 0x80 8 0x80E8 0x00000040 0x00000000 CKOUT fuse 0x00000040 0x00000040 CKOUT fuse 0x00010000 0x00000000 SELFPRGEN Fuse 0x00010000 0x00010000 SELFPRGEN Fuse 0x00000031 0x00000000 258CK, 14CK +4.1ms 0x00000031 0x00000010 258CK, 14CK +65ms 0x00000031 0x00000020 1kCK, 14CK 0x00000031 0x00000030 1kCK, 14CK +4.1ms 0x00000031 0x00000001 1kCK, 14CK +65ms 0x00000031 0x00000011 16kCK, 14CK 0x00000031 0x00000021 16kCK, 14CK +4.1ms 0x00000031 0x00000031 16kCK, 14CK +65ms 0x00000030 0x00000000 6 CK, 14CK 0x00000030 0x00000010 6 CK, 14CK+4ms 0x00000030 0x00000020 6 CK, 14CK+64 ms 0x00000030 0x00000000 1K CK, 14CK + 8ms 0x00000030 0x00000010 16K CK, 14CK + 8ms 0x00000030 0x00000020 1K CK, 14CK + 128ms 0x00000030 0x00000030 16K CK, 14CK + 128ms 0x00000030 0x00000000 6 CK, 14CK 0x00000030 0x00000010 6 CK, 14CK+4ms 0x00000030 0x00000020 6 CK, 14CK+64 ms 0x0000000e 0x0000000e 0x0000000f 0x00000001 0x0000000f 0x00000002 8 0x0000000f 0x00000003 6.4 0x0000000f 0x00000000 0x00001000 0x00000000 Watchdog always ON 0x00001000 0x00001000 Watchdog disabled 0x00008000 0x00000000 RSTDSBL Fuse 0x00008000 0x00008000 RSTDSBL 8 0x00000080 0x00000000 CKDIV8 Fuse 0x00000080 0x00000080 CKDIV8 0x00000700 0x00000700 BOD disabled 0x00000700 0x00000600 BOD enabled, 1.8 V 0x00000700 0x00000500 BOD enabled, 2.7 V 0x00000700 0x00000400 BOD enabled, 4.3 V 2001002532030x53114510x4132100x400x4C0x000x000x000x41450xC10xC20x000x000x0025625644440x4C 0x0C 0x1C 0x2C 0x3C 0x64 0x74 0x66 0x68 0x78 0x68 0x68 0x7A 0x6A 0x68 0x78 0x78 0x7D 0x6D 0x0C 0x80 0x40 0x20 0x10 0x11 0x08 0x04 0x02 0x03 0x08 0x04 0x0010006112510100254000x0B25652560x0525652562525 0x9108 DebugWire 0xF8,0xE1,0xFF,0xF1,0xFB,0xFF,0xBF,0xAF 0xC8,0xE1,0xFF,0x71,0xBB,0x7F,0xAD,0xAB 0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00 0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 0x00 0X00 0X00 32 4 0x0000 0x0000 0x0000 0x0000 0x0000 0x00 0x800 0x0000,32 0x0020,64 0x00 0x40 0x00 0x00 0x20 0x00 0xBB, 0xFF, 0xBB, 0xEE, 0xBB, 0xCC, 0xB2, 0x0D, 0xBC, 0x02, 0xB4, 0x02, 0xBA, 0x0D, 0xBB, 0xBC, 0x99, 0xE1, 0xBB, 0xAC 0xB4, 0x02, 0x12 0x3e 0x3d 0x22 0x00 0x00 0x00 0x00 0x00 0x1c