[ADMIN:CORE:INTERRUPT_VECTOR:MEMORY:PACKAGE:FUSE:LOCKBIT:PROGRAMMING:IO_MODULE:ICE_SETTINGS] ATtiny26 16MHZ 235 RELEASED $1E $91 $09 V1 AVRSimCoreV1.SimCoreV1 [lpm rd,z] [] [0x0023:0x0034:0x0054] 32 $00 $1B $1A $1D $1C $1F $1E 12 $000 RESET External Reset, Power-on Reset and Watchdog Reset $001 INT0 External Interrupt 0 $002 I/O_PINS External Interrupt Request 0 $003 TIMER1,CMPA Timer/Counter1 Compare Match 1A $004 TIMER1,CMPB Timer/Counter1 Compare Match 1B $005 TIMER1,OVF1 Timer/Counter1 Overflow $006 TIMER0,OVF0 Timer/Counter0 Overflow $007 USI_STRT USI Start $008 USI_OVF USI Overflow $009 EE_RDY EEPROM Ready $00A ANA_COMP Analog Comparator $00B ADC ADC Conversion Complete AVRSimMemory8bit.SimMemory8bit 2048 128 128 $60 0 NA $00 $3F NA NA $20 $5F $3F $5F 0x010x020x040x080x100x200x400x80 $3D $5D 0x010x020x040x080x100x200x400x80 $3B $5B 0x100x200x40 $3A $5A 0x200x40 $39 $59 0x020x040x200x40 $38 $58 0x020x040x200x40 $35 $55 0x010x020x080x100x200x40 $34 $54 0x010x020x040x08 $33 $53 0x010x020x040x08 $32 $52 0x010x020x040x080x100x200x400x80 $31 $51 0x010x020x040x080x100x200x400x80 $30 $50 0x010x020x040x080x100x200x400x80 $2F $4F 0x010x020x040x080x400x80 $2E $4E 0x010x020x040x080x100x200x400x80 $2D $4D 0x010x020x040x080x100x200x400x80 $2C $4C 0x010x020x040x080x100x200x400x80 $2B $4B 0x010x020x040x080x100x200x400x80 $29 $49 0x010x020x04 $21 $41 0x010x020x040x080x10 $1E $3E 0x010x020x040x080x100x200x40 $1D $3D 0x010x020x040x080x100x200x400x80 $1C $3C 0x010x020x040x08 $1B $3B 0x010x020x040x080x100x200x400x80 $1A $3A 0x010x020x040x080x100x200x400x80 $19 $39 0x010x020x040x080x100x200x400x80 $18 $38 0x010x020x040x080x100x200x400x80 $17 $37 0x010x020x040x080x100x200x400x80 $16 $36 0x010x020x040x080x100x200x400x80 $0F $2F 0x010x020x040x080x100x200x400x80 $0E $2E 0x010x020x040x080x100x200x400x80 $0D $2D 0x010x020x040x080x100x200x400x80 $08 $28 0x010x020x040x080x100x200x400x80 $07 $27 0x010x020x040x080x100x200x400x80 $06 $26 0x010x020x040x080x100x200x400x80 $05 $25 0x010x020x040x080x100x200x400x80 $04 $24 0x010x020x040x080x100x200x400x80 [PDIP:SOIC] 20 [MOSI:DI:SDA:'OC1A:PCINT0:PB0] DI: Data input in USI 3-wire mode. USI 3-wire mode does not override normal port functions., so pin must be configure as an input. SDA: Serial data in USI 2-wire mode. Serial data pin is bi-directional and uses open-col-lector output. The SDA pin is enabled by setting the pin as an output. The pin is pulled low when the PORTB0 or USI shiftregister is zero when DDB0 is set (one). Pull-up is disabled in USI 2-wire mode. OC1A: Inverted Timer/Counter1 PWM Output A: The PB0 pin can serve as an Inverted output for the PWM mode if not used in programming or USI. The PB0 pin has to be configured as an output (DDB0 set (one)) to serve this function. For further reading on PCINT0 please refer to the manual [MISO:DO:OC1A:PCINT0:PB1] DO: Data output in USI 3-wire mode. Data output (DO) overrides PORTB1 value and it is driven to the port when the data direction bit DDB1 is set (one). However the PORTB1 bit still controls the pullup, enabling pullup if direction is input and PORTB1 is set(one). OC1A: Output compare match output: The PB1 pin can serve as an output for the Timer/Counter1 compare match A. The PB1 pin has to be configured as an output (DDB3 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM mode timer function if not used in programming or USI. PCINT0: Pin Change Interrupt 0 pin. Pin change interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate functions do not mask the interrupt. The masking alternate functions are the output compare match out-put OC1A and data output DO in USI 3-wire mode. Digital input is enabled on pin PB4 also in SLEEP modes, if the pin change interrupt is enabled and not masked by the alternate function [SCK:SCL:'OC1B:PCINT0:PB2] SCK: Clock input or output in USI 3-wire mode. When the SPI is enabled this pin is con-figured [OC1B:PCINT0:PB3] OC1B: Output compare match output: The PB3 pin can serve as an output for the Timer/Counter1 compare match B. The PB3 pin has to be configured as an output (DDB3 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM mode. PCINT0: Pin Change Interrupt 0 pin. Pin change interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate functions do not mask the interrupt. The masking alternate function is the output compare match output OC1B. Digital input is enabled on pin PB3 also in SLEEP modes, if the pin change interrupt is enabled and not masked by the alternate function [VCC] [GND] [ADC7:XTAL1:PCINT1:PB4] ADC7: ADC input channel 7. Configure the port pins as inputs with the internal pull-ups switched off to avoid the digital port function from interfering with the function of the ana-log to digital converter. XTAL1: Chip clock oscillator pin 1. Used for all chip clock sources except internal cali-brateble RC oscillator and PLL clock. When used as a clock pin, the pin can not be used as an I/O pin. When using internal calibratable RC oscillator or PLL clock as chip clock sources, PB4 serves as an ordinary I/O pin. PCINT1: Pin Change Interrupt 1 pin. Pin change interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate functions do not mask the interrupt. The masking alternate functions are the XTAL1 inputs. Digital input is enabled on pin PB4 also in SLEEP modes, if the pin change interrupt is enabled and not masked by the alternate functions [ADC8:XTAL2:PCINT1:PB5] ADC8: ADC input channel 8. Configure the port pins as inputs with the internal pull-ups switched off to avoid the digital port function from interfering with the function of the ana-log to digital converter. XTAL2: Chip clock oscillator pin 2. Used as clock pin for all chip clock sources except internal calibrateble RC oscillator, external clock and PLL clock. When used as a clock pin, the pin can not be used as an I/O pin. When using internal calibratable RC oscillator, external clock or PLL clock as chip clock sources, PB5 serves as an ordinary I/O pin. PCINT1: Pin Change Interrupt 1 pin. Pin change interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate functions do not mask the interrupt. The masking alternate functions are the XTAL2 outputs. Digital input is enabled on pin PB5 also in SLEEP modes, if the pin change interrupt is enabled and not masked by the alternate function [ADC9:INT0:T0:PCINT1:PB6] ADC9: ADC input channel 9. Configure the port pins as inputs with the internal pull-ups switched off to avoid the digital port function from interfering with the function of the analog to digital converter. INT0: External Interrupt source 0: The PB6 pin can serve as an external interrupt source enabled by setting (one) the bit INT0 in the general input mask register (GIMSK). T0: Timer/Counter0 External Counter Clock Input is enabled by setting (one) the bits CS02 and CS01 in the Timer/Counter0 control register (TCCR0). PCINT1: Pin Change Interrupt 1 pin. Pin change interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate functions do not mask the interrupt. The masking alternate functions are the external low level Interrupt source 0 (INT0) and the Timer/Counter0 external counter clock input (T0). Digital input is enabled on pin PB6 also in SLEEP modes, if the pin change interrupt is enabled and not masked by the alternate functio [ADC10:'RESET:PCINT1:PB7] ADC10: ADC input channel 10. Configure the port pins as inputs with the internal pull-ups switched off to avoid the digital port function from interfering with the function of the analog to digital converter. RESET: External Reset Input is active low and enabled by unprogramming (“1”) the RSTDISBL fuse. Pullup is activated and output driver and digital input are deactivated when the pin is used as the RESET pin. PCINT1: Pin Change Interrupt 1 pin. Pin change interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate function do not mask the interrupt. The masking alternate function is the pin usage as RESET. Digital input is enabled on pin PB7 also in SLEEP modes, if the pin change interrupt is enabled and not masked by the alternate functi [ADC6:AIN1:PA7] AIN1: Analog Comparator Negative Input and ADC6: ADC input channel 6. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the analog comparator or analog to digital converter. PCINT1: Pin Change Interrupt 1 pin. Pin change interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate function do not mask the interrupt. The masking alternate function is the analog comparator.Digital input is enabled on pin PA7 also in SLEEP modes, if the pin change interrupt is enabled and not masked by the alternate functio [ADC5:AIN0:PA6] AIN0: Analog Comparator Positive Input and ADC5: ADC input channel 5. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the analog comparator or analog to digital converter. PCINT1: Pin Change Interrupt 1 pin. Pin change interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate function do not mask the interrupt. The masking alternate function is the analog comparator.Digital input is enabled on pin PA6 also in SLEEP modes, if the pin change interrupt is enabled and not masked by the alternate functio [ADC4:PA5] ADC4/ADC3: ADC input channel 4 and 3. Configure the port pins as inputs with the internal pull-ups switched off to avoid the digital port function from interfering with the function of the analog to digital converter. [ADC3:PA4] ADC4/ADC3: ADC input channel 4 and 3. Configure the port pins as inputs with the internal pull-ups switched off to avoid the digital port function from interfering with the function of the analog to digital converter. [AVCC] [AGND] [AREF:PA3] AREF: External reference for ADC. Pullup and output driver are disabled on PA3 when the pin is used as an external reference or Internal Voltage Reference (2.56V) with external capacitor at the AREF pin by setting (one) the bit REFS0 in the ADC Multiplexer Selection Register (ADMUX). PCINT1: Pin Change Interrupt 1 pin. Pin change interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate function do not mask the interrupt. The masking alternate function is the pin usage as an analog refer-ence for the ADC. Digital input is enabled on pin PA3 also in SLEEP modes, if the pin change interrupt is enabled and not masked by the alternate function. Please refer to the manual for further details [ADC2:PA2] [ADC1:PA1] [ADC0:PA0] [LOW:HIGH] 8 PLLCK Use PLL for internal clock 1 CKOPT Oscillator options 1 SUT1 Select start-up time 1 SUT0 Select start-up time 1 CKSEL3 Select Clock Source 1 CKSEL2 Select Clock Source 0 CKSEL1 Select Clock Source 0 CKSEL0 Select Clock Source 1 63 0x40 0x00 CKOPT fuse (operation dependent of CKSEL fuses); [CKOPT=0] 0xBF 0x01 PLL Clock; Start-up time: 1K CK + 0 ms; [CKSEL=0001 SUT=00] 0xBF 0x11 PLL Clock; Start-up time: 1K CK + 4 ms; [CKSEL=0001 SUT=01] 0xBF 0x21 PLL Clock; Start-up time: 1K CK + 64 ms; [CKSEL=0001 SUT=10] 0xBF 0x31 PLL Clock; Start-up time: 16K CK + 64 ms; [CKSEL=0001 SUT=11] 0xBF 0x80 Ext. Clock; Start-up time: 6 CK + 0 ms; [CKSEL=0000 SUT=00] 0xBF 0x90 Ext. Clock; Start-up time: 6 CK + 4 ms; [CKSEL=0000 SUT=01] 0xBF 0xA0 Ext. Clock; Start-up time: 6 CK + 64 ms; [CKSEL=0000 SUT=10] 0xBF 0x81 Int. RC Osc. 1 MHz; Start-up time: 6 CK + 0 ms; [CKSEL=0001 SUT=00] 0xBF 0x91 Int. RC Osc. 1 MHz; Start-up time: 6 CK + 4 ms; [CKSEL=0001 SUT=01] 0xBF 0xA1 Int. RC Osc. 1 MHz; Start-up time: 6 CK + 64 ms; [CKSEL=0001 SUT=10]; default value 0xBF 0x82 Int. RC Osc. 2 MHz; Start-up time: 6 CK + 0 ms; [CKSEL=0010 SUT=00] 0xBF 0x92 Int. RC Osc. 2 MHz; Start-up time: 6 CK + 4 ms; [CKSEL=0010 SUT=01] 0xBF 0xA2 Int. RC Osc. 2 MHz; Start-up time: 6 CK + 64 ms; [CKSEL=0010 SUT=10] 0xBF 0x83 Int. RC Osc. 4 MHz; Start-up time: 6 CK + 0 ms; [CKSEL=0011 SUT=00] 0xBF 0x93 Int. RC Osc. 4 MHz; Start-up time: 6 CK + 4 ms; [CKSEL=0011 SUT=01] 0xBF 0xA3 Int. RC Osc. 4 MHz; Start-up time: 6 CK + 64 ms; [CKSEL=0011 SUT=10] 0xBF 0x84 Int. RC Osc. 8 MHz; Start-up time: 6 CK + 0 ms; [CKSEL=0100 SUT=00] 0xBF 0x94 Int. RC Osc. 8 MHz; Start-up time: 6 CK + 4 ms; [CKSEL=0100 SUT=01] 0xBF 0xA4 Int. RC Osc. 8 MHz; Start-up time: 6 CK + 64 ms; [CKSEL=0100 SUT=10] 0xBF 0x85 Ext. RC Osc. - 0.9 MHz; Start-up time: 18 CK + 0 ms; [CKSEL=0101 SUT=00] 0xBF 0x95 Ext. RC Osc. - 0.9 MHz; Start-up time: 18 CK + 4 ms; [CKSEL=0101 SUT=01] 0xBF 0xA5 Ext. RC Osc. - 0.9 MHz; Start-up time: 18 CK + 64 ms; [CKSEL=0101 SUT=10] 0xBF 0xB5 Ext. RC Osc. - 0.9 MHz; Start-up time: 6 CK + 4 ms; [CKSEL=0101 SUT=11] 0xBF 0x86 Ext. RC Osc. 0.9 MHz - 3.0 MHz; Start-up time: 18 CK + 0 ms; [CKSEL=0110 SUT=00] 0xBF 0x96 Ext. RC Osc. 0.9 MHz - 3.0 MHz; Start-up time: 18 CK + 4 ms; [CKSEL=0110 SUT=01] 0xBF 0xA6 Ext. RC Osc. 0.9 MHz - 3.0 MHz; Start-up time: 18 CK + 64 ms; [CKSEL=0110 SUT=10] 0xBF 0xB6 Ext. RC Osc. 0.9 MHz - 3.0 MHz; Start-up time: 6 CK + 4 ms; [CKSEL=0110 SUT=11] 0xBF 0x87 Ext. RC Osc. 3.0 MHz - 8.0 MHz; Start-up time: 18 CK + 0 ms; [CKSEL=0111 SUT=00] 0xBF 0x97 Ext. RC Osc. 3.0 MHz - 8.0 MHz; Start-up time: 18 CK + 4 ms; [CKSEL=0111 SUT=01] 0xBF 0xA7 Ext. RC Osc. 3.0 MHz - 8.0 MHz; Start-up time: 18 CK + 64 ms; [CKSEL=0111 SUT=10] 0xBF 0xB7 Ext. RC Osc. 3.0 MHz - 8.0 MHz; Start-up time: 6 CK + 4 ms; [CKSEL=0111 SUT=11] 0xBF 0x88 Ext. RC Osc. 8.0 MHz - 12.0 MHz; Start-up time: 18 CK + 0 ms; [CKSEL=1000 SUT=00] 0xBF 0x98 Ext. RC Osc. 8.0 MHz - 12.0 MHz; Start-up time: 18 CK + 4 ms; [CKSEL=1000 SUT=01] 0xBF 0xA8 Ext. RC Osc. 8.0 MHz - 12.0 MHz; Start-up time: 18 CK + 64 ms; [CKSEL=1000 SUT=10] 0xBF 0xB8 Ext. RC Osc. 8.0 MHz - 12.0 MHz; Start-up time: 6 CK + 4 ms; [CKSEL=1000 SUT=11] 0xBF 0x89 Ext. Low-Freq. Crystal; Start-up time: 1K CK + 4 ms; [CKSEL=1001 SUT=00] 0xBF 0x99 Ext. Low-Freq. Crystal; Start-up time: 1K CK + 64 ms; [CKSEL=1001 SUT=01] 0xBF 0xA9 Ext. Low-Freq. Crystal; Start-up time: 32K CK + 64 ms; [CKSEL=1001 SUT=10] 0xBF 0x8A Ext. Crystal/Resonator Low Freq.; Start-up time: 258 CK + 4 ms; [CKSEL=1010 SUT=00] 0xBF 0x9A Ext. Crystal/Resonator Low Freq.; Start-up time: 258 CK + 64 ms; [CKSEL=1010 SUT=01] 0xBF 0xAA Ext. Crystal/Resonator Low Freq.; Start-up time: 1K CK + 0 ms; [CKSEL=1010 SUT=10] 0xBF 0xBA Ext. Crystal/Resonator Low Freq.; Start-up time: 1K CK + 4 ms; [CKSEL=1010 SUT=11] 0xBF 0x8B Ext. Crystal/Resonator Low Freq.; Start-up time: 1K CK + 64 ms; [CKSEL=1011 SUT=00] 0xBF 0x9B Ext. Crystal/Resonator Low Freq.; Start-up time: 16K CK + 0 ms; [CKSEL=1011 SUT=01] 0xBF 0xAB Ext. Crystal/Resonator Low Freq.; Start-up time: 16K CK + 4 ms; [CKSEL=1011 SUT=10] 0xBF 0xBB Ext. Crystal/Resonator Low Freq.; Start-up time: 16K CK + 64 ms; [CKSEL=1011 SUT=11] 0xBF 0x8C Ext. Crystal/Resonator Medium Freq.; Start-up time: 258 CK + 4 ms; [CKSEL=1100 SUT=00] 0xBF 0x9C Ext. Crystal/Resonator Medium Freq.; Start-up time: 258 CK + 64 ms; [CKSEL=1100 SUT=01] 0xBF 0xAC Ext. Crystal/Resonator Medium Freq.; Start-up time: 1K CK + 0 ms; [CKSEL=1100 SUT=10] 0xBF 0xBC Ext. Crystal/Resonator Medium Freq.; Start-up time: 1K CK + 4 ms; [CKSEL=1100 SUT=11] 0xBF 0x8D Ext. Crystal/Resonator Medium Freq.; Start-up time: 1K CK + 64 ms; [CKSEL=1101 SUT=00] 0xBF 0x9D Ext. Crystal/Resonator Medium Freq.; Start-up time: 16K CK + 0 ms; [CKSEL=1101 SUT=01] 0xBF 0xAD Ext. Crystal/Resonator Medium Freq.; Start-up time: 16K CK + 4 ms; [CKSEL=1101 SUT=10] 0xBF 0xBD Ext. Crystal/Resonator Medium Freq.; Start-up time: 16K CK + 64 ms; [CKSEL=1101 SUT=11] 0xBF 0x8E Ext. Crystal/Resonator High Freq.; Start-up time: 258 CK + 4 ms; [CKSEL=1110 SUT=00] 0xBF 0x9E Ext. Crystal/Resonator High Freq.; Start-up time: 258 CK + 64 ms; [CKSEL=1110 SUT=01] 0xBF 0xAE Ext. Crystal/Resonator High Freq.; Start-up time: 1K CK + 0 ms; [CKSEL=1110 SUT=10] 0xBF 0xBE Ext. Crystal/Resonator High Freq.; Start-up time: 1K CK + 4 ms; [CKSEL=1110 SUT=11] 0xBF 0x8F Ext. Crystal/Resonator High Freq.; Start-up time: 1K CK + 64 ms; [CKSEL=1111 SUT=00] 0xBF 0x9F Ext. Crystal/Resonator High Freq.; Start-up time: 16K CK + 0 ms; [CKSEL=1111 SUT=01] 0xBF 0xAF Ext. Crystal/Resonator High Freq.; Start-up time: 16K CK + 4 ms; [CKSEL=1111 SUT=10] 0xBF 0xBF Ext. Crystal/Resonator High Freq.; Start-up time: 16K CK + 64 ms; [CKSEL=1111 SUT=11] 5 RSTDISBL Select if PB/ is I/O pin or RESET pin 1 SPIEN Enable Serial Program and Data Downloading 0 EESAVE EEPROM memory is preserved through the Chip Erase 1 BODLEVEL Brown out detector trigger level 1 BODEN Brown out detector enable 1 6 0x10 0x00 Reset Disabled (Enable PB7 as i/o pin); [RSTDISBL=0] 0x08 0x00 Serial program downloading (SPI) enabled; [SPIEN=0] 0x04 0x00 Preserve EEPROM memory through the Chip Erase cycle; [EESAVE=0] 0x02 0x00 Brown-out detection level at VCC=4.0 V; [BODLEVEL=0] 0x02 0x02 Brown-out detection level at VCC=2.7 V; [BODLEVEL=1] 0x01 0x00 Brown-out detection enabled; [BODEN=0] [LB1 = 1 : LB2 = 1] No memory lock features enabled. [LB1 = 0 : LB2 = 1] Further programming of Flash and EEPROM is enabled. [LB1 = 0 : LB2 = 0] Same as previous, but verify is also disabled 3 2 0x03 0x03 Mode 1: No memory lock features enabled 0x03 0x02 Mode 2: Further programming disabled 0x03 0x00 Mode 3: Further programming and verification disabled LB1 Lockbit LB2 Lockbit 0xff,0xf7 1,0x08,0x08,WARNING! These fuse settings will disable the ISP interface! 1,0x10,0x00,WARNING! Disabling external reset will make the ISP interface inaccessible! 1,0x08,0x08,WARNING! These fuse settings will disable the ISP interface! 1,0x10,0x00,WARNING! Disabling external reset will make the ISP interface inaccessible! 0x00,1.0 MHz 0x01,2.0 MHz 0x02,4.0 MHz 0x03,8.0 MHz 32 4 [AD_CONVERTER:ANALOG_COMPARATOR:USI:PORTA:PORTB:EEPROM:WATCHDOG:CPU:TIMER_COUNTER_0:TIMER_COUNTER_1:EXTERNAL_INTERRUPT] [ADMUX:ADCSR:ADCH:ADCL] ((IF ADMUX.ADLAR = 1) LINK [ADCH(1:0):ADCL(7:0)]); (IF ADMUX.ADLAR = 0) LINK [ADCH(7:0):ADCL(7:6)]); io_analo.bmp AD Converter Feature list: 10-bit Resolution. 0.5 LSB Integral Non-Linearity. +-2 LSB Absolute Accuracy. TBD - 260 µs Conversion Time. Up to TBD kSPS at maximum resolution. 8 Multiplexed Single Ended Input Channels. 7 Differential input channels (TQFP package only). 2 Differential input channels with optional gain of 10x and 200x (TQFP package only). Optional left adjustment for ADC result readout. 0 - VCC ADC Input Voltage Range. Selectable 2.56 V ADC reference voltage. Free Running or Single Conversion Mode. Interrupt on ADC Conversion Complete. Sleep Mode Noise ADMUX The ADC multiplexer Selection Register $07 $27 io_analo.bmp Y REFS1 Reference Selection Bit 1 These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin. RW 0 REFS0 Reference Selection Bit 0 These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin. RW 0 ADLAR Left Adjust Result The ADLAR bit affects the presentation of the ADC conversion result in the ADC data register. If ADLAR is cleared, the result is right adjusted. If ADLAR is set, the result is left adjusted. Changing the ADLAR bit will affect the ADC data register immediately, regardless of any ongoing conversions. For a complete description of this bit, see “The ADC Data Register -ADCL and ADCH” on page 198. RW 0 MUX4 Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). RW 0 MUX3 Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). RW 0 MUX2 Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). RW 0 MUX1 Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). RW 0 MUX0 Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). RW 0 ADCSR ADCSRA The ADC Control and Status register $06 $26 io_flag.bmp Y ADEN ADC Enable Writing a logical ‘1’ to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion. RW 0 ADSC ADC Start Conversion In Single Conversion Mode, a logical ‘1’ must be written to this bit to start each conversion. In Free Running Mode, a logical ‘1’ must be written to this bit to start the first conversion. The first time ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, an extended conversion will result. This extended conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. When a dummy conversion precedes a real conversion, ADSC will stay high until the real conversion completes. Writing a 0 to this bit has no effect RW 0 ADFR ADC Free Running Select When this bit is set (one) the ADC operates in Free Running Mode. In this mode, the ADC samples and updates the data registers continuously. Clearing this bit (zero) will terminate Free Running Mode. RW 0 ADIF ADC Interrupt Flag This bit is set (one) when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set (one). ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a read-modify-write on ADCSR, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used. RW 0 ADIE ADC Interrupt Enable When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Complete Interrupt is activated. RW 0 ADPS2 ADC Prescaler Select Bits These bits determine the division factor between the XTAL frequency and the input clock to the ADC. RW 0 ADPS1 ADC Prescaler Select Bits These bits determine the division factor between the XTAL frequency and the input clock to the ADC. RW 0 ADPS0 ADC Prescaler Select Bits These bits determine the division factor between the XTAL frequency and the input clock to the ADC. RW 0 ADCH ADC Data Register High Byte When an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. The selected channel is differential if MUX4..0 are between ‘01000’ and ‘11101’, otherwise the selected channel is single ended. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8 bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUX4..0 bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adju $05 $25 io_analo.bmp N ADCH7 ADC Data Register High Byte Bit 7 RW 0 ADCH6 ADC Data Register High Byte Bit 6 RW 0 ADCH5 ADC Data Register High Byte Bit 5 RW 0 ADCH4 ADC Data Register High Byte Bit 4 RW 0 ADCH3 ADC Data Register High Byte Bit 3 RW 0 ADCH2 ADC Data Register High Byte Bit 2 RW 0 ADCH1 ADC Data Register High Byte Bit 1 RW 0 ADCH0 ADC Data Register High Byte Bit 0 RW 0 ADCL ADC Data Register Low Byte When an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. The selected channel is differential if MUX4..0 are between ‘01000’ and ‘11101’, otherwise the selected channel is single ended. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8 bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUX4..0 bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right ad $04 $24 io_analo.bmp N ADCL7 ADC Data Register Low Byte Bit 7 RW 0 ADCL6 ADC Data Register Low Byte Bit 6 RW 0 ADCL5 ADC Data Register Low Byte Bit 5 RW 0 ADCL4 ADC Data Register Low Byte Bit 4 RW 0 ADCL3 ADC Data Register Low Byte Bit 3 RW 0 ADCL2 ADC Data Register Low Byte Bit 2 RW 0 ADCL1 ADC Data Register Low Byte Bit 1 RW 0 ADCL0 ADC Data Register Low Byte Bit 0 RW 0 [ACSR] io_analo.bmp AlgComp_06 ACSR Analog Comparator Control And Status Register $08 $28 io_analo.bmp Y ACD Analog Comparator Disable When this bit is written logic one, the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed. RW 0 ACBG Analog Comparator Bandgap Select When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. See “Internal Voltage Reference” on page 42. RW 0 ACO Analog Compare Output The output of the analog comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1-2 clock cycles. R NA ACI Analog Comparator Interrupt Flag This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hard-ware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag. RW 0 ACIE Analog Comparator Interrupt Enable When the ACIE bit is written logic one and the I-bit in the Status Register is set, the analog comparator interrupt is acti-vated. When written logic zero, the interrupt is disabled. RW 0 ACME Analog Comparator Multiplexer Enable When the ACME bit is set (one) and the ADC is switched off (ADEN in ADCSR is zero), MUX3...0 in ADMUX select the input pin to replace the negative input to the Analog Comparator, as shown in the table in the datasheet. If ACME is cleared (zero) or ADEN is set (one), PA7(AIN1) is applied to the negative input to the Analog Comparator. RW 0 ACIS1 Analog Comparator Interrupt Mode Select bit 1 These bits determine which comparator events that trigger the Analog Comparator interrupt. RW 0 ACIS0 Analog Comparator Interrupt Mode Select bit 0 These bits determine which comparator events that trigger the Analog Comparator interrupt. RW 0 [USIDR:USISR:USICR] io_com.bmp Universal Serial Interface USIDR USI Data Register $0F $2F io_com.bmp N USIDR7 USI Data Register bit 7 RW 0 USIDR6 USI Data Register bit 6 RW 0 USIDR5 USI Data Register bit 5 RW 0 USIDR4 USI Data Register bit 4 RW 0 USIDR3 USI Data Register bit 3 RW 0 USIDR2 USI Data Register bit 2 RW 0 USIDR1 USI Data Register bit 1 RW 0 USIDR0 USI Data Register bit 0 RW 0 USISR USI Status Register $0E $2E io_flag.bmp Y USISIF Start Condition Interrupt Flag RW 0 USIOIF Counter Overflow Interrupt Flag RW 0 USIPF Stop Condition Flag RW 1 USIDC Data Output Collision RW 0 USICNT3 USI Counter Value Bit 3 RW 0 USICNT2 USI Counter Value Bit 2 RW 0 USICNT1 USI Counter Value Bit 1 RW 0 USICNT0 USI Counter Value Bit 0 RW 0 USICR USI Control Register $0D $2D io_flag.bmp Y USISIE Start Condition Interrupt Enable RW 0 USIOIE Counter Overflow Interrupt Enable RW 0 USIWM1 USI Wire Mode Bit 1 RW 1 USIWM0 USI Wire Mode Bit 0 RW 0 USICS1 USI Clock Source Select Bit 1 RW 0 USICS0 USI Clock Source Select Bit 0 RW 0 USICLK Clock Strobe R 0 USITC Toggle Clock Port Pin W 0 [PORTA:DDRA:PINA] io_port.bmp AVRSimIOPort.SimIOPort PORTA Port A Data Register $1B $3B io_port.bmp N PORTA7 Port A Data Register bit 7 RW 0 PORTA6 Port A Data Register bit 6 RW 0 PORTA5 Port A Data Register bit 5 RW 0 PORTA4 Port A Data Register bit 4 RW 0 PORTA3 Port A Data Register bit 3 RW 0 PORTA2 Port A Data Register bit 2 RW 0 PORTA1 Port A Data Register bit 1 RW 0 PORTA0 Port A Data Register bit 0 RW 0 DDRA Port A Data Direction Register $1A $3A io_flag.bmp N DDA7 Data Direction Register, Port A, bit 7 RW 0 DDA6 Data Direction Register, Port A, bit 6 RW 0 DDA5 Data Direction Register, Port A, bit 5 RW 0 DDA4 Data Direction Register, Port A, bit 4 RW 0 DDA3 Data Direction Register, Port A, bit 3 RW 0 DDA2 Data Direction Register, Port A, bit 2 RW 0 DDA1 Data Direction Register, Port A, bit 1 RW 0 DDA0 Data Direction Register, Port A, bit 0 RW 0 PINA Port A Input Pins The Port A Input Pins address - PINA - is not a register, and this address enables access to the physical value on each Port A pin. When reading PORTA the Port A Data Latch is read, and when reading PINA, the logical values present on the pins are read. $19 $39 io_port.bmp N PINA7 Input Pins, Port A bit 7 RW Hi-Z PINA6 Input Pins, Port A bit 6 RW Hi-Z PINA5 Input Pins, Port A bit 5 RW Hi-Z PINA4 Input Pins, Port A bit 4 RW Hi-Z PINA3 Input Pins, Port A bit 3 RW Hi-Z PINA2 Input Pins, Port A bit 2 RW Hi-Z PINA1 Input Pins, Port A bit 1 RW Hi-Z PINA0 Input Pins, Port A bit 0 RW Hi-Z [PORTB:DDRB:PINB] io_port.bmp AVRSimIOPort.SimIOPort PORTB Port B Data Register $18 $38 io_port.bmp N PORTB7 Port B Data Register bit 7 RW 0 PORTB6 Port B Data Register bit 6 RW 0 PORTB5 Port B Data Register bit 5 RW 0 PORTB4 Port B Data Register bit 4 RW 0 PORTB3 Port B Data Register bit 3 RW 0 PORTB2 Port B Data Register bit 2 RW 0 PORTB1 Port B Data Register bit 1 RW 0 PORTB0 Port B Data Register bit 0 RW 0 DDRB Port B Data Direction Register $17 $37 io_flag.bmp N DDB7 Port B Data Direction Register bit 7 RW 0 DDB6 Port B Data Direction Register bit 6 RW 0 DDB5 Port B Data Direction Register bit 5 RW 0 DDB4 Port B Data Direction Register bit 4 RW 0 DDB3 Port B Data Direction Register bit 3 RW 0 DDB2 Port B Data Direction Register bit 2 RW 0 DDB1 Port B Data Direction Register bit 1 RW 0 DDB0 Port B Data Direction Register bit 0 RW 0 PINB Port B Input Pins The Port B Input Pins address - PINB - is not a register, and this address enables access to the physical value on each Port B pin. When reading PORTB, the Port B Data Latch is read, and when reading PINB, the logical values present on the pins are read. $16 $36 io_port.bmp N PINB7 Port B Input Pins bit 7 R 0 PINB6 Port B Input Pins bit 6 R 0 PINB5 Port B Input Pins bit 5 R 0 PINB4 Port B Input Pins bit 4 R 0 PINB3 Port B Input Pins bit 3 R 0 PINB2 Port B Input Pins bit 2 R 0 PINB1 Port B Input Pins bit 1 R 0 PINB0 Port B Input Pins bit 0 R 0 [EEAR:EEDR:EECR] io_cpu.bmp EEPROM_02.xml EEAR EEPROM Read/Write Access The EEPROM access register is accessible in the I/O space. The write access time is in the range of 2.5 - 4ms, depending on the V CC voltages. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains code that writes the EEPROM, some pre-caution must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. CPU operation under these conditions is likely cause the program counter to perform unintentional jumps and eventually execute the EEPROM write code. To secure EEPROM integrity, the user is advised to use an external under-voltage reset circuit in this case. In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction $1E $3E io_cpu.bmp N EEAR6 EEPROM Read/Write Access bit 6 RW 0 EEAR5 EEPROM Read/Write Access bit 5 RW 0 EEAR4 EEPROM Read/Write Access bit 4 RW 0 EEAR3 EEPROM Read/Write Access bit 3 RW 0 EEAR2 EEPROM Read/Write Access bit 2 RW 0 EEAR1 EEPROM Read/Write Access bit 1 RW 0 EEAR0 EEPROM Read/Write Access bit 0 RW 0 EEDR EEPROM Data Register For the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR. $1D $3D io_cpu.bmp N EEDR7 EEPROM Data Register bit 7 RW 0 EEDR6 EEPROM Data Register bit 6 RW 0 EEDR5 EEPROM Data Register bit 5 RW 0 EEDR4 EEPROM Data Register bit 4 RW 0 EEDR3 EEPROM Data Register bit 3 RW 0 EEDR2 EEPROM Data Register bit 2 RW 0 EEDR1 EEPROM Data Register bit 1 RW 0 EEDR0 EEPROM Data Register bit 0 RW 0 EECR EEPROM Control Register $1C $3C io_flag.bmp Y EERIE EEProm Ready Interrupt Enable When the I-bit in SREG and EERIE are set (one), the EEPROM Ready Interrupt is enabled. When cleared (zero), the interrupt is disabled. The EEPROM Ready Interrupt generates a constant interrupt when EEWE is cleared (zero). RW 0 EEMWE EEPROM Master Write Enable The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set(one) setting EEWE will write data to the EEPROM at the selected address If EEMWE is zero, setting EEWE will have no effect. When EEMWE has been set (one) by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for a EEPROM write procedure. RW 0 EEWE EEPROM Write Enable The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 2 and 3 is unessential): 1. Wait until EEWE becomes zero. 2. Write new EEPROM address to EEARL and EEARH (optional). 3. Write new EEPROM data to EEDR (optional). 4. Write a logical one to the EEMWE bit in EECR (to be able to write a logical one to the EEMWE bit, the EEWE bit mustbewritten to zero in thesamecycle). 5. Within four clock cycles after setting EEMWE, write a logical one to EEWE. When the write access time (typically 2.5 ms at V CC =5Vor 4msatV CC = 2.7V) has elapsed, the EEWE bit is cleared (zero) by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted or two cycles before the next instruction is executed. Caution: An interrupt between step 4 and step 5 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR regis-ter will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the 4 last steps to avoid these problems. RW 0 EERE EEPROM Read Enable The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be set. When the EERE bit is cleared (zero) by hardware, requested data is found in the EEDR register. The EEPROM read access takes one instruction and there is no need to poll the EERE bit. When EERE has been set, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress when new data or address is written to the EEPROM I/O registers, the write operation will be interrupted, and the result is undefined. RW 0 [WDTCR] io_watch.bmp WDTCR WDTCSR Watchdog Timer Control Register $21 $41 io_flag.bmp Y WDCE WDTOE Watchdog Change Enable This bit must be set when the WDE bit is written to logic zero.Otherwise,the watchdog will not be disabled.Once written to one,hardware will clear this bit after four clock cycles.Refer to the description of the WDE bit for a watchdog disable procedure.This bit must also be set when changing the prescaler bits. RW 0 WDE Watch Dog Enable When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog RW 0 WDP2 Watch Dog Timer Prescaler bit 2 The WDP2,WDP1,and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. RW 0 WDP1 Watch Dog Timer Prescaler bit 1 The WDP2,WDP1,and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. RW 0 WDP0 Watch Dog Timer Prescaler bit 0 The WDP2,WDP1,and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. RW 0 [SREG:SP:MCUCR:MCUSR:OSCCAL] io_cpu.com SREG Status Register $3F $5F io_sreg.bmp Y I Global Interrupt Enable The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable bit is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. RW 0 T Bit Copy Storage The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction. RW 0 H Half Carry Flag The half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed information. RW 0 S Sign Bit The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruc-tion Set Description for detailed information. RW 0 V Two's Complement Overflow Flag The two’s complement overflow flag V supports two’s complement arithmetics. See the Instruction Set Description for detailed information. RW 0 N Negative Flag The negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information. RW 0 Z Zero Flag The zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information. RW 0 C Carry Flag The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software. RW 0 SP Stack Pointer $3D $5D io_sreg.bmp N SP7 Stack Pointer Bit 7 RW 0 SP6 Stack Pointer Bit 6 RW 0 SP5 Stack Pointer Bit 5 RW 0 SP4 Stack Pointer Bit 4 RW 0 SP3 Stack Pointer Bit 3 RW 0 SP2 Stack Pointer Bit 2 RW 0 SP1 Stack Pointer Bit 1 RW 0 SP0 Stack Pointer Bit 0 RW 0 MCUCR MCU Control Register The MCU Control Register contains control bits for general MCU functions. $35 $55 io_cpu.bmp Y PUD Pull-up Disable RW 0 SE Sleep Enable The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmers purpose, it is recommended to set the Sleep Enable SE bit just before the execution of the SLEEP instruction. R 0 SM1 Sleep Mode Select Bit 1 RW 0 SM0 Sleep Mode Select Bit 0 RW 0 ISC01 Interrupt Sense Control 0 bit 1 R 0 ISC00 Interrupt Sense Control 0 bit 0 R 0 MCUSR MCU Status register The MCU Status Registerprovides information on which reset source caused a MCU reset. $34 $54 io_cpu.bmp Y WDRF Watchdog Reset Flag RW 0 BORF Brown-out Reset Flag RW 0 EXTRF External Reset Flag After a power-on reset, this bit is undefined (X). It will be set by an external reset. A watchdog reset will leave this bit unchanged. RW 0 PORF Power-On Reset Flag This bit is set by a power-on reset. A watchdog reset or an external reset will leave this bit unchanged RW 0 OSCCAL Status Register $31 $51 io_sreg.bmp N CAL7 Oscillator Calibration Value Bit 7 RW 0 CAL6 Oscillator Calibration Value Bit 6 RW 0 CAL5 Oscillator Calibration Value Bit 5 RW 0 CAL4 OSCCAL4 Oscillator Calibration Value Bit 4 RW 0 CAL3 OSCCAL3 Oscillator Calibration Value Bit 3 RW 0 CAL2 OSCCAL2 Oscillator Calibration Value Bit 2 RW 0 CAL1 OSCCAL1 Oscillator Calibration Value Bit 1 RW 0 CAL0 OSCCAL0 Oscillator Calibration Value Bit 0 RW 0 [TIMSK:TIFR:TCCR0:TCNT0] io_timer.bmp t81 The 8-bit Timer/Counter0 can select clock source from CK, prescaled CK, or an external pin. In addition it can be stopped as described in “Timer/Counter0 Control Register - TCCR0” on page 35. The overflow status flag is found in “The Timer/Counter Interrupt Flag Register - TIFR” on page 29. Control signals are found in the Timer/Counter0 Control Register - TCCR0. The interrupt enable/disable settings for Timer/Counter0 are found in “The Timer/Counter Interrupt Mask Regis-ter - TIMSK” on page 28. When Timer/Counter0 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. The 8-bit Timer/Counter0 features both a high resolution and a high accuracy usage with the lower prescaling opportuni-ties. Similarly, the high prescaling opportuni ties make the Timer/Counter0 useful for lower speed functions or exact timing functions with infrequent actions TIMSK Timer/Counter Interrupt Mask Register $39 $59 io_flag.bmp Y TOIE0 Timer/Counter0 Overflow Interrupt Enable When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register - TIFR. RW 0 TIFR Timer/Counter Interrupt Flag register $38 $58 io_flag.bmp Y TOV0 Timer/Counter0 Overflow Flag The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, and TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. RW 0 TCCR0 Timer/Counter0 Control Register $33 $53 io_flag.bmp Y PSR0 Prescaler Reset Timer/Counter0 When this bit is set (one), the prescaler of the Timer/Counter0 will be reset. The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. This bit will always be read as zero. RW 0 CS02 Clock Select0 bit 2 RW 0 CS01 Clock Select0 bit 1 RW 0 CS00 Clock Select0 bit 0 RW 0 TCNT0 Timer Counter 0 The Timer/Counter0 is realized as an up-counter with read and write access. If the Timer/Counter0 is written and a clock source is present, the Timer/Counter0 continues counting in the clock cycle following the write operation. $32 $52 io_timer.bmp N TCNT07 Timer Counter 0 bit 7 RW 0 TCNT06 Timer Counter 0 bit 6 RW 0 TCNT05 Timer Counter 0 bit 5 RW 0 TCNT04 Timer Counter 0 bit 4 RW 0 TCNT03 Timer Counter 0 bit 3 RW 0 TCNT02 Timer Counter 0 bit 2 RW 0 TCNT01 Timer Counter 0 bit 1 RW 0 TCNT00 Timer Counter 0 bit 0 RW 0 [TCCR1A:TCCR1B:TCNT1:OCR1A:OCR1B:OCR1C:TIMSK:TIFR:PLLCSR] io_timer.bmp t8pwm1_00 TCCR1A Timer/Counter Control Register A $30 $50 io_flag.bmp Y COM1A1 Comparator A Output Mode Bit 1 The COM1A1 and COM1A0 control bits determine any output pin action following a compare match with compare register A in Timer/Counter1. Output pin actions affect pin PB1 (OC1A). Since this is an alternative function to an I/O port, the corresponding direction control bit must be set (one) in order to control an output pin. Note that OC1A is not connected in normal mode. RW 0 COM1A0 Comparator A Output Mode Bit 0 The COM1A1 and COM1A0 control bits determine any output pin action following a compare match with compare register A in Timer/Counter1. Output pin actions affect pin PB1 (OC1A). Since this is an alternative function to an I/O port, the corresponding direction control bit must be set (one) in order to control an output pin. Note that OC1A is not connected in normal mode. RW 0 COM1B1 Comparator B Output Mode Bit 1 The COM1B1 and COM1B0 control bits determine any output pin action following a compare match with compare register B in Timer/Counter1. Output pin actions affect pin PB3 (OC1B). Since this is an alternative function to an I/O port, the corresponding direction control bit must be set (one) in order to control an output pin. Note that OC1B is not connected in normal mode. RW 0 COM1B0 Comparator B Output Mode Bit 0 The COM1B1 and COM1B0 control bits determine any output pin action following a compare match with compare register B in Timer/Counter1. Output pin actions affect pin PB3 (OC1B). Since this is an alternative function to an I/O port, the corresponding direction control bit must be set (one) in order to control an output pin. Note that OC1B is not connected in normal mode. RW 0 FOC1A Force Output Compare Match 1A Writing a logical one to this bit forces a change in the compare match output pin PB1 (OC1A) according to the values already set in COM1A1 and COM1A0. If COM1A1 and COM1A0 written in the same cycle as FOC1A, the new settings will be used. The Force Output Compare bit can be used to change the output pin value regardless of the timer value. The automatic action programmed in COM1A1 and COM1A0 takes place as if a compare match had occurred, but no interrupt is generated. The FOC1A bit always reads as zero. FOC1A is not in use if PWM1A bit is RW 0 FOC1B Force Output Compare Match 1B Writing a logical one to this bit forces a change in the compare match output pin PB3 (OC1B) according to the values already set in COM1B1 and COM1B0. If COM1B1 and COM1B0 written in the same cycle as FOC1B, the new settings will be used. The Force Output Compare bit can be used to change the output pin value regardless of the timer value. The automatic action programmed in COM1B1 and COM1B0 takes place as if a compare match had occurred, but no interrupt is generated. The FOC1B bit always reads as zero. FOC1B is not in use if PWM1B bit is set RW 0 PWM1A Pulse Width Modulator A Enable When set (one) this bit enables PWM mode based on comparator OCR1A in Timer/Counter1 and the counter value is reset to $00 in the CPU clock cycle after a compare match with OCR1C register value. RW 0 PWM1B Pulse Width Modulator B Enable When set (one) this bit enables PWM mode based on comparator OCR1B in Timer/Counter1 and the counter value is reset to $00 in the CPU clock cycle after a compare match with OCR1C register value. RW 0 TCCR1B Timer/Counter Control Register B $2F $4F io_flag.bmp Y CTC1 Clear Timer/Counter on Compare Match When the CTC1 control bit is set (one), Timer/Counter1 is reset to $00 in the CPU clock cycle after a compare match with OCR1C register value. If the control bit is cleared, Timer/Counter1 continues counting and is unaffected by a compare match. RW 0 PSR1 Prescaler Reset Timer/Counter1 When this bit is set (one), the Timer/Counter prescaler will be reset. The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. This bit will always read as zero. RW 0 CS13 Clock Select Bits The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1. RW 0 CS12 Clock Select Bits The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1. RW 0 CS11 Clock Select Bits The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1. RW 0 CS10 Clock Select Bits The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1. RW 0 TCNT1 Timer/Counter Register The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT1 register blocks (removes) the compare match on the following timer clock. Modifying the counter (TCNT1) while the counter is running, introduces a risk of missing a compare match between TCNT1 the OCR2 register. $2E $4E io_timer.bmp N TCNT1_7 Timer/Counter Register Bit 7 RW 0 TCNT1_6 Timer/Counter Register Bit 6 RW 0 TCNT1_5 Timer/Counter Register Bit 5 RW 0 TCNT1_4 Timer/Counter Register Bit 4 RW 0 TCNT1_3 Timer/Counter Register Bit 3 RW 0 TCNT1_2 Timer/Counter Register Bit 2 RW 0 TCNT1_1 Timer/Counter Register Bit 1 RW 0 TCNT1_0 Timer/Counter Register Bit 0 RW 0 OCR1A Output Compare Register The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT1). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC2 pin. $2D $4D io_timer.bmp N OCR1A7 Output Compare Register A Bit 7 RW 0 OCR1A6 Output Compare Register A Bit 6 RW 0 OCR1A5 Output Compare Register A Bit 5 RW 0 OCR1A4 Output Compare Register A Bit 4 RW 0 OCR1A3 Output Compare Register A Bit 3 RW 0 OCR1A2 Output Compare Register A Bit 2 RW 0 OCR1A1 Output Compare Register A Bit 1 RW 0 OCR1A0 Output Compare Register A Bit 0 RW 0 OCR1B Output Compare Register The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT1). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC2 pin. $2C $4C io_timer.bmp N OCR1B7 Output Compare Register B Bit 7 RW 0 OCR1B6 Output Compare Register B Bit 6 RW 0 OCR1B5 Output Compare Register B Bit 5 RW 0 OCR1B4 Output Compare Register B Bit 4 RW 0 OCR1B3 Output Compare Register B Bit 3 RW 0 OCR1B2 Output Compare Register B Bit 2 RW 0 OCR1B1 Output Compare Register B Bit 1 RW 0 OCR1B0 Output Compare Register B Bit 0 RW 0 OCR1C Output Compare Register The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT1). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC2 pin. $2B $4B io_timer.bmp N OCR1C7 Output Compare Register C Bit 7 RW 0 OCR1C6 Output Compare Register C Bit 6 RW 0 OCR1C5 Output Compare Register C Bit 5 RW 0 OCR1C4 Output Compare Register C Bit 4 RW 0 OCR1C3 Output Compare Register C Bit 3 RW 0 OCR1C2 Output Compare Register C Bit 2 RW 0 OCR1C1 Output Compare Register C Bit 1 RW 0 OCR1C0 Output Compare Register C Bit 0 RW 0 TIMSK Timer/Counter Interrupt Mask Register $39 $59 io_flag.bmp Y OCIE1A Timer/Counter1 Output Compare Interrupt Enable When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Compare MatchA, interrupt is enabled. The corresponding interrupt at vector $003 is executed if a compare matchA occurs. The Compare Flag in Timer/Counter1 is set (one) in the Timer/Counter Interrupt Flag Register. RW 0 OCIE1B Timer/Counter1 Output Compare Interrupt Enable When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Compare MatchB, interrupt is enabled. The corresponding interrupt at vector $004 is executed if a compare matchB occurs. The Compare Flag in Timer/Counter1 is set (one) in the Timer/Counter Interrupt Flag Register. RW 0 TOIE1 Timer/Counter1 Overflow Interrupt Enable When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $004) is executed if an overflow in Timer/Counter1 occurs (i.e., when the TOV1 bit is set in the Timer/Counter Interrupt Flag Register [TIFR]). RW 0 TIFR Timer/Counter Interrupt Flag Register $38 $58 io_flag.bmp Y OCF1A Timer/Counter1 Output Compare Flag 1A The OCF1A bit is set (one) when compare match occurs between Timer/Counter1 and the data value in OCR1A (Output Compare Register 1A). OCF1A is cleared by hard-ware when executing the corresponding interrupt handling vector. Alternatively, OCF1A is cleared by writing a logical “1” to the flag. When the I-bit in SREG, OCIE1A, and OCF1A are set (one), the Timer/Counter1 compare match A interrupt is executed. RW 0 OCF1B Timer/Counter1 Output Compare Flag 1B The OCF1B bit is set (one) when compare match occurs between Timer/Counter1 and the data value in OCR1B – Output Compare Register 1A. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF1B is cleared, after synchronization clock cycle, by writing a logic one to the flag. When the I-bit in SREG, OCIE1B, and OCF1B are set (one), the Timer/Counter1 B compare match interrupt is executed. RW 0 TOV1 Timer/Counter1 Overflow Flag The bit TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logical “1” to the flag. When the SREG I-bit, TOIE1 (Timer/Counter1 Overf low Interrupt Enable) and TOV1 are set (one), the Timer/Counter1 Overflow interrupt is executed. RW 0 PLLCSR PLL Control and Status Register $29 $49 io_sreg.bmp Y PCKE PCK Enable RW 0 PLLE PLL Enable RW 0 PLOCK PLL Lock Detector R 0 [GIMSK:GIFR] io_ext.bmp GIMSK General Interrupt Mask Register $3B $5B io_flag.bmp Y INT0 External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from program memory address $001. See also “External Interrupts.” • Bits 5..0 - Res: Reserved bits RW 0 PCIE1 Pin Change Interrupt Enable 1 RW 0 PCIE0 Pin Change Interrupt Enable 0 RW 0 GIFR General Interrupt Flag register $3A $5A io_flag.bmp Y INTF0 External Interrupt Flag 0 When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the interrupt vector at address $001. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. RW 0 PCIF Pin Change Interrupt Flag RW 0 [ICE50:SIMULATOR:STK500:STK500_2:AVRISPmkII] 0x05 0x0F 0x0F 0x0F 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x0F 0x0F 0x0F 0x15 0x14 0x14 0x000000DF 0x00000000 0x00000000 0x00000000 0x0000007F 0x000007FF 0x000003FF 0x000003FF 0x000003FF 0x000003FF 0x000000DF 0x0000FFFF 0x0000007F 0x00000000 0x00000000 0x00000000 0x0023FFFF 0x00000FFF 0x00000060 0x00000000 0x00000000 0x00000000 0x00000000 0x0000007F 0x000007FF 0x000003FF 0x000003FF 0x000003FF 0x000003FF 0x000000DF 0x0000FFFF 0x0000007F 0x00000000 0x00000000 0x00000000 0x0023FFFF 0x00000FFF 0x00000060 0x00000000 0x00000000 0x00000000 0x00000000 0x0000007F 0x000007FF 0x000003FF 0x000003FF 0x000003FF 0x000003FF 0x000000DF 0x0000FFFF 0x0000007F 0x00000000 0x00000000 0x00000000 0x0023FFFF 0x00000FFF 0x000000000 0x00 0x00 0x00 0x00 0xF7 0xE1 0xff 0x51 0xc7 ATtiny26.bin 0x02 0x00 1000000 40000000 7 2 ; INTOSC = 1, INTRC=2;EXTCLK=4 1 ;NOTUSE = 1, EXTERNAL = 4, INTERNAL = 2 1 0 0x00 0x01 0x01 0x02 0x80E8 0x00000031 0x00000000 258 CK, 4.1 ms 0x00000031 0x00000010 258 CK, 65 ms 0x00000031 0x00000020 1K CK 0x00000031 0x00000030 1K CK, 4.1 ms 0x00000031 0x00000001 1K CK, 65 ms 0x00000031 0x00000011 16K CK 0x00000031 0x00000021 16K CK, 4.1 ms 0x00000031 0x00000031 16K CK, 65 ms 0x00000030 0x00000000 6 CK 0x00000030 0x00000010 6 CK, 4.1 ms 0x00000030 0x00000020 6 CK, 65 ms 0x00000030 0x00000000 6 CK 0x00000030 0x00000010 6 CK, 4.1 ms 0x00000030 0x00000020 6 CK, 65 ms 0x00000030 0x00000000 1K CK 0x00000030 0x00000010 1K CK, 4.1 ms 0x00000030 0x00000020 1K CK, 65 ms 0x00000030 0x00000030 16K CK 0x000000ff 0x000000Ab 0x000000ff 0x000000E1 1.0 0x000000ff 0x000000E2 2.0 0x000000ff 0x000000E3 4.0 0x000000ff 0x000000E4 8.0 0x000000ff 0x000000E0 0x000000ff 0x00000020 0x00001000 0x00000000 RSTDSBL Fuse 0x00001000 0x00001000 RSTDSBL Fuse 0x00000300 0x00000300 BOD disabled 0x00000300 0x00000200 BOD enabled, 2.7 V 0x00000300 0x00000000 BOD enabled, 4.0 V AVRSimCoreV2.SimCoreV2 AVRSimMemory8bit.SimMemory8bit AVRSimInterrupt.SimInterrupt 0x09 0 9 AVRSimIOPort.SimIOPort N AVRSimIOPort.SimIOPort N AVRSimIOExtInterrupt.SimIOExtInterrupt 0x01 0x3B 0x0x40 0x3A 0x40 0x16 0x40 0x35 0x03 AVRSimIOPinChangeT26.SimIOPinChangeT26 0x02 0x3B 0x10 0x20 0x3A 0x20 0x10 0x16 0xf0 0x19 0xc8 0x16 0x0f AVRSimIOTimert81.SimIOTimert81 0x06 0x16 0x40 AVRSimIOTimer8pll_OCABC.SimIOTimer8pll_OCABC 0x03 0x04 0x05 0x16 0x17 0x02 0x08 0x01 0x04 AVRSimAC.SimIOAC 0x0A AvrSimADC.SimADC 0x0B AvrSimUSI.SimUSI 0x08 0x07 0xff 0xff 0xff 0xff 0x21 1 1 1 0xFF 0xFF 0xFF 0 1 2001002532030x53111000x2116100x400x4C0x200xFF0x000x0464100xC00x000xA00xFF0xFF25625644440xC4 0xE4 0xC4 0xE4 0xCC 0xEC 0xCC 0xEC 0xD4 0xF4 0xD4 0xF4 0xDC 0xFC 0xDC 0xFC 0xC8 0xE8 0xD8 0xF8 0x4C 0x6C 0x5C 0x7C 0xEC 0xBC 0x00 0x06 0x00 0x00 0x00 0x001000511520151501050x0B25625650x052562560505