[ADMIN:CORE:INTERRUPT_VECTOR:MEMORY:PACKAGE:FUSE:LOCKBIT:PROGRAMMING:IO_MODULE:ICE_SETTINGS]ATtiny2616MHZ235RELEASED$1E$91$09V1AVRSimCoreV1.SimCoreV1[lpm rd,z][][0x0023:0x0034:0x0054]32$00$1B$1A$1D$1C$1F$1E12$000External Reset, Power-on Reset and Watchdog Reset$001External Interrupt 0$002External Interrupt Request 0$003Timer/Counter1 Compare Match 1A$004Timer/Counter1 Compare Match 1B$005Timer/Counter1 Overflow$006Timer/Counter0 Overflow$007USI Start$008USI Overflow$009EEPROM Ready$00AAnalog Comparator$00BADC Conversion CompleteAVRSimMemory8bit.SimMemory8bit2048128128$600NA$00$3FNANA$20$5F$3F$5F0x010x020x040x080x100x200x400x80$3D$5D0x010x020x040x080x100x200x400x80$3B$5B0x100x200x40$3A$5A0x200x40$39$590x020x040x200x40$38$580x020x040x200x40$35$550x010x020x080x100x200x40$34$540x010x020x040x08$33$530x010x020x040x08$32$520x010x020x040x080x100x200x400x80$31$510x010x020x040x080x100x200x400x80$30$500x010x020x040x080x100x200x400x80$2F$4F0x010x020x040x080x400x80$2E$4E0x010x020x040x080x100x200x400x80$2D$4D0x010x020x040x080x100x200x400x80$2C$4C0x010x020x040x080x100x200x400x80$2B$4B0x010x020x040x080x100x200x400x80$29$490x010x020x04$21$410x010x020x040x080x10$1E$3E0x010x020x040x080x100x200x40$1D$3D0x010x020x040x080x100x200x400x80$1C$3C0x010x020x040x08$1B$3B0x010x020x040x080x100x200x400x80$1A$3A0x010x020x040x080x100x200x400x80$19$390x010x020x040x080x100x200x400x80$18$380x010x020x040x080x100x200x400x80$17$370x010x020x040x080x100x200x400x80$16$360x010x020x040x080x100x200x400x80$0F$2F0x010x020x040x080x100x200x400x80$0E$2E0x010x020x040x080x100x200x400x80$0D$2D0x010x020x040x080x100x200x400x80$08$280x010x020x040x080x100x200x400x80$07$270x010x020x040x080x100x200x400x80$06$260x010x020x040x080x100x200x400x80$05$250x010x020x040x080x100x200x400x80$04$240x010x020x040x080x100x200x400x80[PDIP:SOIC]20[MOSI:DI:SDA:'OC1A:PCINT0:PB0]DI: Data input in USI 3-wire mode. USI 3-wire mode does not override normal port functions., so pin must be configure as an input. SDA: Serial data in USI 2-wire mode. Serial data pin is bi-directional and uses open-col-lector output. The SDA pin is enabled by setting the pin as an output. The pin is pulled low when the PORTB0 or USI shiftregister is zero when DDB0 is set (one). Pull-up is disabled in USI 2-wire mode. OC1A: Inverted Timer/Counter1 PWM Output A: The PB0 pin can serve as an Inverted output for the PWM mode if not used in programming or USI. The PB0 pin has to be configured as an output (DDB0 set (one)) to serve this function. For further reading on PCINT0 please refer to the manual[MISO:DO:OC1A:PCINT0:PB1]DO: Data output in USI 3-wire mode. Data output (DO) overrides PORTB1 value and it is driven to the port when the data direction bit DDB1 is set (one). However the PORTB1 bit still controls the pullup, enabling pullup if direction is input and PORTB1 is set(one). OC1A: Output compare match output: The PB1 pin can serve as an output for the Timer/Counter1 compare match A. The PB1 pin has to be configured as an output (DDB3 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM mode timer function if not used in programming or USI. PCINT0: Pin Change Interrupt 0 pin. Pin change interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate functions do not mask the interrupt. The masking alternate functions are the output compare match out-put OC1A and data output DO in USI 3-wire mode. Digital input is enabled on pin PB4 also in SLEEP modes, if the pin change interrupt is enabled and not masked by the alternate function[SCK:SCL:'OC1B:PCINT0:PB2]SCK: Clock input or output in USI 3-wire mode. When the SPI is enabled this pin is con-figured[OC1B:PCINT0:PB3]OC1B: Output compare match output: The PB3 pin can serve as an output for the Timer/Counter1 compare match B. The PB3 pin has to be configured as an output (DDB3 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM mode. PCINT0: Pin Change Interrupt 0 pin. Pin change interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate functions do not mask the interrupt. The masking alternate function is the output compare match output OC1B. Digital input is enabled on pin PB3 also in SLEEP modes, if the pin change interrupt is enabled and not masked by the alternate function[VCC][GND][ADC7:XTAL1:PCINT1:PB4]ADC7: ADC input channel 7. Configure the port pins as inputs with the internal pull-ups switched off to avoid the digital port function from interfering with the function of the ana-log to digital converter. XTAL1: Chip clock oscillator pin 1. Used for all chip clock sources except internal cali-brateble RC oscillator and PLL clock. When used as a clock pin, the pin can not be used as an I/O pin. When using internal calibratable RC oscillator or PLL clock as chip clock sources, PB4 serves as an ordinary I/O pin. PCINT1: Pin Change Interrupt 1 pin. Pin change interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate functions do not mask the interrupt. The masking alternate functions are the XTAL1 inputs. Digital input is enabled on pin PB4 also in SLEEP modes, if the pin change interrupt is enabled and not masked by the alternate functions[ADC8:XTAL2:PCINT1:PB5]ADC8: ADC input channel 8. Configure the port pins as inputs with the internal pull-ups switched off to avoid the digital port function from interfering with the function of the ana-log to digital converter. XTAL2: Chip clock oscillator pin 2. Used as clock pin for all chip clock sources except internal calibrateble RC oscillator, external clock and PLL clock. When used as a clock pin, the pin can not be used as an I/O pin. When using internal calibratable RC oscillator, external clock or PLL clock as chip clock sources, PB5 serves as an ordinary I/O pin. PCINT1: Pin Change Interrupt 1 pin. Pin change interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate functions do not mask the interrupt. The masking alternate functions are the XTAL2 outputs. Digital input is enabled on pin PB5 also in SLEEP modes, if the pin change interrupt is enabled and not masked by the alternate function[ADC9:INT0:T0:PCINT1:PB6]ADC9: ADC input channel 9. Configure the port pins as inputs with the internal pull-ups switched off to avoid the digital port function from interfering with the function of the analog to digital converter. INT0: External Interrupt source 0: The PB6 pin can serve as an external interrupt source enabled by setting (one) the bit INT0 in the general input mask register (GIMSK). T0: Timer/Counter0 External Counter Clock Input is enabled by setting (one) the bits CS02 and CS01 in the Timer/Counter0 control register (TCCR0). PCINT1: Pin Change Interrupt 1 pin. Pin change interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate functions do not mask the interrupt. The masking alternate functions are the external low level Interrupt source 0 (INT0) and the Timer/Counter0 external counter clock input (T0). Digital input is enabled on pin PB6 also in SLEEP modes, if the pin change interrupt is enabled and not masked by the alternate functio[ADC10:'RESET:PCINT1:PB7]ADC10: ADC input channel 10. Configure the port pins as inputs with the internal pull-ups switched off to avoid the digital port function from interfering with the function of the analog to digital converter. RESET: External Reset Input is active low and enabled by unprogramming (“1”) the RSTDISBL fuse. Pullup is activated and output driver and digital input are deactivated when the pin is used as the RESET pin. PCINT1: Pin Change Interrupt 1 pin. Pin change interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate function do not mask the interrupt. The masking alternate function is the pin usage as RESET. Digital input is enabled on pin PB7 also in SLEEP modes, if the pin change interrupt is enabled and not masked by the alternate functi[ADC6:AIN1:PA7]AIN1: Analog Comparator Negative Input and ADC6: ADC input channel 6. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the analog comparator or analog to digital converter. PCINT1: Pin Change Interrupt 1 pin. Pin change interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate function do not mask the interrupt. The masking alternate function is the analog comparator.Digital input is enabled on pin PA7 also in SLEEP modes, if the pin change interrupt is enabled and not masked by the alternate functio[ADC5:AIN0:PA6]AIN0: Analog Comparator Positive Input and ADC5: ADC input channel 5. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the analog comparator or analog to digital converter. PCINT1: Pin Change Interrupt 1 pin. Pin change interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate function do not mask the interrupt. The masking alternate function is the analog comparator.Digital input is enabled on pin PA6 also in SLEEP modes, if the pin change interrupt is enabled and not masked by the alternate functio[ADC4:PA5]ADC4/ADC3: ADC input channel 4 and 3. Configure the port pins as inputs with the internal pull-ups switched off to avoid the digital port function from interfering with the function of the analog to digital converter.[ADC3:PA4]ADC4/ADC3: ADC input channel 4 and 3. Configure the port pins as inputs with the internal pull-ups switched off to avoid the digital port function from interfering with the function of the analog to digital converter.[AVCC][AGND][AREF:PA3]AREF: External reference for ADC. Pullup and output driver are disabled on PA3 when the pin is used as an external reference or Internal Voltage Reference (2.56V) with external capacitor at the AREF pin by setting (one) the bit REFS0 in the ADC Multiplexer Selection Register (ADMUX). PCINT1: Pin Change Interrupt 1 pin. Pin change interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate function do not mask the interrupt. The masking alternate function is the pin usage as an analog refer-ence for the ADC. Digital input is enabled on pin PA3 also in SLEEP modes, if the pin change interrupt is enabled and not masked by the alternate function. Please refer to the manual for further details[ADC2:PA2][ADC1:PA1][ADC0:PA0][LOW:HIGH]8PLLCKUse PLL for internal clock1CKOPTOscillator options1SUT1Select start-up time1SUT0Select start-up time1CKSEL3Select Clock Source1CKSEL2Select Clock Source0CKSEL1Select Clock Source0CKSEL0Select Clock Source1630x400x00CKOPT fuse (operation dependent of CKSEL fuses); [CKOPT=0]0xBF0x01PLL Clock; Start-up time: 1K CK + 0 ms; [CKSEL=0001 SUT=00]0xBF0x11PLL Clock; Start-up time: 1K CK + 4 ms; [CKSEL=0001 SUT=01]0xBF0x21PLL Clock; Start-up time: 1K CK + 64 ms; [CKSEL=0001 SUT=10]0xBF0x31PLL Clock; Start-up time: 16K CK + 64 ms; [CKSEL=0001 SUT=11]0xBF0x80Ext. Clock; Start-up time: 6 CK + 0 ms; [CKSEL=0000 SUT=00]0xBF0x90Ext. Clock; Start-up time: 6 CK + 4 ms; [CKSEL=0000 SUT=01]0xBF0xA0Ext. Clock; Start-up time: 6 CK + 64 ms; [CKSEL=0000 SUT=10]0xBF0x81Int. RC Osc. 1 MHz; Start-up time: 6 CK + 0 ms; [CKSEL=0001 SUT=00]0xBF0x91Int. RC Osc. 1 MHz; Start-up time: 6 CK + 4 ms; [CKSEL=0001 SUT=01]0xBF0xA1Int. RC Osc. 1 MHz; Start-up time: 6 CK + 64 ms; [CKSEL=0001 SUT=10]; default value0xBF0x82Int. RC Osc. 2 MHz; Start-up time: 6 CK + 0 ms; [CKSEL=0010 SUT=00]0xBF0x92Int. RC Osc. 2 MHz; Start-up time: 6 CK + 4 ms; [CKSEL=0010 SUT=01]0xBF0xA2Int. RC Osc. 2 MHz; Start-up time: 6 CK + 64 ms; [CKSEL=0010 SUT=10]0xBF0x83Int. RC Osc. 4 MHz; Start-up time: 6 CK + 0 ms; [CKSEL=0011 SUT=00]0xBF0x93Int. RC Osc. 4 MHz; Start-up time: 6 CK + 4 ms; [CKSEL=0011 SUT=01]0xBF0xA3Int. RC Osc. 4 MHz; Start-up time: 6 CK + 64 ms; [CKSEL=0011 SUT=10]0xBF0x84Int. RC Osc. 8 MHz; Start-up time: 6 CK + 0 ms; [CKSEL=0100 SUT=00]0xBF0x94Int. RC Osc. 8 MHz; Start-up time: 6 CK + 4 ms; [CKSEL=0100 SUT=01]0xBF0xA4Int. RC Osc. 8 MHz; Start-up time: 6 CK + 64 ms; [CKSEL=0100 SUT=10]0xBF0x85Ext. RC Osc. - 0.9 MHz; Start-up time: 18 CK + 0 ms; [CKSEL=0101 SUT=00]0xBF0x95Ext. RC Osc. - 0.9 MHz; Start-up time: 18 CK + 4 ms; [CKSEL=0101 SUT=01]0xBF0xA5Ext. RC Osc. - 0.9 MHz; Start-up time: 18 CK + 64 ms; [CKSEL=0101 SUT=10]0xBF0xB5Ext. RC Osc. - 0.9 MHz; Start-up time: 6 CK + 4 ms; [CKSEL=0101 SUT=11]0xBF0x86Ext. RC Osc. 0.9 MHz - 3.0 MHz; Start-up time: 18 CK + 0 ms; [CKSEL=0110 SUT=00]0xBF0x96Ext. RC Osc. 0.9 MHz - 3.0 MHz; Start-up time: 18 CK + 4 ms; [CKSEL=0110 SUT=01]0xBF0xA6Ext. RC Osc. 0.9 MHz - 3.0 MHz; Start-up time: 18 CK + 64 ms; [CKSEL=0110 SUT=10]0xBF0xB6Ext. RC Osc. 0.9 MHz - 3.0 MHz; Start-up time: 6 CK + 4 ms; [CKSEL=0110 SUT=11]0xBF0x87Ext. RC Osc. 3.0 MHz - 8.0 MHz; Start-up time: 18 CK + 0 ms; [CKSEL=0111 SUT=00]0xBF0x97Ext. RC Osc. 3.0 MHz - 8.0 MHz; Start-up time: 18 CK + 4 ms; [CKSEL=0111 SUT=01]0xBF0xA7Ext. RC Osc. 3.0 MHz - 8.0 MHz; Start-up time: 18 CK + 64 ms; [CKSEL=0111 SUT=10]0xBF0xB7Ext. RC Osc. 3.0 MHz - 8.0 MHz; Start-up time: 6 CK + 4 ms; [CKSEL=0111 SUT=11]0xBF0x88Ext. RC Osc. 8.0 MHz - 12.0 MHz; Start-up time: 18 CK + 0 ms; [CKSEL=1000 SUT=00]0xBF0x98Ext. RC Osc. 8.0 MHz - 12.0 MHz; Start-up time: 18 CK + 4 ms; [CKSEL=1000 SUT=01]0xBF0xA8Ext. RC Osc. 8.0 MHz - 12.0 MHz; Start-up time: 18 CK + 64 ms; [CKSEL=1000 SUT=10]0xBF0xB8Ext. RC Osc. 8.0 MHz - 12.0 MHz; Start-up time: 6 CK + 4 ms; [CKSEL=1000 SUT=11]0xBF0x89Ext. Low-Freq. Crystal; Start-up time: 1K CK + 4 ms; [CKSEL=1001 SUT=00]0xBF0x99Ext. Low-Freq. Crystal; Start-up time: 1K CK + 64 ms; [CKSEL=1001 SUT=01]0xBF0xA9Ext. Low-Freq. Crystal; Start-up time: 32K CK + 64 ms; [CKSEL=1001 SUT=10]0xBF0x8AExt. Crystal/Resonator Low Freq.; Start-up time: 258 CK + 4 ms; [CKSEL=1010 SUT=00]0xBF0x9AExt. Crystal/Resonator Low Freq.; Start-up time: 258 CK + 64 ms; [CKSEL=1010 SUT=01]0xBF0xAAExt. Crystal/Resonator Low Freq.; Start-up time: 1K CK + 0 ms; [CKSEL=1010 SUT=10]0xBF0xBAExt. Crystal/Resonator Low Freq.; Start-up time: 1K CK + 4 ms; [CKSEL=1010 SUT=11]0xBF0x8BExt. Crystal/Resonator Low Freq.; Start-up time: 1K CK + 64 ms; [CKSEL=1011 SUT=00]0xBF0x9BExt. Crystal/Resonator Low Freq.; Start-up time: 16K CK + 0 ms; [CKSEL=1011 SUT=01]0xBF0xABExt. Crystal/Resonator Low Freq.; Start-up time: 16K CK + 4 ms; [CKSEL=1011 SUT=10]0xBF0xBBExt. Crystal/Resonator Low Freq.; Start-up time: 16K CK + 64 ms; [CKSEL=1011 SUT=11]0xBF0x8CExt. Crystal/Resonator Medium Freq.; Start-up time: 258 CK + 4 ms; [CKSEL=1100 SUT=00]0xBF0x9CExt. Crystal/Resonator Medium Freq.; Start-up time: 258 CK + 64 ms; [CKSEL=1100 SUT=01]0xBF0xACExt. Crystal/Resonator Medium Freq.; Start-up time: 1K CK + 0 ms; [CKSEL=1100 SUT=10]0xBF0xBCExt. Crystal/Resonator Medium Freq.; Start-up time: 1K CK + 4 ms; [CKSEL=1100 SUT=11]0xBF0x8DExt. Crystal/Resonator Medium Freq.; Start-up time: 1K CK + 64 ms; [CKSEL=1101 SUT=00]0xBF0x9DExt. Crystal/Resonator Medium Freq.; Start-up time: 16K CK + 0 ms; [CKSEL=1101 SUT=01]0xBF0xADExt. Crystal/Resonator Medium Freq.; Start-up time: 16K CK + 4 ms; [CKSEL=1101 SUT=10]0xBF0xBDExt. Crystal/Resonator Medium Freq.; Start-up time: 16K CK + 64 ms; [CKSEL=1101 SUT=11]0xBF0x8EExt. Crystal/Resonator High Freq.; Start-up time: 258 CK + 4 ms; [CKSEL=1110 SUT=00]0xBF0x9EExt. Crystal/Resonator High Freq.; Start-up time: 258 CK + 64 ms; [CKSEL=1110 SUT=01]0xBF0xAEExt. Crystal/Resonator High Freq.; Start-up time: 1K CK + 0 ms; [CKSEL=1110 SUT=10]0xBF0xBEExt. Crystal/Resonator High Freq.; Start-up time: 1K CK + 4 ms; [CKSEL=1110 SUT=11]0xBF0x8FExt. Crystal/Resonator High Freq.; Start-up time: 1K CK + 64 ms; [CKSEL=1111 SUT=00]0xBF0x9FExt. Crystal/Resonator High Freq.; Start-up time: 16K CK + 0 ms; [CKSEL=1111 SUT=01]0xBF0xAFExt. Crystal/Resonator High Freq.; Start-up time: 16K CK + 4 ms; [CKSEL=1111 SUT=10]0xBF0xBFExt. Crystal/Resonator High Freq.; Start-up time: 16K CK + 64 ms; [CKSEL=1111 SUT=11]5RSTDISBLSelect if PB/ is I/O pin or RESET pin1SPIENEnable Serial Program and Data Downloading0EESAVEEEPROM memory is preserved through the Chip Erase1BODLEVELBrown out detector trigger level1BODENBrown out detector enable160x100x00Reset Disabled (Enable PB7 as i/o pin); [RSTDISBL=0]0x080x00Serial program downloading (SPI) enabled; [SPIEN=0]0x040x00Preserve EEPROM memory through the Chip Erase cycle; [EESAVE=0]0x020x00Brown-out detection level at VCC=4.0 V; [BODLEVEL=0]0x020x02Brown-out detection level at VCC=2.7 V; [BODLEVEL=1]0x010x00Brown-out detection enabled; [BODEN=0][LB1 = 1 : LB2 = 1] No memory lock features enabled. [LB1 = 0 : LB2 = 1] Further programming of Flash and EEPROM is enabled. [LB1 = 0 : LB2 = 0] Same as previous, but verify is also disabled320x030x03Mode 1: No memory lock features enabled0x030x02Mode 2: Further programming disabled0x030x00Mode 3: Further programming and verification disabledLB1LockbitLB2Lockbit0xff,0xf71,0x08,0x08,WARNING! These fuse settings will disable the ISP interface!1,0x10,0x00,WARNING! Disabling external reset will make the ISP interface inaccessible!1,0x08,0x08,WARNING! These fuse settings will disable the ISP interface!1,0x10,0x00,WARNING! Disabling external reset will make the ISP interface inaccessible!0x00,1.0 MHz0x01,2.0 MHz0x02,4.0 MHz0x03,8.0 MHz324[AD_CONVERTER:ANALOG_COMPARATOR:USI:PORTA:PORTB:EEPROM:WATCHDOG:CPU:TIMER_COUNTER_0:TIMER_COUNTER_1:EXTERNAL_INTERRUPT][ADMUX:ADCSR:ADCH:ADCL]((IF ADMUX.ADLAR = 1) LINK [ADCH(1:0):ADCL(7:0)]); (IF ADMUX.ADLAR = 0) LINK [ADCH(7:0):ADCL(7:6)]);io_analo.bmpAD Converter Feature list: 10-bit Resolution. 0.5 LSB Integral Non-Linearity. +-2 LSB Absolute Accuracy. TBD - 260 µs Conversion Time. Up to TBD kSPS at maximum resolution. 8 Multiplexed Single Ended Input Channels. 7 Differential input channels (TQFP package only). 2 Differential input channels with optional gain of 10x and 200x (TQFP package only). Optional left adjustment for ADC result readout. 0 - VCC ADC Input Voltage Range. Selectable 2.56 V ADC reference voltage. Free Running or Single Conversion Mode. Interrupt on ADC Conversion Complete. Sleep Mode NoiseADMUXThe ADC multiplexer Selection Register$07$27io_analo.bmpYREFS1Reference Selection Bit 1These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin.RW0REFS0Reference Selection Bit 0These bits select the voltage reference for the ADC, as shown in Table 91. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). If differential channels are used, the selected reference should not be closer to AV CC than indicated in Table 94 on page 200. The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin.RW0ADLARLeft Adjust ResultThe ADLAR bit affects the presentation of the ADC conversion result in the ADC data register. If ADLAR is cleared, the result is right adjusted. If ADLAR is set, the result is left adjusted. Changing the ADLAR bit will affect the ADC data register immediately, regardless of any ongoing conversions. For a complete description of this bit, see “The ADC Data Register -ADCL and ADCH” on page 198. RW0MUX4Analog Channel and Gain Selection BitsThe value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).RW0MUX3Analog Channel and Gain Selection BitsThe value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).RW0MUX2Analog Channel and Gain Selection BitsThe value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).RW0MUX1Analog Channel and Gain Selection BitsThe value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).RW0MUX0Analog Channel and Gain Selection BitsThe value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 92 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set).RW0ADCSRADCSRAThe ADC Control and Status register$06$26io_flag.bmpYADENADC EnableWriting a logical ‘1’ to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.RW0ADSCADC Start ConversionIn Single Conversion Mode, a logical ‘1’ must be written to this bit to start each conversion. In Free Running Mode, a logical ‘1’ must be written to this bit to start the first conversion. The first time ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, an extended conversion will result. This extended conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. When a dummy conversion precedes a real conversion, ADSC will stay high until the real conversion completes. Writing a 0 to this bit has no effectRW0ADFRADC Free Running SelectWhen this bit is set (one) the ADC operates in Free Running Mode. In this mode, the ADC samples and updates the data registers continuously. Clearing this bit (zero) will terminate Free Running Mode.RW0ADIFADC Interrupt FlagThis bit is set (one) when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set (one). ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a read-modify-write on ADCSR, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used.RW0ADIEADC Interrupt EnableWhen this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Complete Interrupt is activated.RW0ADPS2ADC Prescaler Select BitsThese bits determine the division factor between the XTAL frequency and the input clock to the ADC.RW0ADPS1ADC Prescaler Select BitsThese bits determine the division factor between the XTAL frequency and the input clock to the ADC.RW0ADPS0ADC Prescaler Select BitsThese bits determine the division factor between the XTAL frequency and the input clock to the ADC.RW0ADCHADC Data Register High ByteWhen an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. The selected channel is differential if MUX4..0 are between ‘01000’ and ‘11101’, otherwise the selected channel is single ended. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8 bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUX4..0 bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adju$05$25io_analo.bmpNADCH7ADC Data Register High Byte Bit 7RW0ADCH6ADC Data Register High Byte Bit 6RW0ADCH5ADC Data Register High Byte Bit 5RW0ADCH4ADC Data Register High Byte Bit 4RW0ADCH3ADC Data Register High Byte Bit 3RW0ADCH2ADC Data Register High Byte Bit 2RW0ADCH1ADC Data Register High Byte Bit 1RW0ADCH0ADC Data Register High Byte Bit 0RW0ADCLADC Data Register Low ByteWhen an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. The selected channel is differential if MUX4..0 are between ‘01000’ and ‘11101’, otherwise the selected channel is single ended. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8 bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUX4..0 bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right ad$04$24io_analo.bmpNADCL7ADC Data Register Low Byte Bit 7RW0ADCL6ADC Data Register Low Byte Bit 6RW0ADCL5ADC Data Register Low Byte Bit 5RW0ADCL4ADC Data Register Low Byte Bit 4RW0ADCL3ADC Data Register Low Byte Bit 3RW0ADCL2ADC Data Register Low Byte Bit 2RW0ADCL1ADC Data Register Low Byte Bit 1RW0ADCL0ADC Data Register Low Byte Bit 0RW0[ACSR]io_analo.bmpAlgComp_06ACSRAnalog Comparator Control And Status Register$08$28io_analo.bmpYACDAnalog Comparator DisableWhen this bit is written logic one, the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.RW0ACBGAnalog Comparator Bandgap SelectWhen this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. See “Internal Voltage Reference” on page 42.RW0ACOAnalog Compare OutputThe output of the analog comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1-2 clock cycles.RNAACIAnalog Comparator Interrupt FlagThis bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hard-ware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.RW0ACIEAnalog Comparator Interrupt EnableWhen the ACIE bit is written logic one and the I-bit in the Status Register is set, the analog comparator interrupt is acti-vated. When written logic zero, the interrupt is disabled.RW0ACMEAnalog Comparator Multiplexer EnableWhen the ACME bit is set (one) and the ADC is switched off (ADEN in ADCSR is zero), MUX3...0 in ADMUX select the input pin to replace the negative input to the Analog Comparator, as shown in the table in the datasheet. If ACME is cleared (zero) or ADEN is set (one), PA7(AIN1) is applied to the negative input to the Analog Comparator.RW0ACIS1Analog Comparator Interrupt Mode Select bit 1These bits determine which comparator events that trigger the Analog Comparator interrupt.RW0ACIS0Analog Comparator Interrupt Mode Select bit 0These bits determine which comparator events that trigger the Analog Comparator interrupt.RW0[USIDR:USISR:USICR]io_com.bmpUniversal Serial InterfaceUSIDRUSI Data Register$0F$2Fio_com.bmpNUSIDR7USI Data Register bit 7RW0USIDR6USI Data Register bit 6RW0USIDR5USI Data Register bit 5RW0USIDR4USI Data Register bit 4RW0USIDR3USI Data Register bit 3RW0USIDR2USI Data Register bit 2RW0USIDR1USI Data Register bit 1RW0USIDR0USI Data Register bit 0RW0USISRUSI Status Register$0E$2Eio_flag.bmpYUSISIFStart Condition Interrupt FlagRW0USIOIFCounter Overflow Interrupt FlagRW0USIPFStop Condition FlagRW1USIDCData Output CollisionRW0USICNT3USI Counter Value Bit 3RW0USICNT2USI Counter Value Bit 2RW0USICNT1USI Counter Value Bit 1RW0USICNT0USI Counter Value Bit 0RW0USICRUSI Control Register$0D$2Dio_flag.bmpYUSISIEStart Condition Interrupt EnableRW0USIOIECounter Overflow Interrupt EnableRW0USIWM1USI Wire Mode Bit 1RW1USIWM0USI Wire Mode Bit 0RW0USICS1USI Clock Source Select Bit 1RW0USICS0USI Clock Source Select Bit 0RW0USICLKClock StrobeR0USITCToggle Clock Port PinW0[PORTA:DDRA:PINA]io_port.bmpAVRSimIOPort.SimIOPortPORTAPort A Data Register$1B$3Bio_port.bmpNPORTA7Port A Data Register bit 7RW0PORTA6Port A Data Register bit 6RW0PORTA5Port A Data Register bit 5RW0PORTA4Port A Data Register bit 4RW0PORTA3Port A Data Register bit 3RW0PORTA2Port A Data Register bit 2RW0PORTA1Port A Data Register bit 1RW0PORTA0Port A Data Register bit 0RW0DDRAPort A Data Direction Register$1A$3Aio_flag.bmpNDDA7Data Direction Register, Port A, bit 7RW0DDA6Data Direction Register, Port A, bit 6RW0DDA5Data Direction Register, Port A, bit 5RW0DDA4Data Direction Register, Port A, bit 4RW0DDA3Data Direction Register, Port A, bit 3RW0DDA2Data Direction Register, Port A, bit 2RW0DDA1Data Direction Register, Port A, bit 1RW0DDA0Data Direction Register, Port A, bit 0RW0PINAPort A Input PinsThe Port A Input Pins address - PINA - is not a register, and this address enables access to the physical value on each Port A pin. When reading PORTA the Port A Data Latch is read, and when reading PINA, the logical values present on the pins are read.$19$39io_port.bmpNPINA7Input Pins, Port A bit 7RWHi-ZPINA6Input Pins, Port A bit 6RWHi-ZPINA5Input Pins, Port A bit 5RWHi-ZPINA4Input Pins, Port A bit 4RWHi-ZPINA3Input Pins, Port A bit 3RWHi-ZPINA2Input Pins, Port A bit 2RWHi-ZPINA1Input Pins, Port A bit 1RWHi-ZPINA0Input Pins, Port A bit 0RWHi-Z[PORTB:DDRB:PINB]io_port.bmpAVRSimIOPort.SimIOPortPORTBPort B Data Register$18$38io_port.bmpNPORTB7Port B Data Register bit 7RW0PORTB6Port B Data Register bit 6RW0PORTB5Port B Data Register bit 5RW0PORTB4Port B Data Register bit 4RW0PORTB3Port B Data Register bit 3RW0PORTB2Port B Data Register bit 2RW0PORTB1Port B Data Register bit 1RW0PORTB0Port B Data Register bit 0RW0DDRBPort B Data Direction Register$17$37io_flag.bmpNDDB7Port B Data Direction Register bit 7RW0DDB6Port B Data Direction Register bit 6RW0DDB5Port B Data Direction Register bit 5RW0DDB4Port B Data Direction Register bit 4RW0DDB3Port B Data Direction Register bit 3RW0DDB2Port B Data Direction Register bit 2RW0DDB1Port B Data Direction Register bit 1RW0DDB0Port B Data Direction Register bit 0RW0PINBPort B Input PinsThe Port B Input Pins address - PINB - is not a register, and this address enables access to the physical value on each Port B pin. When reading PORTB, the Port B Data Latch is read, and when reading PINB, the logical values present on the pins are read.$16$36io_port.bmpNPINB7Port B Input Pins bit 7R0PINB6Port B Input Pins bit 6R0PINB5Port B Input Pins bit 5R0PINB4Port B Input Pins bit 4R0PINB3Port B Input Pins bit 3R0PINB2Port B Input Pins bit 2R0PINB1Port B Input Pins bit 1R0PINB0Port B Input Pins bit 0R0[EEAR:EEDR:EECR]io_cpu.bmpEEPROM_02.xmlEEAREEPROM Read/Write AccessThe EEPROM access register is accessible in the I/O space. The write access time is in the range of 2.5 - 4ms, depending on the V CC voltages. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains code that writes the EEPROM, some pre-caution must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. CPU operation under these conditions is likely cause the program counter to perform unintentional jumps and eventually execute the EEPROM write code. To secure EEPROM integrity, the user is advised to use an external under-voltage reset circuit in this case. In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction$1E$3Eio_cpu.bmpNEEAR6EEPROM Read/Write Access bit 6RW0EEAR5EEPROM Read/Write Access bit 5RW0EEAR4EEPROM Read/Write Access bit 4RW0EEAR3EEPROM Read/Write Access bit 3RW0EEAR2EEPROM Read/Write Access bit 2RW0EEAR1EEPROM Read/Write Access bit 1RW0EEAR0EEPROM Read/Write Access bit 0RW0EEDREEPROM Data RegisterFor the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.$1D$3Dio_cpu.bmpNEEDR7EEPROM Data Register bit 7RW0EEDR6EEPROM Data Register bit 6RW0EEDR5EEPROM Data Register bit 5RW0EEDR4EEPROM Data Register bit 4RW0EEDR3EEPROM Data Register bit 3RW0EEDR2EEPROM Data Register bit 2RW0EEDR1EEPROM Data Register bit 1RW0EEDR0EEPROM Data Register bit 0RW0EECREEPROM Control Register$1C$3Cio_flag.bmpYEERIEEEProm Ready Interrupt EnableWhen the I-bit in SREG and EERIE are set (one), the EEPROM Ready Interrupt is enabled. When cleared (zero), the interrupt is disabled. The EEPROM Ready Interrupt generates a constant interrupt when EEWE is cleared (zero).RW0EEMWEEEPROM Master Write EnableThe EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set(one) setting EEWE will write data to the EEPROM at the selected address If EEMWE is zero, setting EEWE will have no effect. When EEMWE has been set (one) by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for a EEPROM write procedure.RW0EEWEEEPROM Write EnableThe EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 2 and 3 is unessential): 1. Wait until EEWE becomes zero. 2. Write new EEPROM address to EEARL and EEARH (optional). 3. Write new EEPROM data to EEDR (optional). 4. Write a logical one to the EEMWE bit in EECR (to be able to write a logical one to the EEMWE bit, the EEWE bit mustbewritten to zero in thesamecycle). 5. Within four clock cycles after setting EEMWE, write a logical one to EEWE. When the write access time (typically 2.5 ms at V CC =5Vor 4msatV CC = 2.7V) has elapsed, the EEWE bit is cleared (zero) by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted or two cycles before the next instruction is executed. Caution: An interrupt between step 4 and step 5 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR regis-ter will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the 4 last steps to avoid these problems.RW0EEREEEPROM Read EnableThe EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be set. When the EERE bit is cleared (zero) by hardware, requested data is found in the EEDR register. The EEPROM read access takes one instruction and there is no need to poll the EERE bit. When EERE has been set, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress when new data or address is written to the EEPROM I/O registers, the write operation will be interrupted, and the result is undefined.RW0[WDTCR]io_watch.bmpWDTCRWDTCSRWatchdog Timer Control Register$21$41io_flag.bmpYWDCEWDTOEWatchdog Change EnableThis bit must be set when the WDE bit is written to logic zero.Otherwise,the watchdog will not be disabled.Once written to one,hardware will clear this bit after four clock cycles.Refer to the description of the WDE bit for a watchdog disable procedure.This bit must also be set when changing the prescaler bits. RW0WDEWatch Dog EnableWhen the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdogRW0WDP2Watch Dog Timer Prescaler bit 2The WDP2,WDP1,and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled.RW0WDP1Watch Dog Timer Prescaler bit 1The WDP2,WDP1,and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled.RW0WDP0Watch Dog Timer Prescaler bit 0The WDP2,WDP1,and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled.RW0[SREG:SP:MCUCR:MCUSR:OSCCAL]io_cpu.comSREGStatus Register$3F$5Fio_sreg.bmpYIGlobal Interrupt EnableThe global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable bit is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts.RW0TBit Copy StorageThe bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction.RW0HHalf Carry FlagThe half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed information.RW0SSign BitThe S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruc-tion Set Description for detailed information.RW0VTwo's Complement Overflow FlagThe two’s complement overflow flag V supports two’s complement arithmetics. See the Instruction Set Description for detailed information.RW0NNegative FlagThe negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.RW0ZZero FlagThe zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.RW0CCarry FlagThe carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software.RW0SPStack Pointer$3D$5Dio_sreg.bmpNSP7Stack Pointer Bit 7RW0SP6Stack Pointer Bit 6RW0SP5Stack Pointer Bit 5RW0SP4Stack Pointer Bit 4RW0SP3Stack Pointer Bit 3RW0SP2Stack Pointer Bit 2RW0SP1Stack Pointer Bit 1RW0SP0Stack Pointer Bit 0RW0MCUCRMCU Control RegisterThe MCU Control Register contains control bits for general MCU functions.$35$55io_cpu.bmpYPUDPull-up DisableRW0SESleep EnableThe SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmers purpose, it is recommended to set the Sleep Enable SE bit just before the execution of the SLEEP instruction.R0SM1Sleep Mode Select Bit 1RW0SM0Sleep Mode Select Bit 0RW0ISC01Interrupt Sense Control 0 bit 1R0ISC00Interrupt Sense Control 0 bit 0R0MCUSRMCU Status registerThe MCU Status Registerprovides information on which reset source caused a MCU reset.$34$54io_cpu.bmpYWDRFWatchdog Reset FlagRW0BORFBrown-out Reset FlagRW0EXTRFExternal Reset FlagAfter a power-on reset, this bit is undefined (X). It will be set by an external reset. A watchdog reset will leave this bit unchanged.RW0PORFPower-On Reset FlagThis bit is set by a power-on reset. A watchdog reset or an external reset will leave this bit unchangedRW0OSCCALStatus Register$31$51io_sreg.bmpNCAL7Oscillator Calibration Value Bit 7RW0CAL6Oscillator Calibration Value Bit 6RW0CAL5Oscillator Calibration Value Bit 5RW0CAL4OSCCAL4Oscillator Calibration Value Bit 4RW0CAL3OSCCAL3Oscillator Calibration Value Bit 3RW0CAL2OSCCAL2Oscillator Calibration Value Bit 2RW0CAL1OSCCAL1Oscillator Calibration Value Bit 1RW0CAL0OSCCAL0Oscillator Calibration Value Bit 0RW0[TIMSK:TIFR:TCCR0:TCNT0]io_timer.bmpt81The 8-bit Timer/Counter0 can select clock source from CK, prescaled CK, or an external pin. In addition it can be stopped as described in “Timer/Counter0 Control Register - TCCR0” on page 35. The overflow status flag is found in “The Timer/Counter Interrupt Flag Register - TIFR” on page 29. Control signals are found in the Timer/Counter0 Control Register - TCCR0. The interrupt enable/disable settings for Timer/Counter0 are found in “The Timer/Counter Interrupt Mask Regis-ter - TIMSK” on page 28. When Timer/Counter0 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. The 8-bit Timer/Counter0 features both a high resolution and a high accuracy usage with the lower prescaling opportuni-ties. Similarly, the high prescaling opportuni ties make the Timer/Counter0 useful for lower speed functions or exact timing functions with infrequent actionsTIMSKTimer/Counter Interrupt Mask Register$39$59io_flag.bmpYTOIE0Timer/Counter0 Overflow Interrupt EnableWhen the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.RW0TIFRTimer/Counter Interrupt Flag register$38$58io_flag.bmpYTOV0Timer/Counter0 Overflow FlagThe bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, and TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed.RW0TCCR0Timer/Counter0 Control Register$33$53io_flag.bmpYPSR0Prescaler Reset Timer/Counter0When this bit is set (one), the prescaler of the Timer/Counter0 will be reset. The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. This bit will always be read as zero.RW0CS02Clock Select0 bit 2RW0CS01Clock Select0 bit 1RW0CS00Clock Select0 bit 0RW0TCNT0Timer Counter 0The Timer/Counter0 is realized as an up-counter with read and write access. If the Timer/Counter0 is written and a clock source is present, the Timer/Counter0 continues counting in the clock cycle following the write operation.$32$52io_timer.bmpNTCNT07Timer Counter 0 bit 7RW0TCNT06Timer Counter 0 bit 6RW0TCNT05Timer Counter 0 bit 5RW0TCNT04Timer Counter 0 bit 4RW0TCNT03Timer Counter 0 bit 3RW0TCNT02Timer Counter 0 bit 2RW0TCNT01Timer Counter 0 bit 1RW0TCNT00Timer Counter 0 bit 0RW0[TCCR1A:TCCR1B:TCNT1:OCR1A:OCR1B:OCR1C:TIMSK:TIFR:PLLCSR]io_timer.bmpt8pwm1_00TCCR1ATimer/Counter Control Register A$30$50io_flag.bmpYCOM1A1Comparator A Output Mode Bit 1The COM1A1 and COM1A0 control bits determine any output pin action following a compare match with compare register A in Timer/Counter1. Output pin actions affect pin PB1 (OC1A). Since this is an alternative function to an I/O port, the corresponding direction control bit must be set (one) in order to control an output pin. Note that OC1A is not connected in normal mode.RW0COM1A0Comparator A Output Mode Bit 0The COM1A1 and COM1A0 control bits determine any output pin action following a compare match with compare register A in Timer/Counter1. Output pin actions affect pin PB1 (OC1A). Since this is an alternative function to an I/O port, the corresponding direction control bit must be set (one) in order to control an output pin. Note that OC1A is not connected in normal mode.RW0COM1B1Comparator B Output Mode Bit 1The COM1B1 and COM1B0 control bits determine any output pin action following a compare match with compare register B in Timer/Counter1. Output pin actions affect pin PB3 (OC1B). Since this is an alternative function to an I/O port, the corresponding direction control bit must be set (one) in order to control an output pin. Note that OC1B is not connected in normal mode.RW0COM1B0Comparator B Output Mode Bit 0The COM1B1 and COM1B0 control bits determine any output pin action following a compare match with compare register B in Timer/Counter1. Output pin actions affect pin PB3 (OC1B). Since this is an alternative function to an I/O port, the corresponding direction control bit must be set (one) in order to control an output pin. Note that OC1B is not connected in normal mode.RW0FOC1AForce Output Compare Match 1AWriting a logical one to this bit forces a change in the compare match output pin PB1 (OC1A) according to the values already set in COM1A1 and COM1A0. If COM1A1 and COM1A0 written in the same cycle as FOC1A, the new settings will be used. The Force Output Compare bit can be used to change the output pin value regardless of the timer value. The automatic action programmed in COM1A1 and COM1A0 takes place as if a compare match had occurred, but no interrupt is generated. The FOC1A bit always reads as zero. FOC1A is not in use if PWM1A bit isRW0FOC1BForce Output Compare Match 1BWriting a logical one to this bit forces a change in the compare match output pin PB3 (OC1B) according to the values already set in COM1B1 and COM1B0. If COM1B1 and COM1B0 written in the same cycle as FOC1B, the new settings will be used. The Force Output Compare bit can be used to change the output pin value regardless of the timer value. The automatic action programmed in COM1B1 and COM1B0 takes place as if a compare match had occurred, but no interrupt is generated. The FOC1B bit always reads as zero. FOC1B is not in use if PWM1B bit is setRW0PWM1APulse Width Modulator A EnableWhen set (one) this bit enables PWM mode based on comparator OCR1A in Timer/Counter1 and the counter value is reset to $00 in the CPU clock cycle after a compare match with OCR1C register value.RW0PWM1BPulse Width Modulator B EnableWhen set (one) this bit enables PWM mode based on comparator OCR1B in Timer/Counter1 and the counter value is reset to $00 in the CPU clock cycle after a compare match with OCR1C register value.RW0TCCR1BTimer/Counter Control Register B$2F$4Fio_flag.bmpYCTC1Clear Timer/Counter on Compare MatchWhen the CTC1 control bit is set (one), Timer/Counter1 is reset to $00 in the CPU clock cycle after a compare match with OCR1C register value. If the control bit is cleared, Timer/Counter1 continues counting and is unaffected by a compare match.RW0PSR1Prescaler Reset Timer/Counter1When this bit is set (one), the Timer/Counter prescaler will be reset. The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. This bit will always read as zero.RW0CS13Clock Select BitsThe Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1.RW0CS12Clock Select BitsThe Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1.RW0CS11Clock Select BitsThe Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1.RW0CS10Clock Select BitsThe Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1.RW0TCNT1Timer/Counter RegisterThe Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT1 register blocks (removes) the compare match on the following timer clock. Modifying the counter (TCNT1) while the counter is running, introduces a risk of missing a compare match between TCNT1 the OCR2 register. $2E$4Eio_timer.bmpNTCNT1_7Timer/Counter Register Bit 7RW0TCNT1_6Timer/Counter Register Bit 6RW0TCNT1_5Timer/Counter Register Bit 5RW0TCNT1_4Timer/Counter Register Bit 4RW0TCNT1_3Timer/Counter Register Bit 3RW0TCNT1_2Timer/Counter Register Bit 2RW0TCNT1_1Timer/Counter Register Bit 1RW0TCNT1_0Timer/Counter Register Bit 0RW0OCR1AOutput Compare RegisterThe Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT1). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC2 pin.$2D$4Dio_timer.bmpNOCR1A7Output Compare Register A Bit 7RW0OCR1A6Output Compare Register A Bit 6RW0OCR1A5Output Compare Register A Bit 5RW0OCR1A4Output Compare Register A Bit 4RW0OCR1A3Output Compare Register A Bit 3RW0OCR1A2Output Compare Register A Bit 2RW0OCR1A1Output Compare Register A Bit 1RW0OCR1A0Output Compare Register A Bit 0RW0OCR1BOutput Compare RegisterThe Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT1). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC2 pin.$2C$4Cio_timer.bmpNOCR1B7Output Compare Register B Bit 7RW0OCR1B6Output Compare Register B Bit 6RW0OCR1B5Output Compare Register B Bit 5RW0OCR1B4Output Compare Register B Bit 4RW0OCR1B3Output Compare Register B Bit 3RW0OCR1B2Output Compare Register B Bit 2RW0OCR1B1Output Compare Register B Bit 1RW0OCR1B0Output Compare Register B Bit 0RW0OCR1COutput Compare RegisterThe Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT1). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC2 pin.$2B$4Bio_timer.bmpNOCR1C7Output Compare Register C Bit 7RW0OCR1C6Output Compare Register C Bit 6RW0OCR1C5Output Compare Register C Bit 5RW0OCR1C4Output Compare Register C Bit 4RW0OCR1C3Output Compare Register C Bit 3RW0OCR1C2Output Compare Register C Bit 2RW0OCR1C1Output Compare Register C Bit 1RW0OCR1C0Output Compare Register C Bit 0RW0TIMSKTimer/Counter Interrupt Mask Register$39$59io_flag.bmpYOCIE1ATimer/Counter1 Output Compare Interrupt EnableWhen the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Compare MatchA, interrupt is enabled. The corresponding interrupt at vector $003 is executed if a compare matchA occurs. The Compare Flag in Timer/Counter1 is set (one) in the Timer/Counter Interrupt Flag Register.RW0OCIE1BTimer/Counter1 Output Compare Interrupt EnableWhen the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Compare MatchB, interrupt is enabled. The corresponding interrupt at vector $004 is executed if a compare matchB occurs. The Compare Flag in Timer/Counter1 is set (one) in the Timer/Counter Interrupt Flag Register.RW0TOIE1Timer/Counter1 Overflow Interrupt EnableWhen the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $004) is executed if an overflow in Timer/Counter1 occurs (i.e., when the TOV1 bit is set in the Timer/Counter Interrupt Flag Register [TIFR]).RW0TIFRTimer/Counter Interrupt Flag Register$38$58io_flag.bmpYOCF1ATimer/Counter1 Output Compare Flag 1AThe OCF1A bit is set (one) when compare match occurs between Timer/Counter1 and the data value in OCR1A (Output Compare Register 1A). OCF1A is cleared by hard-ware when executing the corresponding interrupt handling vector. Alternatively, OCF1A is cleared by writing a logical “1” to the flag. When the I-bit in SREG, OCIE1A, and OCF1A are set (one), the Timer/Counter1 compare match A interrupt is executed.RW0OCF1BTimer/Counter1 Output Compare Flag 1BThe OCF1B bit is set (one) when compare match occurs between Timer/Counter1 and the data value in OCR1B – Output Compare Register 1A. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF1B is cleared, after synchronization clock cycle, by writing a logic one to the flag. When the I-bit in SREG, OCIE1B, and OCF1B are set (one), the Timer/Counter1 B compare match interrupt is executed.RW0TOV1Timer/Counter1 Overflow FlagThe bit TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logical “1” to the flag. When the SREG I-bit, TOIE1 (Timer/Counter1 Overf low Interrupt Enable) and TOV1 are set (one), the Timer/Counter1 Overflow interrupt is executed.RW0PLLCSRPLL Control and Status Register$29$49io_sreg.bmpYPCKEPCK EnableRW0PLLEPLL EnableRW0PLOCKPLL Lock DetectorR0[GIMSK:GIFR]io_ext.bmpGIMSKGeneral Interrupt Mask Register$3B$5Bio_flag.bmpYINT0External Interrupt Request 0 EnableWhen the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from program memory address $001. See also “External Interrupts.” • Bits 5..0 - Res: Reserved bitsRW0PCIE1Pin Change Interrupt Enable 1RW0PCIE0Pin Change Interrupt Enable 0RW0GIFRGeneral Interrupt Flag register$3A$5Aio_flag.bmpYINTF0External Interrupt Flag 0When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the interrupt vector at address $001. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. RW0PCIFPin Change Interrupt FlagRW0[ICE50:SIMULATOR:STK500:STK500_2:AVRISPmkII]0x050x0F0x0F0x0F0x050x050x050x050x050x050x050x050x050x0F0x0F0x0F0x150x140x140x000000DF0x000000000x000000000x000000000x0000007F0x000007FF0x000003FF0x000003FF0x000003FF0x000003FF0x000000DF0x0000FFFF0x0000007F0x000000000x000000000x000000000x0023FFFF0x00000FFF0x000000600x000000000x000000000x000000000x000000000x0000007F0x000007FF0x000003FF0x000003FF0x000003FF0x000003FF0x000000DF0x0000FFFF0x0000007F0x000000000x000000000x000000000x0023FFFF0x00000FFF0x000000600x000000000x000000000x000000000x000000000x0000007F0x000007FF0x000003FF0x000003FF0x000003FF0x000003FF0x000000DF0x0000FFFF0x0000007F0x000000000x000000000x000000000x0023FFFF0x00000FFF0x0000000000x000x000x000x000xF70xE10xff0x510xc7ATtiny26.bin0x020x0010000004000000072 ; INTOSC = 1, INTRC=2;EXTCLK=41 ;NOTUSE = 1, EXTERNAL = 4, INTERNAL = 2 1 00x000x010x010x020x80E80x000000310x00000000258 CK, 4.1 ms 0x000000310x00000010258 CK, 65 ms0x000000310x000000201K CK0x000000310x000000301K CK, 4.1 ms0x000000310x000000011K CK, 65 ms0x000000310x0000001116K CK0x000000310x0000002116K CK, 4.1 ms0x000000310x0000003116K CK, 65 ms0x000000300x000000006 CK0x000000300x000000106 CK, 4.1 ms0x000000300x000000206 CK, 65 ms0x000000300x000000006 CK0x000000300x000000106 CK, 4.1 ms0x000000300x000000206 CK, 65 ms0x000000300x000000001K CK0x000000300x000000101K CK, 4.1 ms0x000000300x000000201K CK, 65 ms0x000000300x0000003016K CK0x000000ff0x000000Ab0x000000ff0x000000E11.00x000000ff0x000000E22.00x000000ff0x000000E34.00x000000ff0x000000E48.00x000000ff0x000000E00x000000ff0x000000200x000010000x00000000RSTDSBL Fuse 0x000010000x00001000RSTDSBL Fuse 0x000003000x00000300BOD disabled0x000003000x00000200BOD enabled, 2.7 V0x000003000x00000000BOD enabled, 4.0 VAVRSimCoreV2.SimCoreV2AVRSimMemory8bit.SimMemory8bitAVRSimInterrupt.SimInterrupt0x0909AVRSimIOPort.SimIOPortNAVRSimIOPort.SimIOPortNAVRSimIOExtInterrupt.SimIOExtInterrupt0x010x3B0x0x400x3A0x400x160x400x350x03AVRSimIOPinChangeT26.SimIOPinChangeT260x020x3B0x100x200x3A0x200x100x160xf00x190xc80x160x0fAVRSimIOTimert81.SimIOTimert810x060x160x40AVRSimIOTimer8pll_OCABC.SimIOTimer8pll_OCABC0x030x040x050x160x170x020x080x010x04AVRSimAC.SimIOAC0x0AAvrSimADC.SimADC0x0BAvrSimUSI.SimUSI0x080x070xff0xff0xff0xff0x211110xFF0xFF0xFF012001002532030x53111000x2116100x400x4C0x200xFF0x000x0464100xC00x000xA00xFF0xFF25625644440xC4 0xE4 0xC4 0xE4 0xCC 0xEC 0xCC 0xEC 0xD4 0xF4 0xD4 0xF4 0xDC 0xFC 0xDC 0xFC 0xC8 0xE8 0xD8 0xF8 0x4C 0x6C 0x5C 0x7C 0xEC 0xBC 0x00 0x06 0x00 0x00 0x00 0x001000511520151501050x0B25625650x052562560505