[ADMIN:FUSE:LOCKBIT:MEMORY:PROGRAMMING:CORE:INTERRUPT_VECTOR:PACKAGE:IO_MODULE:ICE_SETTINGS]ATtiny284MHZ1RELEASED$1E$91$07[LOW]1750x100x00Internal load capacitors between XTAL1/XTAL2 and GND0x0F0x0FCKSEL=1111 External Crystal / Ceramic Resonator0x0F0x0ECKSEL=1110 External Crystal / Ceramic Resonator0x0F0x0DCKSEL=1101 External Crystal / Ceramic Resonator0x0F0x0CCKSEL=1100 External Crystal / Ceramic Resonator0x0F0x0BCKSEL=1011 External Crystal / Ceramic Resonator0x0F0x0ACKSEL=1010 External Crystal / Ceramic Resonator0x0F0x09CKSEL=1001 External Low-Frequency Crystal0x0F0x08CKSEL=1000 External Low-Frequency Crystal0x0F0x07CKSEL=0111 External RC Ocsillator0x0F0x06CKSEL=0110 External RC Ocsillator0x0F0x05CKSEL=0101 External RC Ocsillator0x0F0x04CKSEL=0100 Internal RC Ocsillator0x0F0x03CKSEL=0011 Internal RC Ocsillator0x0F0x02CKSEL=0010 Internal RC Ocsillator ; default value0x0F0x01CKSEL=0001 External Clock0x0F0x00CKSEL=0000 External Clock[LB1 = 1 : LB2 = 1] No memory lock features enabled. [LB1 = 0 : LB2 = 1] Further programming of Flash and EEPROM is enabled. [LB1 = 0 : LB2 = 0] Same as previous, but verify is also disabled320x060x06Mode 1: No memory lock features enabled0x060x04Mode 2: Further programming disabled0x060x00Mode 3: Further programming and verification disabledLB1LockbitLB2LockbitAVRSimMemory8bit.SimMemory8bit204800NA0NA$00$3FNANA$20$5F$3FNA0x010x020x040x080x100x200x400x80$1BNA$0f0x010x020x040x08$1ANA0x010x020x040x08$19NA$b0x010x020x08$16NA$ff0x010x020x040x080x100x200x400x80$12NA$ff0x010x020x040x080x100x200x400x80$11NA0x010x020x040x080x100x200x400x80$10NA0x010x020x040x080x100x200x400x80$08NA0x010x020x080x100x200x80$07NA0x010x020x080x100x200x80$06NA0x010x020x040x080x100x200x400x80$05NA0x100x400x80$04NA0x010x020x040x080x100x80$03NA0x010x020x040x080x100x200x400x80$02NA0x010x020x040x080x100x200x400x80$01NA0x010x020x040x080x10$00NA0x010x020x040x080x100x200x400x800x00,1.2 MHz00V0EAVRSimCoreV0.SimCoreV0[][][]32$00$1B$1A$1D$1C$1F$1E6$000External Reset, Power-on Reset and Watchdog Reset$001External Interrupt 0$002External Interrupt 1$003Low-level Input on Port B$004Timer/Counter0 Overflow$005Analog Comparator[TQFP]32[PD3][PD4][NC][VCC][GND][NC][XTAL1][XTAL2][PD5][PD6][PD7][AIN0:PB0][AIN1:PB1][T0:PB2][INT0:PB3][INT1:PB4][PB5][VCC][NC][NC][GND][NC][PB6][PB7][PA2:IR][PA3][PA1][PA0][RESET][PD0][PD1][PD2][PORTD:CPU:ANALOG_COMPARATOR:TIMER_COUNTER_0:WATCHDOG:EXTERNAL_INTERRUPT:PORTA:PORTB:MODULATOR][PORTD:DDRD:PIND]io_port.bmpAVRSimIOPort.SimIOPortPORTDPort D Data Register$12NAio_port.bmpNPORTD7Port D Data Register bit 7RW0PORTD6Port D Data Register bit 6RW0PORTD5Port D Data Register bit 5RW0PORTD4Port D Data Register bit 4RW0PORTD3Port D Data Register bit 3RW0PORTD2Port D Data Register bit 2RW0PORTD1Port D Data Register bit 1RW0PORTD0Port D Data Register bit 0RW0DDRDPort D Data Direction Register$11NAio_flag.bmpNDDD7Port D Data Direction Register bit 7RW0DDD6Port D Data Direction Register bit 6RW0DDD5Port D Data Direction Register bit 5RW0DDD4Port D Data Direction Register bit 4RW0DDD3Port D Data Direction Register bit 3RW0DDD2Port D Data Direction Register bit 2RW0DDD1Port D Data Direction Register bit 1RW0DDD0Port D Data Direction Register bit 0RW0PINDPort D Input PinsThe Port D Input Pins address - PIND - is not a register, and this address enables access to the physical value on each Port D pin. When reading PORTD, the Port D Data Latch is read, and when reading PIND, the logical values present on the pins are read.$10NAio_port.bmpNPIND7Port D Input Pins bit 7R0PIND6Port D Input Pins bit 6R0PIND5Port D Input Pins bit 5R0PIND4Port D Input Pins bit 4R0PIND3Port D Input Pins bit 3R0PIND2Port D Input Pins bit 2R0PIND1Port D Input Pins bit 1R0PIND0Port D Input Pins bit 0R0[SREG:ICR:MCUCS:OSCCAL]io_cpu.comSREGStatus Register$3FNAio_sreg.bmpYIGlobal Interrupt EnableThe global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable bit is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts.RW0TBit Copy StorageThe bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction.RW0HHalf Carry FlagThe half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed information.RW0SSign BitThe S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruc-tion Set Description for detailed information.RW0VTwo's Complement Overflow FlagThe two’s complement overflow flag V supports two’s complement arithmetics. See the Instruction Set Description for detailed information.RW0NNegative FlagThe negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.RW0ZZero FlagThe zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.RW0CCarry FlagThe carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software.RW0ICRInterrupt Control Register$06NAio_cpu.bmpYICS11Interrupt Sense Control 1 bit 1RW0ICS10Interrupt Sense Control 1 bit 0RW0ISC01Interrupt Sense Control 0 bit 1RW0ISC00Interrupt Sense Control 0 bit 0RW0MCUCSMCU Control and Status RegisterThe MCU Control and Status Register contains control and status bits for general MCU functions.$07NAio_cpu.bmpYPLUPBPull-up Enable Port BWhen the PLUPB bit is set (one), pull-up resistors are enabled on all Port B input pins. RW0SESleep EnableThe SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmers purpose, it is recommended to set the Sleep Enable SE bit just before the execution of the SLEEP instruction.RW0SMSleep ModeThis bit selects between the two available sleep modes. When SM is cleared (zero), Idle Mode is selected as Sleep Mode. When SM is set (one), Power Down mode is selected as sleep mode. For details, refer to the section “Sleep Modes” on page 25.RW0WDRFWatchdog Reset FlagRW0EXTRFExternal Reset FlagAfter a power-on reset, this bit is undefined (X). It will be set by an external reset. A watchdog reset will leave this bit unchanged.RW0PORFPower-On Reset FlagThis bit is set by a power-on reset. A watchdog reset or an external reset will leave this bit unchangedRW0OSCCALStatus Register$00NAio_sreg.bmpNCAL7Oscillator Calibration Value Bit 7RW0CAL6Oscillator Calibration Value Bit 6RW0CAL5Oscillator Calibration Value Bit 5RW0CAL4Oscillator Calibration Value Bit 4RW0CAL3Oscillator Calibration Value Bit 3RW0CAL2Oscillator Calibration Value Bit 2RW0CAL1Oscillator Calibration Value Bit 1RW0CAL0Oscillator Calibration Value Bit 0RW0[ACSR]io_analo.bmpThe analog comparator compares the input values on the positive input PB2 (AIN0) and negative input PB3 (AIN1). When the voltage on the positive input PB2 (AIN0) is higher than the voltage on the negative input PB3 (AIN1), the Analog Com-parator Output, ACO is set (one). The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator. The user can select Inter-rupt triggering on comparator output rise, fall or toggleACSRAnalog Comparator Control And Status Register$08NAio_analo.bmpYACDAnalog Comparator DisableWhen this bit is set(one), the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.RW0ACOAnalog Comparator OutputWhen this bit is set(one), the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.R0ACIAnalog Comparator Interrupt FlagThis bit is set (one) when a comparator output event triggers the interrupt mode defined by ACI1 and ACI0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set (one) and the I-bit in SREG is set (one). ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag. Observe however, that if another bit in this register is modified using the SBI or CBI instruction, ACI will be cleared if it has become set before the operationRW0ACIEAnalog Comparator Interrupt EnableWhen the ACIE bit is set (one) and the I-bit in the Status Register is set (one), the analog comparator interrupt is activated. When Cleared (Zero), the interrupt is disabled. RW0ACIS1Analog Comparator Interrupt Mode Select bit 1These bits determine which comparator events that trigger the Analog Comparator interrupt.RW0ACIS0Analog Comparator Interrupt Mode Select bit 0These bits determine which comparator events that trigger the Analog Comparator interrupt.RW0[ICR:IFR:TCCR0:TCNT0]io_timer.bmpt81The 8-bit Timer/Counter0 can select clock source from CK, prescaled CK, or an external pin. In addition it can be stopped as described in “Timer/Counter0 Control Register - TCCR0” on page 35. The overflow status flag is found in “The Timer/Counter Interrupt Flag Register - TIFR” on page 29. Control signals are found in the Timer/Counter0 Control Register - TCCR0. The interrupt enable/disable settings for Timer/Counter0 are found in “The Timer/Counter Interrupt Mask Regis-ter - TIMSK” on page 28. When Timer/Counter0 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. The 8-bit Timer/Counter0 features both a high resolution and a high accuracy usage with the lower prescaling opportuni-ties. Similarly, the high prescaling opportuni ties make the Timer/Counter0 useful for lower speed functions or exact timing functions with infrequent actionsICRInterrupt Control Register$06NAio_flag.bmpYTOIE0Timer/Counter0 Overflow Interrupt EnableWhen the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.RW0IFRInterrupt Flag register$05NAio_flag.bmpYTOV0Timer/Counter0 Overflow FlagThe bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, and TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed.RW0TCCR0Timer/Counter0 Control Register$04NAio_flag.bmpYFOV0Force OverflowWriting a logical "1" to this bit forces a change on the overflow output pin PA2 according to the values already set in OOM01 and OOM00.RW0OOM01Overflow Output Mode, Bit 1The OOM01 and OOM00 control bits determine any output pin action following an overflow or a forced overflow in Timer/Counter0. RW0OOM00Overflow Output Mode, Bit 0The OOM01 and OOM00 control bits determine any output pin action following an overflow or a forced overflow in Timer/Counter0. RW0CS02Clock Select0 bit 2RW0CS01Clock Select0 bit 1RW0CS00Clock Select0 bit 0RW0TCNT0Timer Counter 0The Timer/Counter0 is realized as an up-counter with read and write access. If the Timer/Counter0 is written and a clock source is present, the Timer/Counter0 continues counting in the clock cycle following the write operation.$03NAio_timer.bmpNTCNT07Timer Counter 0 bit 7RW0TCNT06Timer Counter 0 bit 6RW0TCNT05Timer Counter 0 bit 5RW0TCNT04Timer Counter 0 bit 4RW0TCNT03Timer Counter 0 bit 3RW0TCNT02Timer Counter 0 bit 2RW0TCNT01Timer Counter 0 bit 1RW0TCNT00Timer Counter 0 bit 0RW0[WDTCR]io_watch.bmpWDTCRWatchdog Timer Control Register$01NAio_flag.bmpYWDTOEWDDERWThis bit must be set (one) when the WDE bit is cleared. Otherwise, the watchdog will not be disabled. Once set, hardware will clear this bit to zero after four clock cycles. Refer to the description of the WDE bit for a watchdog disable procedure.RW0WDEWatch Dog EnableWhen the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdogRW0WDP2Watch Dog Timer Prescaler bit 2RW0WDP1Watch Dog Timer Prescaler bit 1RW0WDP0Watch Dog Timer Prescaler bit 0RW0[ICR:IFR]io_ext.bmpICRInterrupt Control Register$06NAio_flag.bmpYINT1External Interrupt Request 1 EnableWhen the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled.The interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) define whether the external interrupt is activated on rising or falling edge, on pin change or low level of the INT0 pin.RW0INT0External Interrupt Request 0 EnableWhen the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled.The interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) define whether the external interrupt is activated on rising or falling edge, on pin change or low level of the INT0 pin.RW0LLIELow-level Input Interrupt EnableWhen the LLIE is set (one) and the I-bit in the status register (SREG) is set (one), the interrupt on low-level input is activated. Any of the Port B pins pulled low will then cause an interrupt.RW0IFRInterrupt Flag register$05NAio_flag.bmpYINTF1External Interrupt Flag 1When the INT1 bit is set (one) and I-bit in the Status Register (SREG) is set (one), the external pin interrupt 1 is enabled.RW0INTF0External Interrupt Flag 0When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in ICR are set (one), the MCU will jump to the interrupt vector at address $001. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. RW0[PORTA:PACR:PINA]io_port.bmpAVRSimIOPort.SimIOPortPORTAPort A Data Register$1BNAio_port.bmpNPORTA3Port A Data Register bit 3RW0PORTA2Port A Data Register bit 2RW0PORTA1Port A Data Register bit 1RW0PORTA0Port A Data Register bit 0RW0PACRPort A Control Register$1ANAio_flag.bmpNDDA3Data Direction Port A, bit 3RW0PA2HC PORTA2 High Current EnableRW0DDA1Data Direction Port A, bit 1RW0DDA0Data Direction Port A, bit 0RW0PINAPort A Input PinsThe Port A Input Pins address - PINA - is not a register, and this address enables access to the physical value on each Port A pin. When reading PORTA the Port A Data Latch is read, and when reading PINA, the logical values present on the pins are read.$19NAio_port.bmpNPINA3Input Pins, Port A bit 3RHi-ZPINA1Input Pins, Port A bit 1RHi-ZPINA0Input Pins, Port A bit 0RHi-Z[PINB]io_port.bmpAVRSimIOPort.SimIOPortPINBPort B Input PinsThe Port B Input Pins address - PINB - is not a register, and this address enables access to the physical value on each Port B pin. When reading PORTB, the Port B Data Latch is read, and when reading PINB, the logical values present on the pins are read.$16NAio_port.bmpNPINB7Port B Input Pins bit 7R0PINB6Port B Input Pins bit 6R0PINB5Port B Input Pins bit 5R0PINB4Port B Input Pins bit 4R0PINB3Port B Input Pins bit 3R0PINB2Port B Input Pins bit 2R0PINB1Port B Input Pins bit 1R0PINB0Port B Input Pins bit 0R0[MODCR]io_poer.bmpMODCRModulation Control Register$02NAio_flag.bmpYONTIM4 Modulation On-time Bit 4ONTIM[4:0] +1 determines the number of clock cycles the output pin PA2 is active (low)RW0OTIM3 Modulation On-time Bit 3ONTIM[4:0] +1 determines the number of clock cycles the output pin PA2 is active (low)RW0ONTIM2 Modulation On-time Bit 2ONTIM[4:0] +1 determines the number of clock cycles the output pin PA2 is active (low)RW0ONTIM1 Modulation On-time Bit 1ONTIM[4:0] +1 determines the number of clock cycles the output pin PA2 is active (low)RW0ONTIM0 Modulation On-time Bit 0ONTIM[4:0] +1 determines the number of clock cycles the output pin PA2 is active (low)RW0MCONF2Modulation Configuration Bit 2MODCONF[2:0] determine the relationship between the on- and off-times of the modulat or , and thereby the duty-cycle.RW0MCONF1Modulation Configuration Bit 1MODCONF[2:0] determine the relationship between the on- and off-times of the modulat or , and thereby the duty-cycle.RW0MCONF0Modulation Configuration Bit 0MODCONF[2:0] determine the relationship between the on- and off-times of the modulat or , and thereby the duty-cycle.RW0[STK500:STK500_2:SIMULATOR]0x221100x000x000x0000x0E 0x1E 0x0F 0x1F 0x2E 0x3E 0x2F 0x3F 0x4E 0x5E 0x4F 0x5F 0x6E 0x7E 0x6F 0x7F 0x66 0x76 0x67 0x77 0x6A 0x7A 0x6B 0x7B 0xBE 0xFD 0x00 0x01 0x00 0x00 0x00 0x00100000000151501050x0025625650x002562560505AVRSimCoreV2.SimCoreV2AVRSimMemory8bit.SimMemory8bitAVRSimInterrupt.SimInterrupt8AVRSimIOPort.SimIOPort0x0fNAVRSimIOPort.SimIOPort0xffNAVRSimIOPort.SimIOPort0xffNAVRSimIOExtInterrupt.SimIOExtInterrupt0x010x060x400x050x400x160x080x060x03AVRSimIOExtInterrupt.SimIOExtInterrupt0x020x060x800x050x800x160x100x060x0cAVRSimIOPinChangeInterrupt.SimIOPinChangeInterrupt0x030x060x200x050x000x000x160xFFAVRSimIOTimert81.SimIOTimert810x040x160x04AVRSimAC.SimIOAC0x05