[ADMIN:CORE:PACKAGE:INTERRUPT_VECTOR:LOCKBIT:FUSE:MEMORY:PROGRAMMING:IO_MODULE:ICE_SETTINGS] ATtiny84 20MHZ 63 RELEASED $1E $93 $0C V2 AVRSimCoreV2.SimCoreV2 [lpm rd,z+] [] [] 32 $00 $1B $1A $1D $1C $1F $1E [SOIC:MLF] 14 [VCC] [PB0:PCINT8:XTAL1] [PB1:PCINT9:XTAL2] [PB3:PCINT11:'RESET:dW] [PB2:PCINT10:INT0:OC0A:CKOUT] [PA7:PCINT7:ICP1:OC0B:ADC7] [PA6:PCINT6:OC1A:DI:SDA:MOSI:ADC6] [PA5:ADC5:DO:MISO:OC1B:PCINT5] [PA4:ADC4:USCK:SCL:T1:PCINT4] [PA3:ADC3:T0:PCINT3] [PA2:ADC2:AIN1:PCINT2] [PA1:ADC1:AIN0:PCINT1] [PA0:ADC0:AREF:PCINT0] [GND] 20 [PA4:ADC4:USCK:SCL:T1:PCINT4] [PA3:ADC3:T0:PCINT3] [PA2:ADC2:AIN1:PCINT2] [PA1:ADC1:AIN0:PCINT1] [PA0:ADC0:AREF:PCINT0] NC NC [GND] [VCC] NC [PB0:PCINT8:XTAL1] [PB1:PCINT9:XTAL2] [PB3:PCINT11:'RESET:dW] [PB2:PCINT10:INT0:OC0A:CKOUT] [PA7:PCINT7:ICP1:OC0B:ADC7] [PA6:PCINT6:OC1A:DI:SDA:MOSI:ADC6] NC NC NC [PA5:ADC5:DO:MISO:OC1B:PCINT5] 17 $000 RESET External Pin, Power-on Reset, Brown-out Reset,Watchdog Reset $001 INT0 External Interrupt Request 0 $002 PCINT0 Pin Change Interrupt Request 0 $003 PCINT1 Pin Change Interrupt Request 1 $004 WDT Watchdog Time-out $005 TIMER1 CAPT Timer/Counter1 Capture Event $006 TIM1_COMPA Timer/Counter1 Compare Match A $007 TIM1_COMPB Timer/Counter1 Compare Match B $008 TIM1_OVF Timer/Counter1 Overflow $009 TIM0_COMPA Timer/Counter0 Compare Match A $00A TIM0_COMPB Timer/Counter0 Compare Match B $00B TIM0_OVF Timer/Counter0 Overflow $00C ANA_COMP Analog Comparator $00D ADC ADC Conversion Complete $00E EE_RDY EEPROM Ready $00F USI_START USI START $010 USI_OVF USI Overflow [LB1 = 1 : LB2 = 1] No memory lock features enabled. [LB1 = 0 : LB2 = 1] Further programming of Flash and EEPROM is enabled. [LB1 = 0 : LB2 = 0] Same as previous, but verify is also disabled 3 2 0x03 0x03 Mode 1: No memory lock features enabled 0x03 0x02 Mode 2: Further programming disabled 0x03 0x00 Mode 3: Further programming and verification disabled LB1 Lockbit LB2 Lockbit [LOW:HIGH:EXTENDED] 46 8 0x80 0x00 Divide clock by 8 internally; [CKDIV8=0] 0x40 0x00 Clock output on PORTB2; [CKOUT=0] 0x3F 0x00 Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms; [CKSEL=0000 SUT=00] 0x3F 0x10 Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms; [CKSEL=0000 SUT=01] 0x3F 0x20 Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms; [CKSEL=0000 SUT=10] 0x3F 0x02 Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms; [CKSEL=0010 SUT=00] 0x3F 0x12 Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4 ms; [CKSEL=0010 SUT=01] 0x3F 0x22 Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 64 ms; [CKSEL=0010 SUT=10]; default value 0x3F 0x04 WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms; [CKSEL=0100 SUT=00] 0x3F 0x14 WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4 ms; [CKSEL=0100 SUT=01] 0x3F 0x24 WD. Osc. 128 kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 64 ms; [CKSEL=0100 SUT=10] 0x3F 0x06 Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 0 ms; [CKSEL=0110 SUT=00] 0x3F 0x16 Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4 ms; [CKSEL=0110 SUT=01] 0x3F 0x26 Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 64 ms; [CKSEL=0110 SUT=10] 0x3F 0x08 Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms; [CKSEL=1000 SUT=00] 0x3F 0x18 Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms; [CKSEL=1000 SUT=01] 0x3F 0x28 Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms; [CKSEL=1000 SUT=10] 0x3F 0x38 Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms; [CKSEL=1000 SUT=11] 0x3F 0x09 Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms; [CKSEL=1001 SUT=00] 0x3F 0x19 Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms; [CKSEL=1001 SUT=01] 0x3F 0x29 Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms; [CKSEL=1001 SUT=10] 0x3F 0x39 Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms; [CKSEL=1001 SUT=11] 0x3F 0x0A Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms; [CKSEL=1010 SUT=00] 0x3F 0x1A Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms; [CKSEL=1010 SUT=01] 0x3F 0x2A Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms; [CKSEL=1010 SUT=10] 0x3F 0x3A Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms; [CKSEL=1010 SUT=11] 0x3F 0x0B Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms; [CKSEL=1011 SUT=00] 0x3F 0x1B Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms; [CKSEL=1011 SUT=01] 0x3F 0x2B Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms; [CKSEL=1011 SUT=10] 0x3F 0x3B Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms; [CKSEL=1011 SUT=11] 0x3F 0x0C Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms; [CKSEL=1100 SUT=00] 0x3F 0x1C Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms; [CKSEL=1100 SUT=01] 0x3F 0x2C Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms; [CKSEL=1100 SUT=10] 0x3F 0x3C Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms; [CKSEL=1100 SUT=11] 0x3F 0x0D Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms; [CKSEL=1101 SUT=00] 0x3F 0x1D Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms; [CKSEL=1101 SUT=01] 0x3F 0x2D Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms; [CKSEL=1101 SUT=10] 0x3F 0x3D Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms; [CKSEL=1101 SUT=11] 0x3F 0x0E Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms; [CKSEL=1110 SUT=00] 0x3F 0x1E Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms; [CKSEL=1110 SUT=01] 0x3F 0x2E Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms; [CKSEL=1110 SUT=10] 0x3F 0x3E Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms; [CKSEL=1110 SUT=11] 0x3F 0x0F Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms; [CKSEL=1111 SUT=00] 0x3F 0x1F Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms; [CKSEL=1111 SUT=01] 0x3F 0x2F Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms; [CKSEL=1111 SUT=10] 0x3F 0x3F Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms; [CKSEL=1111 SUT=11] CKSEL0 Select Clock source 0 CKSEL1 Select Clock source 1 CKSEL2 Select Clock source 0 CKSEL3 Select Clock source 1 SUT0 Select start-up time 0 SUT1 Select start-up time 1 CKOUT Clock Output Enable 1 CKDIV8 Divide clock by 8 0 13 8 0x80 0x00 Reset Disabled (Enable PB3 as i/o pin); [RSTDISBL=0] 0x40 0x00 Debug Wire enable; [DWEN=0] 0x20 0x00 Serial program downloading (SPI) enabled; [SPIEN=0] 0x10 0x00 Watch-dog Timer always on; [WDTON=0] 0x08 0x00 Preserve EEPROM memory through the Chip Erase cycle; [EESAVE=0] 0x07 0x07 Brown-out detection disabled; [BODLEVEL=111] 0x07 0x06 Brown-out detection level at VCC=1.8 V; [BODLEVEL=110] 0x07 0x05 Brown-out detection level at VCC=2.7 V; [BODLEVEL=101] 0x07 0x04 Brown-out detection level at VCC=4.3 V; [BODLEVEL=100] 0x07 0x03 Brown-out detection level at VCC=2.3 V; [BODLEVEL=011] 0x07 0x02 Brown-out detection level at VCC=2.2 V; [BODLEVEL=010] 0x07 0x01 Brown-out detection level at VCC=1.9 V; [BODLEVEL=001] 0x07 0x00 Brown-out detection level at VCC=2.0 V; [BODLEVEL=000] BODLEVEL0 Brown-out Detector trigger level 1 BODLEVEL1 Brown-out Detector trigger level 1 BODLEVEL2 Brown-out Detector trigger level 1 EESAVE EEPROM memory is preserved through the Chip Erase 1 WDTON Watchdog Timer always on 1 SPIEN Enable Serial Program and Data Downloading 0 DWEN DebugWIRE Enable 1 RSTDISBL External Reset disable 1 SELFPRGEN Self-Programming Enable 1 1 1 0x01 0x00 Self Programming enable; [SELFPRGEN=0] AVRSimMemory8bit.SimMemory8bit 8192 512 512 $60 0 NA $00 $3F NA NA $20 $5F $3F $5F 0x010x020x040x080x100x200x400x80 $3E $5E 0x010x02 $3D $5D 0x010x020x040x080x100x200x400x80 $3C $5C 0x010x020x040x080x100x200x400x80 $3B $5B 0x100x200x40 $3A $5A 0x100x200x40 $39 $59 0x010x020x04 $38 $58 0x010x020x04 $37 $57 0x010x020x040x080x10 $36 $56 0x010x020x040x080x100x200x400x80 $35 $55 0x010x020x080x100x200x40 $34 $54 0x010x020x040x08 $33 $53 0x010x020x040x080x400x80 $32 $52 0x010x020x040x080x100x200x400x80 $31 $51 0x010x020x040x080x100x200x400x80 $30 $50 0x010x020x100x200x400x80 $2F $4F 0x010x020x100x200x400x80 $2E $4E 0x010x020x040x080x100x400x80 $2D $4D 0x010x020x040x080x100x200x400x80 $2C $4C 0x010x020x040x080x100x200x400x80 $2B $4B 0x010x020x040x080x100x200x400x80 $2A $4A 0x010x020x040x080x100x200x400x80 $29 $49 0x010x020x040x080x100x200x400x80 $28 $48 0x010x020x040x080x100x200x400x80 $27 $47 $26 $46 0x010x020x040x080x80 $25 $45 0x010x020x040x080x100x200x400x80 $24 $44 0x010x020x040x080x100x200x400x80 $23 $43 0x010x80 $22 $42 0x400x80 $21 $41 0x010x020x040x080x100x200x400x80 $20 $40 0x010x020x040x08 $1F $3F 0x01 $1E $3E 0x010x020x040x080x100x200x400x80 $1D $3D 0x010x020x040x080x100x200x400x80 $1C $3C 0x010x020x040x080x100x20 $1B $3B 0x010x020x040x080x100x200x400x80 $1A $3A 0x010x020x040x080x100x200x400x80 $19 $39 0x010x020x040x080x100x200x400x80 $18 $38 0x010x020x040x08 $17 $37 0x010x020x040x08 $16 $36 0x010x020x040x08 $15 $35 0x010x020x040x080x100x200x400x80 $14 $34 0x010x020x040x080x100x200x400x80 $13 $33 0x010x020x040x080x100x200x400x80 $12 $32 0x010x020x040x080x100x200x400x80 $10 $30 0x010x020x040x080x100x200x400x80 $0F $2F 0x010x020x040x080x100x200x400x80 $0E $2E 0x010x020x040x080x100x200x400x80 $0D $2D 0x010x020x040x080x100x200x400x80 $0C $2C 0x010x020x040x20 $0B $2B 0x010x020x040x20 $08 $28 0x010x020x040x080x100x200x400x80 $07 $27 0x010x020x040x080x100x200x400x80 $06 $26 0x010x020x040x080x100x200x400x80 $05 $25 0x010x020x040x080x100x200x400x80 $04 $24 0x010x020x040x080x100x200x400x80 $03 $23 0x400x010x020x040x100x80 $01 $21 0x010x020x040x080x100x200x400x80 $00 $20 0x010x020x040x08 $0 $FFF $0 $0 32 0xff,0xdf, 0x01 0xff,0xdf, 0x01 1,0x20,0x20,WARNING! These fuse settings will disable the ISP interface! 1,0x40,0x00,WARNING! Enabling DEBUGWIRE will make the ISP interface inaccessible! 1,0x80,0x00,WARNING! Disabling external reset will make the ISP interface inaccessible! 1,0x20,0x20,WARNING! These fuse settings will disable the ISP interface! 1,0x40,0x00,WARNING! Enabling DEBUGWIRE will make the ISP interface inaccessible! 1,0x80,0x00,WARNING! Disabling external reset will make the ISP interface inaccessible! 0x00,8.0 MHz 64 4 [PORTA:PORTB:ANALOG_COMPARATOR:AD_CONVERTER:USI:EXTERNAL_INTERRUPT:EEPROM:WATCHDOG:TIMER_COUNTER_0:TIMER_COUNTER_1:BOOT_LOAD:CPU] [PORTA:DDRA:PINA] io_port.bmp AVRSimIOPort.SimIOPort PORTA Port A Data Register $1B $3B io_port.bmp N PORTA7 Port A Data Register bit 7 RW 0 PORTA6 Port A Data Register bit 6 RW 0 PORTA5 Port A Data Register bit 5 RW 0 PORTA4 Port A Data Register bit 4 RW 0 PORTA3 Port A Data Register bit 3 RW 0 PORTA2 Port A Data Register bit 2 RW 0 PORTA1 Port A Data Register bit 1 RW 0 PORTA0 Port A Data Register bit 0 RW 0 DDRA Port A Data Direction Register $1A $3A io_flag.bmp N DDA7 Data Direction Register, Port A, bit 7 RW 0 DDA6 Data Direction Register, Port A, bit 6 RW 0 DDA5 Data Direction Register, Port A, bit 5 RW 0 DDA4 Data Direction Register, Port A, bit 4 RW 0 DDA3 Data Direction Register, Port A, bit 3 RW 0 DDA2 Data Direction Register, Port A, bit 2 RW 0 DDA1 Data Direction Register, Port A, bit 1 RW 0 DDA0 Data Direction Register, Port A, bit 0 RW 0 PINA Port A Input Pins The Port A Input Pins address - PINA - is not a register, and this address enables access to the physical value on each Port A pin. When reading PORTA the Port A Data Latch is read, and when reading PINA, the logical values present on the pins are read. $19 $39 io_port.bmp N PINA7 Input Pins, Port A bit 7 RW Hi-Z PINA6 Input Pins, Port A bit 6 RW Hi-Z PINA5 Input Pins, Port A bit 5 RW Hi-Z PINA4 Input Pins, Port A bit 4 RW Hi-Z PINA3 Input Pins, Port A bit 3 RW Hi-Z PINA2 Input Pins, Port A bit 2 RW Hi-Z PINA1 Input Pins, Port A bit 1 RW Hi-Z PINA0 Input Pins, Port A bit 0 RW Hi-Z [PORTB:DDRB:PINB] io_port.bmp AVRSimIOPort.SimIOPort PORTB Data Register, Port B $18 $38 io_port.bmp N PORTB3 RW 0 PORTB2 RW 0 PORTB1 RW 0 PORTB0 RW 0 DDRB Data Direction Register, Port B $17 $37 io_flag.bmp N DDB3 RW 0 DDB2 RW 0 DDB1 RW 0 DDB0 RW 0 PINB Input Pins, Port B $16 $36 io_port.bmp N PINB3 R 0 PINB2 R 0 PINB1 R 0 PINB0 R 0 [ADCSRB:ACSR:DIDR0] io_analo.bmp AlgComp_01 ADCSRB ADC Control and Status Register B $03 $23 io_flag.bmp Y ACME Analog Comparator Multiplexer Enable When this bit is written logic one and the ADC is switched off (ADEN in ADCSR is zero), the ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed description of this bit, see “Analog Comparator Multiplexed Input” on page 186. RW 0 ACSR Analog Comparator Control And Status Register $08 $28 io_analo.bmp Y ACD Analog Comparator Disable When this bit is written logic one, the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed. RW 0 ACBG AINBG Analog Comparator Bandgap Select When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. See “Internal Voltage Reference” on page 42. RW 0 ACO Analog Compare Output The output of the analog comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1-2 clock cycles. R NA ACI Analog Comparator Interrupt Flag This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hard-ware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag. RW 0 ACIE Analog Comparator Interrupt Enable When the ACIE bit is written logic one and the I-bit in the Status Register is set, the analog comparator interrupt is acti-vated. When written logic zero, the interrupt is disabled. RW 0 ACIC Analog Comparator Input Capture Enable When written logic one, this bit enables the input capture function in Timer/Counter1 to be triggered by the Analog Comparator. R 0 ACIS1 Analog Comparator Interrupt Mode Select bit 1 These bits determine which comparator events that trigger the Analog Comparator interrupt. RW 0 ACIS0 Analog Comparator Interrupt Mode Select bit 0 These bits determine which comparator events that trigger the Analog Comparator interrupt. RW 0 DIDR0 $01 $21 Y ADC1D ADC 1 Digital input buffer disable When this bit is written logic one,the digital input buffer on the AIN1 pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. RW 0 ADC0D ADC 0 Digital input buffer disable When this bit is written logic one,the digital input buffer on the AIN0 pin is disabled.The corresponding PIN register bit will always read as zero when this bit is set.When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed,this bit should be written logic one to reduce power consumption in the digital input buffer. RW 0 [ADMUX:ADCSRA:ADCH:ADCL:ADCSRB:DIDR0] io_analo.bmp ADMUX ADC Multiplexer Selection Register $07 $27 io_analo.bmp N REFS1 Reference Selection Bit 1 RW 0 REFS0 Reference Selection Bit 0 RW 0 MUX5 Analog Channel and Gain Selection Bit 5 RW 0 MUX4 Analog Channel and Gain Selection Bit 4 RW 0 MUX3 Analog Channel and Gain Selection Bit 3 RW 0 MUX2 Analog Channel and Gain Selection Bit 2 RW 0 MUX1 Analog Channel and Gain Selection Bit 1 RW 0 MUX0 Analog Channel and Gain Selection Bit 0 RW 0 ADCSRA ADC Control and Status Register A $06 $26 io_flag.bmp Y ADEN ADC Enable Writing a logical ‘1’ to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion. RW 0 ADSC ADC Start Conversion In Single Conversion Mode, a logical ‘1’ must be written to this bit to start each conversion. In Free Running Mode, a logical ‘1’ must be written to this bit to start the first conversion. The first time ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, an extended conversion will result. This extended conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. When a dummy conversion precedes a real conversion, ADSC will stay high until the real conversion completes. Writing a 0 to this bit has no effec RW 0 ADATE ADC Auto Trigger Enable When this bit is written to one,Auto Triggering of the ADC is enabled.The ADC will start a conversion on a positive edge of the selected trigger signal.The trigger source is selected by setting the ADC Trigger Select bits,ADTS in ADCSRB. RW 0 ADIF ADC Interrupt Flag This bit is set (one) when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set (one). ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a read-modify-write on ADCSR, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used. RW 0 ADIE ADC Interrupt Enable When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Complete Interrupt is activated. RW 0 ADPS2 ADC Prescaler Select Bit 2 These bits determine the division factor between the XTAL frequency and the input clock to the ADC. RW 0 ADPS1 ADC Prescaler Select Bit 1 These bits determine the division factor between the XTAL frequency and the input clock to the ADC. RW 0 ADPS0 ADC Prescaler Select Bit 0 These bits determine the division factor between the XTAL frequency and the input clock to the ADC. RW 0 ADCH ADC Data Register High Byte When an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. The selected channel is differential if MUX4..0 are between ‘01000’ and ‘11101’, otherwise the selected channel is single ended. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8 bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUX4..0 bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right $05 $25 io_analo.bmp N ADCH7 ADC Data Register High Byte Bit 7 RW 0 ADCH6 ADC Data Register High Byte Bit 6 RW 0 ADCH5 ADC Data Register High Byte Bit 5 RW 0 ADCH4 ADC Data Register High Byte Bit 4 RW 0 ADCH3 ADC Data Register High Byte Bit 3 RW 0 ADCH2 ADC Data Register High Byte Bit 2 RW 0 ADCH1 ADC Data Register High Byte Bit 1 RW 0 ADCH0 ADC Data Register High Byte Bit 0 RW 0 ADCL ADC Data Register Low Byte When an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. The selected channel is differential if MUX4..0 are between ‘01000’ and ‘11101’, otherwise the selected channel is single ended. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8 bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUX4..0 bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right $04 $24 io_analo.bmp N ADCL7 ADC Data Register Low Byte Bit 7 RW 0 ADCL6 ADC Data Register Low Byte Bit 6 RW 0 ADCL5 ADC Data Register Low Byte Bit 5 RW 0 ADCL4 ADC Data Register Low Byte Bit 4 RW 0 ADCL3 ADC Data Register Low Byte Bit 3 RW 0 ADCL2 ADC Data Register Low Byte Bit 2 RW 0 ADCL1 ADC Data Register Low Byte Bit 1 RW 0 ADCL0 ADC Data Register Low Byte Bit 0 RW 0 ADCSRB ADC Control and Status Register B $03 $23 io_analo.bmp Y BIN Bipolar Input Mode The gain stage is working in the unipolar mode as default, but the bipolar mode can be selected by writing the BIN bit in the ADCSRB register. R 0 ADLAR ADC Left Adjust Result RW 0 ADTS2 ADC Auto Trigger Source bit 2 If ADATE in ADCSRA is written to one,the value of these bits selects which source will trigger an ADC conversion.If ADATE is cleared,the ADTS2:0 settings will have no effect.A conversion will be triggered by the rising edge of the selected interrupt flag.Note that switching from a trigger source that is cleared to a trigger source that is set,will generate a positive edge on the trigger signal.If ADEN in ADCSRA is set,this will start a conversion.Switching to Free Running Mode (ADTS [2:0 ]=0)will not cause a trigger event,even if the ADC Interrupt Flag is set . RW 0 ADTS1 ADC Auto Trigger Source bit 1 If ADATE in ADCSRA is written to one,the value of these bits selects which source will trigger an ADC conversion.If ADATE is cleared,the ADTS2:0 settings will have no effect.A conversion will be triggered by the rising edge of the selected interrupt flag.Note that switching from a trigger source that is cleared to a trigger source that is set,will generate a positive edge on the trigger signal.If ADEN in ADCSRA is set,this will start a conversion.Switching to Free Running Mode (ADTS [2:0 ]=0)will not cause a trigger event,even if the ADC Interrupt Flag is set . RW 0 ADTS0 ADC Auto Trigger Source bit 0 If ADATE in ADCSRA is written to one,the value of these bits selects which source will trigger an ADC conversion.If ADATE is cleared,the ADTS2:0 settings will have no effect.A conversion will be triggered by the rising edge of the selected interrupt flag.Note that switching from a trigger source that is cleared to a trigger source that is set,will generate a positive edge on the trigger signal.If ADEN in ADCSRA is set,this will start a conversion.Switching to Free Running Mode (ADTS [2:0 ]=0)will not cause a trigger event,even if the ADC Interrupt Flag is set . RW 0 DIDR0 Digital Input Disable Register 0 $01 $21 io_analo.bmp N ADC7D ADC7 Digital Input Disable RW 0 ADC6D ADC6 Digital Input Disable RW 0 ADC5D ADC5 Digital Input Disable RW 0 ADC4D ADC4 Digital Input Disable RW 0 ADC3D ADC3 Digital Input Disable RW 0 ADC2D ADC2 Digital Input Disable RW 0 ADC1D ADC1 Digital Input Disable RW 0 ADC0D ADC0 Digital Input Disable RW 0 [USIBR:USIDR:USISR:USICR] io_com.bmp Universal Serial Interface USIBR USI Buffer Register $10 $30 io_com.bmp N USIBR7 USI Buffer Register bit 7 R 0 USIBR6 USI Buffer Register bit 6 R 0 USIBR5 USI Buffer Register bit 5 R 0 USIBR4 USI Buffer Register bit 4 R 0 USIBR3 USI Buffer Register bit 3 R 0 USIBR2 USI Buffer Register bit 2 R 0 USIBR1 USI Buffer Register bit 1 R 0 USIBR0 USI Buffer Register bit 0 R 0 USIDR USI Data Register $0F $2F io_com.bmp N USIDR7 USI Data Register bit 7 RW 0 USIDR6 USI Data Register bit 6 RW 0 USIDR5 USI Data Register bit 5 RW 0 USIDR4 USI Data Register bit 4 RW 0 USIDR3 USI Data Register bit 3 RW 0 USIDR2 USI Data Register bit 2 RW 0 USIDR1 USI Data Register bit 1 RW 0 USIDR0 USI Data Register bit 0 RW 0 USISR USI Status Register $0E $2E io_flag.bmp Y USISIF Start Condition Interrupt Flag RW 0 USIOIF Counter Overflow Interrupt Flag RW 0 USIPF Stop Condition Flag RW 1 USIDC Data Output Collision RW 0 USICNT3 USI Counter Value Bit 3 RW 0 USICNT2 USI Counter Value Bit 2 RW 0 USICNT1 USI Counter Value Bit 1 RW 0 USICNT0 USI Counter Value Bit 0 RW 0 USICR USI Control Register $0D $2D io_flag.bmp Y USISIE Start Condition Interrupt Enable RW 0 USIOIE Counter Overflow Interrupt Enable RW 0 USIWM1 USI Wire Mode Bit 1 RW 1 USIWM0 USI Wire Mode Bit 0 RW 0 USICS1 USI Clock Source Select Bit 1 RW 0 USICS0 USI Clock Source Select Bit 0 RW 0 USICLK Clock Strobe R 0 USITC Toggle Clock Port Pin W 0 [MCUCR:GIMSK:GIFR:PCMSK1:PCMSK0] io_ext.bmp MCUCR MCU Control Register $35 $55 io_cpu.bmp Y ISC01 Interrupt Sense Control 0 Bit 1 RW 0 ISC00 Interrupt Sense Control 0 Bit 0 RW 0 GIMSK GICR General Interrupt Mask Register $3B $5B io_flag.bmp Y INT0 External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from program memory address $001. See also “External Interrupts.” • Bits 5..0 - Res: Reserved bits RW 0 PCIE1 Pin Change Interrupt Enable 1 RW 0 PCIE0 Pin Change Interrupt Enable 0 RW 0 GIFR General Interrupt Flag register $3A $5A io_flag.bmp Y INTF0 External Interrupt Flag 0 When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the interrupt vector at address $001. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. RW 0 PCIF1 Pin Change Interrupt Flag 1 RW 0 PCIF0 Pin Change Interrupt Flag 0 RW 0 PCMSK1 Pin Change Enable Mask 1 $20 $40 io_flag.bmp N PCINT11 Pin Change Enable Mask Bit 11 RW 1 PCINT10 Pin Change Enable Mask Bit 10 RW 1 PCINT9 Pin Change Enable Mask Bit 9 RW 1 PCINT8 Pin Change Enable Mask Bit 8 RW 1 PCMSK0 Pin Change Enable Mask 0 $12 $32 io_flag.bmp N PCINT7 Pin Change Enable Mask Bit 7 RW 1 PCINT6 Pin Change Enable Mask Bit 6 RW 1 PCINT5 Pin Change Enable Mask Bit 5 RW 1 PCINT4 Pin Change Enable Mask Bit 4 RW 1 PCINT3 Pin Change Enable Mask Bit 3 RW 1 PCINT2 Pin Change Enable Mask Bit 2 RW 1 PCINT1 Pin Change Enable Mask Bit 1 RW 1 PCINT0 Pin Change Enable Mask Bit 0 RW 1 [EEARL:EEARH:EEDR:EECR] io_cpu.bmp EEPROM Read/Write Access. The EEPROM access registers are accessible in the I/O space. The write access time for the EEPROM is given in Table 1. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V CC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page 19. for details on how to avoid problems in these situations.In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When theEEPROM is written, the CPU is halted for two clock cycles before the next instruction is execut EEARH EEPROM Address Register High Byte $1F $3F io_cpu.bmp N EEAR8 EEPROM Read/Write Access Bit 0 RW 0 EEARL EEPROM Address Register Low Byte $1E $3E io_cpu.bmp N EEAR7 EEPROM Read/Write Access Bit 7 RW 0 EEAR6 EEPROM Read/Write Access Bit 6 RW 0 EEAR5 EEPROM Read/Write Access Bit 5 RW 0 EEAR4 EEPROM Read/Write Access Bit 4 RW 0 EEAR3 EEPROM Read/Write Access Bit 3 RW 0 EEAR2 EEPROM Read/Write Access Bit 2 RW 0 EEAR1 EEPROM Read/Write Access Bit 1 RW 0 EEAR0 EEPROM Read/Write Access Bit 0 RW 0 EEDR EEPROM Data Register For the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR. $1D $3D io_cpu.bmp N EEDR7 EEPROM Data Register bit 7 RW 0 EEDR6 EEPROM Data Register bit 6 RW 0 EEDR5 EEPROM Data Register bit 5 RW 0 EEDR4 EEPROM Data Register bit 4 RW 0 EEDR3 EEPROM Data Register bit 3 RW 0 EEDR2 EEPROM Data Register bit 2 RW 0 EEDR1 EEPROM Data Register bit 1 RW 0 EEDR0 EEPROM Data Register bit 0 RW 0 EECR EEPROM Control Register $1C $3C io_flag.bmp Y EEPM1 EEPROM Programming Mode Bit 1 The EEPROM Programming mode bit setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in Table 2. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming. RW X EEPM0 EEPROM Programming Mode Bit 0 The EEPROM Programming mode bit setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in Table 2. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming. RW X EERIE EEPROM Ready Interrupt Enable EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared. RW 0 EEMPE EEPROM Master Write Enable The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is written to one, writing EEWE to one within 4 clock cycles will write data to the EEPROM at the selected address. If EEMWE is zero, writing EEWE to one will have no effect. When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure. RW 0 EEPE EEPROM Write Enable The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential): 1. Wait until EEWE becomes zero. 2. Wait until SPMEN in SPMCR becomes zero. 3. Write new EEPROM address to EEAR (optional). 4. Write new EEPROM data to EEDR (optional). 5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR. 6. Within four clock cycles after setting EEMWE, write a logical one to EEWE. The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a boot loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See “Boot Loader Support - Read While Write self-programming” on page 228 for details about boot programming. Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR regis-ter will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the 4 last steps to avoid these problems. When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruc-tion is executed RW X EERE EEPROM Read Enable The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR register. The calibrated oscillator is used to time the EEPROM accesses. Table 1 lists the typical programming time for EEPROM access from the CPU RW 0 [WDTCSR] io_watch.bmp WDTCSR Watchdog Timer Control Register $21 $41 io_flag.bmp Y WDIF Watchdog Timeout Interrupt Flag RW 0 WDIE Watchdog Timeout Interrupt Enable RW 0 WDP3 Watchdog Timer Prescaler Bit 3 RW 0 WDCE Watchdog Change Enable RW 0 WDE Watch Dog Enable When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure must be followed: 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog RW 0 WDP2 Watch Dog Timer Prescaler bit 2 RW 0 WDP1 Watch Dog Timer Prescaler bit 1 RW 0 WDP0 Watch Dog Timer Prescaler bit 0 RW 0 [TIMSK0:TIFR0:TCCR0A:TCCR0B:TCNT0:OCR0A:OCR0B:GTCCR] io_timer.bmp TIMSK0 Timer/Counter Interrupt Mask Register $39 $59 io_flag.bmp Y OCIE0B Timer/Counter0 Output Compare Match B Interrupt Enable RW 0 OCIE0A Timer/Counter0 Output Compare Match A Interrupt Enable RW 0 TOIE0 Timer/Counter0 Overflow Interrupt Enable RW 0 TIFR0 Timer/Counter0 Interrupt Flag Register $38 $58 io_flag.bmp Y OCF0B Timer/Counter0 Output Compare Flag B RW 0 OCF0A Timer/Counter0 Output Compare Flag A RW 0 TOV0 Timer/Counter0 Overflow Flag RW 0 TCCR0A Timer/Counter Control Register A $30 $50 io_flag.bmp Y COM0A1 Compare Match Output A Mode bit 1 RW 0 COM0A0 Compare Match Output A Mode bit 0 RW 0 COM0B1 Compare Match Output B Mode bit 1 W 0 COM0B0 Compare Match Output B Mode bit 0 RW 0 WGM01 Waveform Generation Mode bit 1 RW 0 WGM00 Waveform Generation Mode bit 0 RW 0 TCCR0B Timer/Counter Control Register B $33 $53 io_flag.bmp Y FOC0A Force Output Compare A W 0 FOC0B Force Output Compare B W 0 WGM02 Waveform Generation Mode bit 2 RW 0 CS02 Clock Select bit 2 RW 0 CS01 Clock Select bit 1 RW 0 CS00 Clock Select bit 0 RW 0 TCNT0 Timer/Counter0 The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT0 register blocks (removes) the compare match on the following timer clock. Modifying the counter (TCNT0) while the counter is running, introduces a risk of missing a compare match between TCNT0 the OCR0 register. $32 $52 io_timer.bmp N TCNT0_7 RW 0 TCNT0_6 RW 0 TCNT0_5 RW 0 TCNT0_4 RW 0 TCNT0_3 RW 0 TCNT0_2 RW 0 TCNT0_1 RW 0 TCNT0_0 RW 0 OCR0A Timer/Counter0 Output Compare Register A $36 $56 io_timer.bmp N OCR0_7 RW 0 OCR0_6 RW 0 OCR0_5 RW 0 OCR0_4 RW 0 OCR0_3 RW 0 OCR0_2 RW 0 OCR0_1 RW 0 OCR0_0 RW 0 OCR0B Timer/Counter0 Output Compare Register B $3C $5C io_timer.bmp N OCR0_7 RW 0 OCR0_6 RW 0 OCR0_5 RW 0 OCR0_4 RW 0 OCR0_3 RW 0 OCR0_2 RW 0 OCR0_1 RW 0 OCR0_0 RW 0 GTCCR General Timer/Counter Control Register $23 $43 io_flag.bmp Y TSM Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSR2 and PSR10 bits is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSR2 and PSR10 bits are cleared by hardware, and the Timer/Counters start counting simultaneousl RW 0 PSR10 Prescaler Reset Timer/CounterN When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. RW 0 [TIMSK1:TIFR1:TCCR1A:TCCR1B:TCCR1C:TCNT1H:TCNT1L:OCR1AH:OCR1AL:OCR1BH:OCR1BL:ICR1H:ICR1L] [TCNT1H:TCNT1L];[OCR1AH:OCR1AL];[OCR1BH:OCR1BL];[ICR1H:ICR1L] io_timer.bmp t16pwm1_13.xml TIMSK1 Timer/Counter1 Interrupt Mask Register $0C $2C io_flag.bmp Y ICIE1 Timer/Counter1 Input Capture Interrupt Enable When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on pin ICP, i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR. RW 0 OCIE1B Timer/Counter1 Output Compare B Match Interrupt Enable When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt is executed if a CompareB match in Timer/Counter1 occurs, i.e., when the OCF1B bit is set in the Timer/Counter Interrupt Flag Register - TIFR. RW 0 OCIE1A Timer/Counter1 Output Compare A Match Interrupt Enable When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a CompareA match in Timer/Counter1 occurs, i.e., when the OCF1A bit is set in the Timer/Counter Interrupt Flag Register - TIFR. RW 0 TOIE1 Timer/Counter1 Overflow Interrupt Enable When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR. RW 0 TIFR1 Timer/Counter Interrupt Flag register $0B $2B io_flag.bmp Y ICF1 Timer/Counter1 Input Capture Flag The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to the input capture register - ICR1. ICF1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF1 is cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable), and ICF1 are set (one), the Timer/Counter1 Capture Interrupt is executed. RW 0 OCF1B Timer/Counter1 Output Compare B Match Flag The OCF1B bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1B - Output Compare Register 1B. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare match InterruptB Enable), and the OCF1B are set (one), the Timer/Counter1 Compare B match Interrupt is executed. RW 0 OCF1A Timer/Counter1 Output Compare A Match Flag The OCF1A bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-tively, OCF1A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare match InterruptA Enable), and the OCF1A are set (one), the Timer/Counter1 Compare A match Interrupt is executed. RW 0 TOV1 Timer/Counter1 Overflow Flag The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the cor-responding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter1 changes counting direction at $0000. RW 0 TCCR1A Timer/Counter1 Control Register A $2F $4F io_flag.bmp Y COM1A1 Compare Output Mode 1A, bit 1 The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA pin 1. This is an alternative function to an I/O port and the corresponding direction control bit must be set (one) to control the output pin. The control configuration is shown in the databook. RW 0 COM1A0 Comparet Ouput Mode 1A, bit 0 The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1A - Output CompareA pin 1. This is an alternative function to an I/O port and the corresponding direction control bit must be set (one) to control the output pin. The control configuration is shown in the databook. RW 0 COM1B1 Compare Output Mode 1B, bit 1 RW 0 COM1B0 Comparet Ouput Mode 1B, bit 0 RW 0 WGM11 PWM11 Pulse Width Modulator Select Bit 1 RW 0 WGM10 PWM10 Pulse Width Modulator Select Bit 0 RW 0 TCCR1B Timer/Counter1 Control Register B $2E $4E io_flag.bmp Y ICNC1 Input Capture 1 Noise Canceler When the ICNC1 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the ICP - input capture pin - as specified. When the ICNC1 bit is set (one), four successive samples are measures on the ICP - input capture pin, and all samples must be high/low according to the input capture trigger specification in the ICES1 bit. The actual sampling frequency is XTAL clock frequency. RW 0 ICES1 Input Capture 1 Edge Select While the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the falling edge of the input capture pin - ICP. While the ICES1 bit is set (one), the Timer/Counter1 contents are transferred to the Input Capture Register - ICR1 - on the rising edge of the input capture pin - ICP. RW 0 WGM13 Waveform Generation Mode Bit 3 RW 0 WGM12 CTC1 Waveform Generation Mode Bit 2 RW 0 CS12 Clock Select1 bit 2 RW 0 CS11 Clock Select 1 bit 1 RW 0 CS10 Clock Select bit 0 RW 0 TCCR1C Timer/Counter1 Control Register C $22 $42 io_flag.bmp Y FOC1A Force Output Compare for Channel A The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM mode. However, for ensuring compatibility with future devices, these bits must be set to zero when TCCR1A is written when operating in a PWM mode. When writing a logical one to the FOC1A/FOC1B bit, an immediate compare match is forced on the Waveform Generation unit. The OC1A/OC1B output is changed according to its COM1x1:0 bits setting. Note that the FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the COM1x1:0 bits that determine the effect of the forced compare. A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zero RW 0 FOC1B Force Output Compare for Channel B The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM mode. However, for ensuring compatibility with future devices, these bits must be set to zero when TCCR1A is written when operating in a PWM mode. When writing a logical one to the FOC1A/FOC1B bit, an immediate compare match is forced on the Waveform Generation unit. The OC1A/OC1B output is changed according to its COM1x1:0 bits setting. Note that the FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the COM1x1:0 bits that determine the effect of the forced compare. A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zero RW 0 TCNT1H Timer/Counter1 High Byte This 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR1A, OCR1B and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt ro $2D $4D io_timer.bmp N TCNT1H7 Timer/Counter1 High Byte bit 7 RW 0 TCNT1H6 Timer/Counter1 High Byte bit 6 RW 0 TCNT1H5 Timer/Counter1 High Byte bit 5 RW 0 TCNT1H4 Timer/Counter1 High Byte bit 4 RW 0 TCNT1H3 Timer/Counter1 High Byte bit 3 RW 0 TCNT1H2 Timer/Counter1 High Byte bit 2 RW 0 TCNT1H1 Timer/Counter1 High Byte bit 1 RW 0 TCNT1H0 Timer/Counter1 High Byte bit 0 RW 0 TCNT1L Timer/Counter1 Low Byte This 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR1A, OCR1B and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrup $2C $4C io_timer.bmp N TCNT1L7 Timer/Counter1 Low Byte bit 7 RW 0 TCNT1L6 Timer/Counter1 Low Byte bit 6 RW 0 TCNT1L5 Timer/Counter1 Low Byte bit 5 RW 0 TCNT1L4 Timer/Counter1 Low Byte bit 4 RW 0 TCNT1L3 Timer/Counter1 Low Byte bit 3 RW 0 TCNT1L2 Timer/Counter1 Low Byte bit 2 RW 0 TCNT1L1 Timer/Counter1 Low Byte bit 1 RW 0 TCNT1L0 Timer/Counter1 Low Byte bit 0 RW 0 OCR1AH Timer/Counter1 Output Compare Register A High Byte The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrup $2B $4B io_timer.bmp N OCR1AH7 Timer/Counter1 Output Compare Register High Byte bit 7 RW 0 OCR1AH6 Timer/Counter1 Output Compare Register High Byte bit 6 RW 0 OCR1AH5 Timer/Counter1 Output Compare Register High Byte bit 5 RW 0 OCR1AH4 Timer/Counter1 Output Compare Register High Byte bit 4 RW 0 OCR1AH3 Timer/Counter1 Output Compare Register High Byte bit 3 RW 0 OCR1AH2 Timer/Counter1 Output Compare Register High Byte bit 2 RW 0 OCR1AH1 Timer/Counter1 Output Compare Register High Byte bit 1 RW 0 OCR1AH0 Timer/Counter1 Output Compare Register High Byte bit 0 RW 0 OCR1AL Timer/Counter1 Output Compare Register A Low Byte The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interru $2A $4A io_timer.bmp N OCR1AL7 Timer/Counter1 Output Compare Register Low Byte Bit 7 RW 0 OCR1AL6 Timer/Counter1 Output Compare Register Low Byte Bit 6 RW 0 OCR1AL5 Timer/Counter1 Output Compare Register Low Byte Bit 5 RW 0 OCR1AL4 Timer/Counter1 Output Compare Register Low Byte Bit 4 RW 0 OCR1AL3 Timer/Counter1 Output Compare Register Low Byte Bit 3 RW 0 OCR1AL2 Timer/Counter1 Output Compare Register Low Byte Bit 2 RW 0 OCR1AL1 Timer/Counter1 Output Compare Register Low Byte Bit 1 RW 0 OCR1AL0 Timer/Counter1 Output Compare Register Low Byte Bit 0 RW 0 OCR1BH Timer/Counter1 Output Compare Register B High Byte The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrup $29 $49 io_timer.bmp N OCR1AH7 Timer/Counter1 Output Compare Register High Byte bit 7 RW 0 OCR1AH6 Timer/Counter1 Output Compare Register High Byte bit 6 RW 0 OCR1AH5 Timer/Counter1 Output Compare Register High Byte bit 5 RW 0 OCR1AH4 Timer/Counter1 Output Compare Register High Byte bit 4 RW 0 OCR1AH3 Timer/Counter1 Output Compare Register High Byte bit 3 RW 0 OCR1AH2 Timer/Counter1 Output Compare Register High Byte bit 2 RW 0 OCR1AH1 Timer/Counter1 Output Compare Register High Byte bit 1 RW 0 OCR1AH0 Timer/Counter1 Output Compare Register High Byte bit 0 RW 0 OCR1BL Timer/Counter1 Output Compare Register B Low Byte The output compare registers are 16-bit read/write registers. The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status register.A compare match does only occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does not generate a compare match. A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event. Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation. The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interru $28 $48 io_timer.bmp N OCR1AL7 Timer/Counter1 Output Compare Register Low Byte Bit 7 RW 0 OCR1AL6 Timer/Counter1 Output Compare Register Low Byte Bit 6 RW 0 OCR1AL5 Timer/Counter1 Output Compare Register Low Byte Bit 5 RW 0 OCR1AL4 Timer/Counter1 Output Compare Register Low Byte Bit 4 RW 0 OCR1AL3 Timer/Counter1 Output Compare Register Low Byte Bit 3 RW 0 OCR1AL2 Timer/Counter1 Output Compare Register Low Byte Bit 2 RW 0 OCR1AL1 Timer/Counter1 Output Compare Register Low Byte Bit 1 RW 0 OCR1AL0 Timer/Counter1 Output Compare Register Low Byte Bit 0 RW 0 ICR1H Timer/Counter1 Input Capture Register High Byte The input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES1) of the signal at the input capture pin -ICP - is detected, the current value of the Timer/Counter1 is transferred to the Input Capture Register - ICR1. At the same time, the input capture flag - ICF1 - is set (one). Since the Input Capture Register - ICR1 - is a 16-bit register, a temporary register TEMP is used when ICR1 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR1L, the data is sent to the CPU and the data of the high byte ICR1H is placed in the TEMP register. When the CPU reads the data in the high byte ICR1H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR1L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT1, OCR1A and OCR1B. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrup $25 $45 io_timer.bmp N ICR1H7 Timer/Counter1 Input Capture Register High Byte bit 7 RW 0 ICR1H6 Timer/Counter1 Input Capture Register High Byte bit 6 R 0 ICR1H5 Timer/Counter1 Input Capture Register High Byte bit 5 R 0 ICR1H4 Timer/Counter1 Input Capture Register High Byte bit 4 R 0 ICR1H3 Timer/Counter1 Input Capture Register High Byte bit 3 R 0 ICR1H2 Timer/Counter1 Input Capture Register High Byte bit 2 R 0 ICR1H1 Timer/Counter1 Input Capture Register High Byte bit 1 R 0 ICR1H0 Timer/Counter1 Input Capture Register High Byte bit 0 R 0 ICR1L Timer/Counter1 Input Capture Register Low Byte The input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES1) of the signal at the input capture pin -ICP - is detected, the current value of the Timer/Counter1 is transferred to the Input Capture Register - ICR1. At the same time, the input capture flag - ICF1 - is set (one). Since the Input Capture Register - ICR1 - is a 16-bit register, a temporary register TEMP is used when ICR1 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR1L, the data is sent to the CPU and the data of the high byte ICR1H is placed in the TEMP register. When the CPU reads the data in the high byte ICR1H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR1L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT1, OCR1A and OCR1B. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within inte $24 $44 io_timer.bmp N ICR1L7 Timer/Counter1 Input Capture Register Low Byte bit 7 R 0 ICR1L6 Timer/Counter1 Input Capture Register Low Byte bit 6 R 0 ICR1L5 Timer/Counter1 Input Capture Register Low Byte bit 5 R 0 ICR1L4 Timer/Counter1 Input Capture Register Low Byte bit 4 R 0 ICR1L3 Timer/Counter1 Input Capture Register Low Byte bit 3 R 0 ICR1L2 Timer/Counter1 Input Capture Register Low Byte bit 2 R 0 ICR1L1 Timer/Counter1 Input Capture Register Low Byte bit 1 R 0 ICR1L0 Timer/Counter1 Input Capture Register Low Byte bit 0 R 0 [SPMCSR] io_cpu.bmp The Boot Loader Support provides a real Read While Write self-programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program. The Boot Loader program can use any available data interface and associated proto-col to read code and write (program) that code into the Flash memory, or read the code from the program memory. The program code within the Boot Loader section has the capability to write into the entire Flash, including the Boot Loader Memory. The Boot Loader can thus even modify itself, and it can also erase itself from the code if the feature is not needed anymore. The size of the Boot Loader Memory is configurable with fuses and the Boot Loader has two separate sets of Boot Lock Bits which can be set independently. This gives the user a unique flexibility to select different levels of protection. Boot Loader Features: Read While Write self-programming. Flexibl Boot Memory size. High security (separate Boot Lock bits for a flexible protection). Separate fuse to select reset vector Optimized page (1) size. Code efficient algorithm Efficient read-modify-write suppo SPMCSR Store Program Memory Control Register The Store Program Memory Control Register contains the control bits needed to control the Boot Loader operations. $37 $57 io_flag.bmp Y CTPB Clear temporary page buffer RW 0 RFLB Read fuse and lock bits RW 0 PGWRT Page Write If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPM instruction is exe-cuted within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed. RW 0 PGERS Page Erase If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page erase. The page address is taken from the high part of the Z pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a page erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed. RW 0 SPMEN Store Program Memory Enable This bit enables the SPM instruction for the next four clock cycles. If written to one together with either RWWSRE, BLB-SET, PGWRT or PGERS, the following SPM instruction will have a special meaning, see description above. If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z pointer. The LSB of the Z pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During page erase and page write, the SPMEN bit remain high until the operation is completed. Writing any other combination than “10001”, "01001", "00101", "00011" or "00001" in the lower five bits will have no eff RW 0 [SREG:SPH:SPL:MCUCR:MCUSR:OSCCAL:GPIOR2:GPIOR1:GPIOR0:PRR:CLKPR] [SPH:SPL] io_cpu.bmp PRR Power Reduction Register $00 $20 io_cpu.bmp Y PRTIM1 Power Reduction Timer/Counter1 R/W 0 PRTIM0 Power Reduction Timer/Counter0 R/W 0 PRUSI Power Reduction USI R/W 0 PRADC Power Reduction ADC R/W 0 OSCCAL Oscillator Calibration Value Writing the calibration byte to this address will trim the internal oscillator to remove process variations from the oscillator frequency. This is done automatically during chip reset. When OSCCAL is zero, the lowest available frequency is chosen. Writing non-zero values to this register will increase the frequency of the internal oscillator. Writing $FF to the register gives the highest available frequency. The calibrated oscillator is used to time EEPROM and Flash access. If EEPROM or Flash is written, do not calibrate to more than 10% above the nominal frequency. Otherwise, the EEPROM or Flash write may fail. Note that the Oscillator is intended for calibration to 1.0 MHz, 2.0 MHz, 4.0 MHz, or 8.0MHz. Tuning to other values is not guaranteed, as indicated in Table 14 $31 $51 io_cpu.bmp N CAL7 Oscillator Calibration Value Bit7 R/W 0 CAL6 Oscillator Calibration Value Bit6 R/W 0 CAL5 Oscillator Calibration Value Bit5 R/W 0 CAL4 Oscillator Calibration Value Bit4 R/W 0 CAL3 Oscillator Calibration Value Bit3 R/W 0 CAL2 Oscillator Calibration Value Bit2 R/W 0 CAL1 Oscillator Calibration Value Bit1 R/W 0 CAL0 Oscillator Calibration Value Bit0 R/W 0 CLKPR Clock Prescale Register $26 $46 io_flag.bmp Y CLKPCE Clock Prescaler Change Enable The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is cleared by hardware four cycles after it is written or when CLKPS bits are written. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the CLKPCE bit. RW 0 CLKPS3 Clock Prescaler Select Bit 3 These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. RW 0 CLKPS2 Clock Prescaler Select Bit 2 These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. RW 0 CLKPS1 Clock Prescaler Select Bit 1 These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. RW 0 CLKPS0 Clock Prescaler Select Bit 0 These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. RW 0 SREG Status Register $3F $5F io_sreg.bmp Y I Global Interrupt Enable The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable bit is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. RW 0 T Bit Copy Storage The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction. RW 0 H Half Carry Flag The half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed information. RW 0 S Sign Bit The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruc-tion Set Description for detailed information. RW 0 V Two's Complement Overflow Flag The two’s complement overflow flag V supports two’s complement arithmetics. See the Instruction Set Description for detailed information. RW 0 N Negative Flag The negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information. RW 0 Z Zero Flag The zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information. RW 0 C Carry Flag The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software. RW 0 SPH Stack Pointer High The general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the AT90S4414/8515 supports up to 64 kB external SRAM, all 16-bits are used. The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or return from interrupt R $3E $5E io_sph.bmp N SP9 Stack pointer bit 9 RW 0 SP8 Stack pointer bit 8 RW 0 SPL Stack Pointer Low The general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the AT90S4414/8515 supports up to 64 kB external SRAM, all 16-bits are used. The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or return from interrupt $3D $5D io_sph.bmp N SP7 Stack pointer bit 7 RW 0 SP6 Stack pointer bit 6 RW 0 SP5 Stack pointer bit 5 RW 0 SP4 Stack pointer bit 4 RW 0 SP3 Stack pointer bit 3 RW 0 SP2 Stack pointer bit 2 RW 0 SP1 Stack pointer bit 1 RW 0 SP0 Stack pointer bit 0 RW 0 MCUCR MCU Control Register The MCU Control Register contains control bits for general MCU functions. $35 $55 io_flag.bmp Y PUD RW 0 SE Sleep Enable RW 0 SM1 Sleep Mode Select Bit 1 RW 0 SM0 Sleep Mode Select Bit 0 RW 0 MCUSR MCU Status Register The MCU Status Register provides information on which reset source caused an MCU reset. $34 $54 io_flag.bmp Y WDRF Watchdog Reset Flag This bit is set if a watchdog reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag. RW 0 BORF Brown-out Reset Flag This bit is set if a brown-out reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag. R/W 0 EXTRF External Reset Flag This bit is set if an external reset occurs. The bit is reset by a power-on reset, or by writing a logic zero to the flag. R/W 0 PORF Power-on reset flag This bit is set if a power-on reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the reset flags to identify a reset condition, the user should read and then reset the MCUCSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags. R/W 0 GPIOR2 General Purpose I/O Register 2 $15 $35 io_flag.bmp N GPIOR27 RW 0 GPIOR26 RW 0 GPIOR25 RW 0 GPIOR24 RW 0 GPIOR23 GPIOR22 RW 0 GPIOR21 RW 0 GPIOR20 RW 0 GPIOR1 General Purpose I/O Register 1 $14 $34 io_flag.bmp N GPIOR17 RW 0 GPIOR16 RW 0 GPIOR15 RW 0 GPIOR14 RW 0 GPIOR13 GPIOR12 RW 0 GPIOR11 RW 0 GPIOR10 RW 0 GPIOR0 General Purpose I/O Register 0 $13 $33 io_flag.bmp N GPIOR07 RW 0 GPIOR06 RW 0 GPIOR05 RW 0 GPIOR04 RW 0 GPIOR03 GPIOR02 RW 0 GPIOR01 RW 0 GPIOR00 RW 0 [SIMULATOR:ICE50:STK500_2:AVRISPmkII:JTAGICEmkII] AVRSimCoreV2.SimCoreV2 AVRSimMemory8bit.SimMemory8bit AVRSimInterrupt.SimInterrupt 0x0e 0 10 AVRSimIOPort.SimIOPort Y AVRSimIOPort.SimIOPort Y AVRSimIOExtInterrupt.SimIOExtInterrupt 0x01 0x3b 0x40 0x3a 0x40 0x16 0x04 0x35 0x03 AVRSimIOPinChangeInterrupt.SimIOPinChangeInterrupt 0x02 0x3B 0x10 0x3A 0x10 0x12 0x19 0xFF AVRSimIOPinChangeInterrupt.SimIOPinChangeInterrupt 0x03 0x3B 0x20 0x3A 0x20 0x20 0x16 0x0F AVRSimAC.SimIOAC 0x0C AVRSimADC.SimADC 0x0D AvrSimIOTim8pwmsync2.tim8pwmsync2 0x0B 0x09 0x0A PORTB 2 PORTA 7 PORTB 2 AvrMasterTimer.MasterTimer 0x05 0x06 0x07 0x08 0x19 0x10 0x19 0x80 0x19 0x40 0x19 0x20 TIFR1/OCF1A TIFR1/OCF1B 1:8:64:256:1024 0x05 0x0F 0x0F 0x0F 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x05 0x0F 0x0F 0x05 0x15 0x14 0x14 0x0000025F 0x00000000 0x00000000 0x00000000 0x000001FF 0x00001FFF 0x00000FFF 0x00000FFF 0x00000FFF 0x00000FFF 0x0000025F 0x0000FFFF 0x000001FF 0x00000000 0x00000000 0x00000000 0x0023FFFF 0x00000FFF 0x0000005F 0xFE 0xDF 0x62 0xff 0x51 0xC7 ATtiny24.bin 0x02 0x00 1000000 20000000 7 2 ; INTOSC = 1, INTRC=2;EXTCLK=4 1 ;NOTUSE = 1, EXTERNAL = 4, INTERNAL = 2 1 0 0x01 0x00 0x00 8 0x80 0x00000040 0x00000000 CKOUT fuse 0x00000040 0x00000040 CKOUT fuse 0x00010000 0x00000000 SELFPRGEN Fuse 0x00010000 0x00010000 SELFPRGEN Fuse 0x00000031 0x00000000 258CK, 14CK +4.1ms 0x00000031 0x00000010 258CK, 14CK +65ms 0x00000031 0x00000020 1kCK, 14CK 0x00000031 0x00000030 1kCK, 14CK +4.1ms 0x00000031 0x00000001 1kCK, 14CK +65ms 0x00000031 0x00000011 16kCK, 14CK 0x00000031 0x00000021 16kCK, 14CK +4.1ms 0x00000031 0x00000031 16kCK, 14CK +65ms 0x00000030 0x00000000 6 CK, 14CK 0x00000030 0x00000010 6 CK, 14CK+4ms 0x00000030 0x00000020 6 CK, 14CK+64 ms 0x00000030 0x00000000 6 CK, 14CK 0x00000030 0x00000010 6 CK, 14CK+4ms 0x00000030 0x00000020 6 CK, 14CK+64 ms 0x0000000e 0x0000000e 0x0000000f 0x00000002 8 0x0000000f 0x00000000 0x00001000 0x00000000 Watchdog always ON 0x00001000 0x00001000 Watchdog disabled 0x00008000 0x00000000 RSTDSBL Fuse 0x00008000 0x00008000 RSTDSBL 8 0x00000080 0x00000000 CKDIV8 Fuse 0x00000080 0x00000080 CKDIV8 0x00000700 0x00000700 BOD disabled 0x00000700 0x00000600 BOD enabled, 1.8 V 0x00000700 0x00000500 BOD enabled, 2.7 V 0x00000700 0x00000400 BOD enabled, 4.3 V 2001002532030x53114510x4164100x400x4C0x000x000x000x414100xC10xC20x000x000x0025625644440x4C 0x0C 0x1C 0x2C 0x3C 0x64 0x74 0x66 0x68 0x78 0x68 0x68 0x7A 0x6A 0x68 0x78 0x78 0x7D 0x6D 0x0C 0x80 0x40 0x20 0x10 0x11 0x08 0x04 0x02 0x03 0x08 0x04 0x0F10006112510100254000x0D25652560x0525652562525 0x930C DebugWire 0xFB,0xF9,0xFD,0xFF,0x7F,0xFF,0xFF,0xFF 0x8B,0xB0,0xFC,0xFF,0x7D,0xFF,0xFD,0xFA 0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00 0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 0x00 0X00 0X00 64 4 0x0000 0x0000 0x0000 0x0000 0x0000 0x00 0x2000 0x0000,32 0x0020,64 0x00 0x40 0x00 0x00 0x20 0x00 0xBB,0xFF,0xBB,0xEE,0xBB,0xCC,0xB2,0x0D,0xBC,0x07,0xB4,0x07,0xBA,0x0D,0xBB,0xBC,0x99,0xE1,0xBB,0xAC 0xB4,0x07,0x17 0x3e 0x3d 0x27 0x00 0x00 0x00 0x00 0x00 0x1c